DOCUMENT NUMBER 9S12B128DGV1/D
MC9S12B128 Device User Guide V01.13 Covers also preliminary MC9S12B64 using MC9S12B128 die
Original Release Date: 22 Nov 2002 Revised: 05 Jul 2005
Semiconductor Products Sector Motorola, Inc.
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer. ©Motorola, Inc., 2001
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DOCUMENT NUMBER 9S12B128DGV1/D
Revision History
Version Revision Effective Number Date Date
V01.00 V01.01 V01.02 V01.03 V01.04 20 NOV 2002 27 JAN 2003 24 FEB 2003 18MAR 2003 05MAY 2003 20 JUN 2003 20 NOV 2002 01 FEB 2003 24 FEB 2003 18 MAR 2003 05 MAY 2003 20 JUN 2003
Author
Description of Changes
Initial version based on MC9S12DGJ64-1.10 Version. updated Table 0-1; added submodule configuration in Section 6 & Section 11. Updated memory map $0118-$011B updated Table 0-1; updated section 2.2.28; Updated memory map $0101. added the IIC to the document; added for B64 more details in the preface and the according “Memory Map out of Reset” Updated bus frequency in Table A-4; updated numbers in A.3.1.2 and A.3.1.3 Updated B64 details. Corrected numbering in Table A-26. Replaced references to HCS12 Core Guide by the individual HCS12 Block guides. Table 2-1 corrected pullrresistor reset state PE4-PE2. Table A-1 corrected footnote on clamp of TEST pin. Updated Section 11, Section 15, A.5.2 Oscillator Table A-15 corrected Num 9 and 10. Added Table 0-2 and note at Section 8.1 Updated Table 1-3 Updated Table 0-5, row 6 of Table A-15 Added Table 0-3, updated Figure 0-1 and Table 1-3 Added Table 0-4; updated Table 1-3; added Note in Section 11; row 5 & 6 of Table A-7; row 4 & 7 Table A-17; A.5.1.5; A.5.1.6; Table A-20 row 13 & 14 Updated Figure 0-1. Updated Table A-10 and Table A-11. Updated Table A-16 and section A.3.2.
V01.05
V01.06 V01.07 V01.08 V01.09 V01.10 V01.11 V01.12
01 SEP 2003 31 OCT 2003 22 JAN 2004 24 FEB 2004 17 MAR 2004 13 AUG 2004 20 JUN 2005
01 SEP 2003 31 OCT 2003 22 JAN 2004 24 FEB 2004 17 MAR 2004 13 AUG 2004 20 JUN 2005
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer. ©Motorola, Inc., 2001
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Device User Guide —9S12B128DGV1/D V01.13
Version Revision Effective Number Date Date
V01.13 05 JUL 2005 05 JUL 2005
Author
Description of Changes
Updated Figure 0-1. Updated A.3.2 NVM Reliability.
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Device User Guide — 9S12B128DGV1/D V01.13
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Device User Guide —9S12B128DGV1/D V01.13
Table of Contents
Section 1 Introduction
1.1 1.2 1.3 1.4 1.5 1.5.1 1.6 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 System Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 Detailed Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 Part ID Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
Section 2 Signal Description
2.1 System Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 2.1.1 Signal Properties Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 2.2 Detailed Signal Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 2.2.1 EXTAL, XTAL — Oscillator Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 2.2.2 RESET — External Reset Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 2.2.3 TEST — Test Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 2.2.4 VREGEN — Voltage Regulator Enable Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 2.2.5 XFC — PLL Loop Filter Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 2.2.6 BKGD / TAGHI / MODC — Background Debug, Tag High, and Mode Pin . . . . . . . .54 2.2.7 PAD[15:0] / AN[15:0] — Port AD Input Pins ATD . . . . . . . . . . . . . . . . . . . . . . . . . . .54 2.2.8 PA[7:0] / ADDR[15:8] / DATA[15:8] — Port A I/O Pins . . . . . . . . . . . . . . . . . . . . . . .55 2.2.9 PB[7:0] / ADDR[7:0] / DATA[7:0] — Port B I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . .55 2.2.10 PE7 / NOACC / XCLKS — Port E I/O Pin 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 2.2.11 PE6 / MODB / IPIPE1 — Port E I/O Pin 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 2.2.12 PE5 / MODA / IPIPE0 — Port E I/O Pin 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 2.2.13 PE4 / ECLK — Port E I/O Pin 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 2.2.14 PE3 / LSTRB / TAGLO — Port E I/O Pin 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 2.2.15 PE2 / R/W — Port E I/O Pin 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 2.2.16 PE1 / IRQ — Port E Input Pin 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 2.2.17 PE0 / XIRQ — Port E Input Pin 0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 2.2.18 PH7 / KWH7 — Port H I/O Pin 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 2.2.19 PH6 / KWH6 — Port H I/O Pin 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 2.2.20 PH5 / KWH5 — Port H I/O Pin 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
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2.2.21 PH4 / KWH4 — Port H I/O Pin 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 2.2.22 PH3 / KWH3 — Port H I/O Pin 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 2.2.23 PH2 / KWH2 — Port H I/O Pin 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 2.2.24 PH1 / KWH1 — Port H I/O Pin 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 2.2.25 PH0 / KWH0 — Port H I/O Pin 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 2.2.26 PJ7 / KWJ7 / SCL — Port J I/O Pins 7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 2.2.27 PJ6 / KWJ6 / SDA — Port J I/O Pins 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 2.2.28 PJ[1:0] / KWJ[1:0] — Port J I/O Pins [1:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 2.2.29 PK7 / ECS / ROMCTL — Port K I/O Pin 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 2.2.30 PK[5:0] / XADDR[19:14] — Port K I/O Pins [5:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 2.2.31 PM7 — Port M I/O Pin 7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 2.2.32 PM6 — Port M I/O Pin 6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 2.2.33 PM5 / SCK0 — Port M I/O Pin 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 2.2.34 PM4 / MOSI0 — Port M I/O Pin 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 2.2.35 PM3 / SS0 — Port M I/O Pin 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 2.2.36 PM2 / MISO0 — Port M I/O Pin 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 2.2.37 PM1 / TXCAN0 — Port M I/O Pin 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 2.2.38 PM0 / RXCAN0 — Port M I/O Pin 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 2.2.39 PP7 / KWP7 / PWM7 — Port P I/O Pin 7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 2.2.40 PP6 / KWP6 / PWM6 — Port P I/O Pin 6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 2.2.41 PP5 / KWP5 / PWM5 — Port P I/O Pin 5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 2.2.42 PP4 / KWP4 / PWM4 — Port P I/O Pin 4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 2.2.43 PP3 / KWP3 / PWM3 — Port P I/O Pin 3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 2.2.44 PP2 / KWP2 / PWM2 — Port P I/O Pin 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 2.2.45 PP1 / KWP1 / PWM1 — Port P I/O Pin 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 2.2.46 PP0 / KWP0 / PWM0 — Port P I/O Pin 0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 2.2.47 PS7 / SS0 — Port S I/O Pin 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 2.2.48 PS6 / SCK0 — Port S I/O Pin 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 2.2.49 PS5 / MOSI0 — Port S I/O Pin 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 2.2.50 PS4 / MISO0 — Port S I/O Pin 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 2.2.51 PS3 / TXD1 — Port S I/O Pin 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 2.2.52 PS2 / RXD1 — Port S I/O Pin 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 2.2.53 PS1 / TXD0 — Port S I/O Pin 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 2.2.54 PS0 / RXD0 — Port S I/O Pin 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 2.2.55 PT[7:0] / IOC[7:0] — Port T I/O Pins [7:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 2.3 Power Supply Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
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2.3.1 2.3.2 62 2.3.3 2.3.4 2.3.5 2.3.6 2.3.7
VDDX, VSSX — Power & Ground Pins for I/O Drivers . . . . . . . . . . . . . . . . . . . . . . .62 VDDR, VSSR — Power & Ground Pins for I/O Drivers & for Internal Voltage Regulator VDD1, VDD2, VSS1, VSS2 — Internal Logic Power Supply Pins . . . . . . . . . . . . . . .63 VDDA, VSSA — Power Supply Pins for ATD and VREG . . . . . . . . . . . . . . . . . . . . .63 VRH, VRL — ATD Reference Voltage Input Pins . . . . . . . . . . . . . . . . . . . . . . . . . . .63 VDDPLL, VSSPLL — Power Supply Pins for PLL . . . . . . . . . . . . . . . . . . . . . . . . . . .63 VREGEN — On Chip Voltage Regulator Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
Section 3 System Clock Description Section 4 Modes of Operation
4.1 4.2 4.3 4.3.1 4.3.2 4.3.3 4.4 4.4.1 4.4.2 4.4.3 4.4.4 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65 Chip Configuration Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65 Security. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66 Securing the Microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66 Operation of the Secured Microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66 Unsecuring the Microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67 Stop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67 Pseudo Stop. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67 Wait . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67 Run. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
Section 5 Resets and Interrupts
5.1 5.2 5.2.1 5.3 5.3.1 5.3.2 5.4 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69 Vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69 Vector Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70 I/O pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71 Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
Section 6 HCS12 Core Block Description
6.1 CPU12 Block Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72 6.1.1 Device-specific information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72 6.2 HCS12 Module Mapping Control (MMC) Block Description . . . . . . . . . . . . . . . . . . . . . .72
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6.2.1 6.3 6.3.1 6.4 6.5 6.5.1 6.6
Device-specific information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72 HCS12 Multiplexed External Bus Interface (MEBI) Block Description . . . . . . . . . . . . . .72 Device-specific information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72 HCS12 Interrupt (INT) Block Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72 HCS12 Background Debug (BDM) Block Description . . . . . . . . . . . . . . . . . . . . . . . . . .73 Device-specific information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73 HCS12 Breakpoint (BKP) Block Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
Section 7 Voltage Regulator (VREG3V3) Block Description Section 8 Clock and Reset Generator (CRG) Block Description
8.1 Device-specific information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
Section 9 Oscillator (OSC) Block Description
9.1 Device-specific information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
Section 10 Standard Timer (TIM) Block Description Section 11 Analog to Digital Converter (ATD) Block Description Section 12 Inter-IC Bus (IIC) Block Description Section 13 Serial Communications Interface (SCI) Block Description Section 14 Serial Peripheral Interface (SPI) Block Description Section 15 Flash EEPROM 128K1 Block Description Section 16 EEPROM 1K Block Description Section 17 RAM Block Description Section 18 MSCAN Block Description Section 19 Pulse Width Modulator (PWM) Block Description Section 20 Port Integration Module (PIM) Block Description
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Section 21 Printed Circuit Board Layout Proposals Appendix A Electrical Characteristics
A.1 General. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81 A.1.1 Parameter Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81 A.1.2 Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81 A.1.3 Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82 A.1.4 Current Injection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82 A.1.5 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83 A.1.6 ESD Protection and Latch-up Immunity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84 A.1.7 Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84 A.1.8 Power Dissipation and Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .85 A.1.9 I/O Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87 A.1.10 Supply Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89 A.2 ATD Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93 A.2.1 ATD Operating Characteristics In 5V Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93 A.2.2 ATD Operating Characteristics In 3.3V Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93 A.2.3 Factors influencing accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94 A.2.4 ATD accuracy. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96 A.3 NVM, Flash and EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99 A.3.1 NVM timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99 A.3.2 NVM Reliability. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101 A.4 VREG_3V3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105 A.4.1 Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105 A.4.2 Chip Power-up and Voltage Drops. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105 A.4.3 Output Loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106 A.5 Reset, Oscillator and PLL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109 A.5.1 Startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109 A.5.2 Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111 A.5.3 Phase Locked Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112 A.6 MSCAN. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117 A.7 SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119 A.7.1 Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119 A.7.2 Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .121 A.8 External Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .123 A.8.1 General Muxed Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .123
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Appendix B Package Information
B.1 B.2 B.3 General. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .127 112-pin LQFP package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .128 80-pin QFP package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .129
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List of Figures
Figure 0-1 Figure 1-1 Figure 1-2 Figure 1-3 Figure 2-1 Figure 2-2 Figure 2-3 Figure 2-4 Figure 2-5 Figure 2-6 Figure 3-1 Figure 21-1 Figure 21-2 Figure 21-3 Figure 21-4 Figure A-1 Figure A-2 Figure A-3 Figure A-4 Figure A-5 Figure A-6 Figure A-7 Figure A-8 Figure A-9 Figure A-10 Figure A-11 Figure B-1 Figure B-2 Order Partnumber Example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 MC9S12B128 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 MC9S12B128 Memory Map out of Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 MC9S12B64 using MC9S12B128 die Memory Map out of Reset . . . . . . . . . . . .30 Pin Assignments in 112-pin LQFP for MC9S12B128 . . . . . . . . . . . . . . . . . . . . .50 Pin Assignments in 80-pin QFP for MC9S12B128 . . . . . . . . . . . . . . . . . . . . . . .51 PLL Loop Filter Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 Colpitts Oscillator Connections (PE7=1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 Pierce Oscillator Connections (PE7=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 External Clock Connections (PE7=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 Clock Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 Recommended PCB Layout 112LQFP Colpitts Oscillator. . . . . . . . . . . . . . . . . .77 Recommended PCB Layout for 80QFP Colpitts Oscillator . . . . . . . . . . . . . . . . .78 Recommended PCB Layout for 112LQFP Pierce Oscillator . . . . . . . . . . . . . . . .79 Recommended PCB Layout for 80QFP Pierce Oscillator . . . . . . . . . . . . . . . . . .80 ATD Accuracy Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 Typical Endurance vs Temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 VREG_3V3 - Chip Power-up and Voltage Drops (not scaled). . . . . . . . . . . . . 106 Basic PLL functional diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 Jitter Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 Maximum bus clock jitter approximation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 SPI Master Timing (CPHA=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 SPI Master Timing (CPHA=1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 SPI Slave Timing (CPHA=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 SPI Slave Timing (CPHA=1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 General External Bus Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 112-pin LQFP mechanical dimensions (case no. 987) . . . . . . . . . . . . . . . . . . 128 80-pin QFP Mechanical Dimensions (case no. 841B) . . . . . . . . . . . . . . . . . . . 129
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List of Tables
Table 0-1 Derivative Differences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 Table 0-2 Defects fixed on Maskset 1L80R . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 Table 0-3 Defects fixed on Maskset 2L80R . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 Table 0-4 Defects fixed on Maskset 3L80R . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 Table 0-5 Document References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 Table 1-1 Device Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 $0000 - $000F MEBI map 1 of 3 (HCS12 Multiplexed External Bus Interface) ................31 $0010 - $0014 MMC map 1 of 4 (HCS12 Module Mapping Control) ...............................31 $0015 - $0016 INT map 1 of 2 (HCS12 Interrupt) ............................................................32 $0017 - $0017 MMC map 2 of 4 (HCS12 Module Mapping Control) ...............................32 $0018 - $0018 Reserved ..................................................................................................32 $0019 - $0019 VREG3V3 (Voltage Regulator) ................................................................32 $001A - $001B Miscellaneous Peripherals (Device User Guide, Table 1-3) ....................32 $001C - $001D MMC map 3 of 4 (HCS12 Module Mapping Control, Table 1-4) ..............32 $001E - $001E MEBI map 2 of 3 (HCS12 Multiplexed External Bus Interface) ................32 $001F - $001F INT map 2 of 2 (HCS12 Interrupt) ............................................................33 $0020 - $0027 Reserved ..................................................................................................33 $0028 - $002F BKP (HCS12 Breakpoint) .........................................................................33 $0030 - $0031 MMC map 4 of 4 (HCS12 Module Mapping Control) ...............................33 $0032 - $0033 MEBI map 3 of 3 (HCS12 Multiplexed External Bus Interface) ................33 $0034 - $003F CRG (Clock and Reset Generator) ..........................................................34 $0040 - $006F TIM (Timer 16 Bit 8 Channels) .................................................................34 $0070 - $007F Reserved .................................................................................................36 $0080 - $00AF ATD (Analog to Digital Converter 10 Bit 16 Channel) ..............................36 $00B0 - $00C7 Reserved .................................................................................................38 $00C8 - $00CF SCI0 (Asynchronous Serial Interface) ......................................................38 $00D0 - $00D7 SCI1 (Asynchronous Serial Interface) ......................................................38 $00D8 - $00DF SPI0 (Serial Peripheral Interface) ............................................................39 $00E0 - $00E7 IIC (Inter IC Bus) ......................................................................................39 $00E8 - $00FF Reserved ..................................................................................................40 $0100 - $010F Flash Control Register (fts128k1) ............................................................40 $0110 - $011B EEPROM Control Register (eets1k) ........................................................41 $011C - $013F Reserved ..................................................................................................41
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$0140 - $017F CAN0 (Motorola Scalable CAN - MSCAN) ..............................................41 Table 1-2 Detailed MSCAN Foreground Receive and Transmit Buffer Layout . . . . . . . . . . .42 $0180 - $01FF Reserved ..................................................................................................43 $0200 - $0227 PWM (Pulse Width Modulator 8 Bit 8 Channel) .......................................44 $0228 - $023F Reserved ..................................................................................................45 $0240 - $027F PIM (Port Integration Module) ..................................................................45 $0280 - $03FF Reserved ..................................................................................................47 Table 1-3 Assigned Part ID Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 Table 1-4 Memory Size Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 Table 2-1 Signal Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 Table 2-2 MC9S12B128 Power and Ground Connection Summary . . . . . . . . . . . . . . . . . . .62 Table 4-1 Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65 Table 4-2 Clock Selection Based on PE7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65 Table 4-3 Voltage Regulator VREGEN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66 Table 5-1 Interrupt Vector Locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69 Table 21-1 Suggested External Component Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76 Table A-1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83 Table A-2 ESD and Latch-up Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84 Table A-3 ESD and Latch-Up Protection Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .84 Table A-4 Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85 Table A-5 Thermal Package Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87 Table A-6 5V I/O Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88 Table A-7 3.3V I/O Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89 Table A-8 Supply Current Characteristics at 25MHz Bus Frequency. . . . . . . . . . . . . . . . . . .90 Table A-9 Supply Current Characteristics at 16MHz Bus Frequency. . . . . . . . . . . . . . . . . . .91 Table A-10 ATD Operating Characteristics In 5V Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93 Table A-11 ATD Operating Characteristics In 3.3V Range . . . . . . . . . . . . . . . . . . . . . . . . . . .94 Table A-12 ATD Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95 Table A-13 ATD Conversion Performance In 5V Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96 Table A-14 ATD Conversion Performance In 3.3V Range . . . . . . . . . . . . . . . . . . . . . . . . . . .97 Table A-15 NVM Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100 Table A-16 NVM Reliability Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102 Table A-17 VREG_3V3 - Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105 Table A-18 VREG_3V3 - Capacitive Loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107 Table A-19 Startup Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109 Table A-20 Oscillator Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111
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Table A-21 Table A-22 Table A-23 Table A-24 Table A-25 Table A-26
PLL Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115 MSCAN Wake-up Pulse Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117 Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119 SPI Master Mode Timing Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .120 SPI Slave Mode Timing Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .122 Expanded Bus Timing Characteristics In 5V Range . . . . . . . . . . . . . . . . . . . . . .125
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Derivative Differences and Document References
The Device User Guide provides information about the particular system made up of the MC9S12B128 and MC9S12B64.
Derivative Differences
Table 0-1 shows the availability of peripheral modules on the various derivatives. For details about using the HCS12 D family as a development platform for the HCS12B family refer also to engineering bulletin EB388. Table 0-1 Derivative Differences
Generic device
Packages Mask Set Temp Options Package Codes Bus Speed Options Note
MC9S12B128
112LQFP, 80QFP L80R M, V, C PV, FU 25MHz, 16MHz An errata exists contact Sales office
MC9S12B64
112LQFP, 80QFP L80R M, V, C PV, FU 25MHz, 16MHz An errata exists contact Sales office
Table 0-2 shows the defects fixed on maskset 1L80R. Table 0-2 Defects fixed on Maskset 1L80R
Errata Number MUCts01096 Module affected mscan Brief Description Data byte corrupted in receive buffer Workaround YES
Table 0-3 shows the defects fixed on maskset 2L80R. Table 0-3 Defects fixed on Maskset 2L80R
Errata Number MUCts01096 MUCts01371 Module affected mscan mscan Brief Description Data byte corrupted in receive buffer Message erroneously accepted if bus error in bit 6 of EOF Workaround YES NO
Table 0-4 shows the defects fixed on maskset 3L80R. Table 0-4 Defects fixed on Maskset 3L80R
Errata Number MUCts01096 MUCts01371 MUCts01534 Module affected mscan mscan vreg_3v3 Brief Description Data byte corrupted in receive buffer Message erroneously accepted if bus error in bit 6 of EOF Return from STOP malfunction Workaround YES NO NO
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MC9S12 B128 C FU 25
Speed Package Option Temperature Option Device Title Controller Family
Temperature Options C = -40˚C to 85˚C V = -40˚C to 105˚C M = -40˚C to 125˚C Package Options FU = 80QFP PV = 112LQFP Speed Options 25 = 25MHz bus 16 = 16MHz bus
Note: Parts with no speed option coding default to 25MHz bus Figure 0-1 Order Partnumber Example The following items should be considered when using a derivative. • PreliminaryMC9S12B64 using MC9S12B128 die The MC9S12B128 is tested only for MC9S12B64 functionality. For the preliminary MC9S12B64 the upper 2K Bytes RAM of the MC9S12B128 are reserved and should not be used. Also the pages $38-$3B of Flash are reserved and should not be used. • Pins not available in 80 pin QFP package – Port H In order to avoid floating nodes the ports should be either configured as outputs by setting the data direction register (DDRH at Base+$0262) to $FF, or enabling the pull resistors by writing a $FF to the pull enable register (PERH at Base+$0264). Port J[1:0] Port J pull-up resistors are enabled out of reset on all four pins (7:6 and 1:0). Therefore care must be taken not to disable the pull enables on PJ[1:0] by clearing the bits PERJ1 and PERJ0 at Base+$026C. Port K Port K pull-up resistors are enabled out of reset, i.e. Bit 7 = PUKE = 1 in the register PUCR at Base+$000C. Therefor care must be taken not to clear this bit. Port M[7:6] PM7:6 must be configured as outputs or their pull resistors must be enabled to avoid floating inputs. Port P6 PP6 must be configured as output or its pull resistor must be enabled to avoid a floating input.
–
–
–
–
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Device User Guide —9S12B128DGV1/D V01.13
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Port S[7:4] PS7:4 must be configured as outputs or their pull resistors must be enabled to avoid floating inputs. PAD[15:8] (ATD channels) Out of reset the ATD channels to PAD[15:8] are disabled preventing current flows in the pins. Do not modify the ATD registers for these channels!
–
Document References
The Device User Guide provides information about the MC9S12B128 device made up of standard HCS12 blocks and the HCS12 processor core. This document is part of the customer documentation. A complete set of device manuals also includes all the individual Block User Guides of the implemented modules. In a effort to reduce redundancy all module specific information is located only in the respective Block User Guide. If applicable, special implementation details of the module are given in the block description sections of this document. See Table 0-5 for names and versions of the referenced documents throughout the Device User Guide. Table 0-5 Document References
User Guide
CPU12 Reference Manual HCS12 Module Mapping Control (MMC) Block Guide HCS12 Multiplexed External Bus Interface (MEBI) Block Guide HCS12 Interrupt (INT) Block Guide HCS12 Background Debug (BDM) Block Guide HCS12 Breakpoint (BKP) Block Guide Clock and Reset Generator (CRG) Block User Guide Oscillator (OSC) Block User Guide Input Capture/Output Compare Timer (TIM_16B8C) Block User Guide Analog to Digital Converter10 Bit 16 Channel (ATD_10B16C) Block User Guide Inter IC Bus (IIC) Block User Guide Asynchronous Serial Interface (SCI) Block User Guide Serial Peripheral Interface (SPI) Block User Guide Pulse Width Modulator 8 Bit 8 Channel (PWM_8B8C) Block User Guide 128K Byte Flash (FTS128K1) Block User Guide 1K Byte EEPROM (EETS1K) Block User Guide Motorola Scalable CAN (MSCAN) Block User Guide Voltage Regulator (VREG3V3) Block User Guide Port Integration Module (PIM_9B128) Block User Guide
Versi on
V02 V04 V03 V01 V04 V01 V04 V02 V01 V03 V02 V02 V03 V01 V01 V01 V02 V02 V01
Document Order Number
S12CPU12V2/AD S12MMCV4/D S12MEBIV3/D S12INTV1/D S12BDMV4/D S12BKPV1/D S12CRGV4/D S12OSCV2/D S12TIM16B8CV1/D S12ATD10B16CV3/D S12IICV2/D S12SCIV2/D S12SPIV3/D S12PWM8B8CV1/D S12FTS128K1V1/D S12EETS1KV1/D S12MSCANV2/D S12VREG3V3V2/D S12PIM9B128V1/D
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Section 1 Introduction
1.1 Overview
The MC9S12B128 microcontroller unit (MCU) is a 16-bit device composed of standard on-chip peripherals including a 16-bit central processing unit (CPU12), 128K bytes of Flash EEPROM, 4K bytes of RAM, 1K bytes of EEPROM, two asynchronous serial communications interfaces (SCI), serial peripheral interface (SPI), an input capture/output compare timer (TIM), 16- channel, 10-bit analog-to-digital converter (ADC), an 8-channel pulse-width modulator (PWM), one CAN 2.0 A, B software compatible module (MSCAN12) and an Inter-IC Bus. The MC9S12B128 has full 16-bit data paths throughout, however, the external bus can operate in an 8-bit narrow mode so single 8-bit wide memory can be interfaced for lower cost systems. The inclusion of a PLL circuit allows power consumption and performance to be adjusted to suit operational requirements. In addition to the I/O ports available in each module, up to 22 I/O ports are available with Wake-Up capability from STOP or WAIT mode.
1.2 Features
• HCS12 Core – 16-bit HCS12 CPU i. Upward compatible with M68HC11 instruction set ii. Interrupt stacking and programmer’s model identical to M68HC11 iii. Instruction queue iv. Enhanced indexed addressing – – – – – • – – – – – – • MEBI (Multiplexed External Bus Interface) MMC (Module Mapping Control) INT (Interrupt control) BKP (Breakpoints) BDM (Background Debug Mode) Low current Colpitts or Pierce oscillator, PLL, COP watchdog, Real time interrupt, Clock monitor
CRG
8-bit and 4-bit ports with interrupt functionality
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Device User Guide — 9S12B128DGV1/D V01.13
– – • – – – • – – – • – – – – – • – – – – – – – • – – – – – – –
Digital filtering Programmable rising or falling edge trigger 128K Flash EEPROM 1K byte EEPROM 4K byte RAM 16-channels for 112 Pin Package, 8 channels for 80 Pin package options 10-bit resolution External conversion trigger capability Five receive and three transmit buffers Flexible identifier filter programmable as 2 x 32 bit, 4 x 16 bit or 8 x 8 bit Four separate interrupt channels for Rx, Tx, error and wake-up Low-pass filter wake-up function Loop-back for self test operation 16-bit Counter with 7-bit Prescaler 8 programmable input capture or output compare channels 16-bit Pulse Accumulators Simple PWM Mode Modulo Reset of Timer Counter External Event Counting Gated Time Accumulation Programmable period and duty cycle 8-bit 8-channel or 16-bit 4-channel Separate control for each pulse width and duty cycle Center-aligned or left-aligned outputs Programmable clock select logic with a wide range of frequencies Fast emergency shutdown input Usable as interrupt inputs
Memory
Analog-to-Digital Converter
1M bit per second, CAN 2.0 A, B software compatible module
Input Capture/Output Compare Timer (TIM)
8 PWM channels
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Device User Guide —9S12B128DGV1/D V01.13
•
Serial interfaces – – Two asynchronous Serial Communications Interfaces (SCI) Synchronous Serial Peripheral Interface (SPI) Compatible with I2C Bus standard Multi-master operation Software programmable for one of 256 different serial clock frequencies Supports an input voltage range from 2.97V to 5.5V Low power mode capability Includes low voltage reset (LVR) circuitry Includes low voltage interrupt (LVI) circuitry I/O lines with 5V input and drive capability 5V A/D converter inputs Operation at 32 MHz equivalent to 16 MHz Bus Speed; Option 50MHz equivalent to 25MHz Bus Speed Development support Single-wire background debug™ mode (BDM) On-chip hardware breakpoints
•
Inter-IC Bus (IIC) – – –
•
Internal 2.5V Regulator – – – –
•
112-Pin LQFP or 80 QFP package – – – – – –
1.3 Modes of Operation
User modes • Normal and Emulation Operating Modes – – – – – • – – Normal Single-Chip Mode Normal Expanded Wide Mode Normal Expanded Narrow Mode Emulation Expanded Wide Mode Emulation Expanded Narrow Mode Special Single-Chip Mode with active Background Debug Mode Special Test Mode (Motorola use only)
Special Operating Modes
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Device User Guide — 9S12B128DGV1/D V01.13
–
Special Peripheral Mode (Motorola use only)
Low power modes • • • Stop Mode Pseudo Stop Mode Wait Mode
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Device User Guide —9S12B128DGV1/D V01.13
1.4 Block Diagram
Figure 1-1 shows a block diagram of the MC9S12B128 device.
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Device User Guide — 9S12B128DGV1/D V01.13
Figure 1-1 MC9S12B128 Block Diagram
128K Byte Flash EEPROM 4K Byte RAM 1K Byte EEPROM
VDDR VSSR VREGEN VDD1,2 VSS1,2 BKGD XFC VDDPLL VSSPLL EXTAL XTAL RESET PE0 PE1 PE2 PE3 PE4 PE5 PE6 PE7 TEST AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 PAD0 PAD1 PAD2 PAD3 PAD4 PAD5 PAD6 PAD7 AN08 AN09 AN10 AN11 AN12 AN13 AN14 AN15 PIX0 PIX1 PIX2 PIX3 PIX4 PIX5 ECS IOC0 IOC1 IOC2 IOC3 IOC4 IOC5 IOC6 IOC7 KWP0 KWP1 KWP2 KWP3 KWP4 KWP5 KWP6 KWP7 RXD TXD RXD TXD MISO MOSI SCK SS RxCAN TxCAN
VRH
ATD
VRL VDDA VSSA
VRH VRL VDDA VSSA PAD08 PAD09 PAD10 PAD11 PAD12 PAD13 PAD14 PAD15 PK0 PK1 PK2 PK3 PK4 PK5 PK7 PT0 PT1 PT2 PT3 PT4 PT5 PT6 PT7 PP0 PP1 PP2 PP3 PP4 PP5 PP6 PP7 PS0 PS1 PS2 PS3 PS4 PS5 PS6 PS7 PM0 PM1 PM2 PM3 PM4 PM5 PM6 PM7 PJ0 PJ1 PJ6 PJ7 PH0 PH1 XADDR14 XADDR15 XADDR16 XADDR17 XADDR18 XADDR19
Voltage Regulator
Single-wire Background Debug Module
Clock and Reset Generation Module
CPU12
DDRK
PPAGE
AD
PLL
Periodic Interrupt COP Watchdog Clock Monitor Breakpoints
PTK
AD
ECS
XIRQ IRQ System R/W Integration LSTRB Module ECLK (SIM) MODA MODB NOACC/XCLKS
DDRE
PTE
Input Capture Output Compare Timer
DDRT DDRP DDRS DDRM DDRJ
Multiplexed Address/Data Bus PWM DDRA PTA
DATA15 ADDR15 PA7 DATA14 ADDR14 PA6 DATA13 ADDR13 PA5 DATA12 ADDR12 PA4 DATA11 ADDR11 PA3 DATA10 ADDR10 PA2 DATA9 ADDR9 PA1 DATA8 ADDR8 PA0
DDRB PTB
PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0
PWM0 PWM1 PWM2 PWM3 PWM4 PWM5 PWM6 PWM7
SCI0
ADDR7 ADDR6 ADDR5 ADDR4 ADDR3 ADDR2 ADDR1 ADDR0
SPI0
Multiplexed Wide Bus
DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0
CAN0
Multiplexed Narrow Bus
Internal Logic 2.5V
VDD1,2 VSS1,2
DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0
I/O Driver 5V
VDDX VSSX
PLL 2.5V
VDDPLL
A/D Converter 5V & Voltage Regulator Reference
VDDA VSSA
IIC
SDA SCL
KWJ6 KWJ7 KWH0 KWH1 KWH2 KWH3 KWH4 KWH5 KWH6 KWH7
DDRH
VSSPLL
PTJ PTH
KWJ0 KWJ1
PTM
PTS
SCI1
PTP
PTT
Voltage Regulator 5V & I/O
VDDR VSSR
Pin Interrupt Logic
PH2
PH3 PH4 PH5 PH6 PH7
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Device User Guide —9S12B128DGV1/D V01.13
1.5 System Memory Map
Table 1-1 and Figure 1-2 show the device memory map of the MC9S12B128 after reset. The 1K EEPROM is mapped twice in a 2K address space. Note that after reset the bottom 1k of the EEPROM ($0000 - $03FF) are hidden by the register space, and the 1K $0400 - $07FF is hidden by the RAM. Table 1-1 Device Memory Map
Address
$0000 - $000F $0010 - $0014 $0015 - $0016 $0017 $0018 $0019
Module
HCS12 Multiplexed External Bus Interface HCS12 Module Mapping Control HCS12 Interrupt HCS12 Module Mapping Control Reserved Voltage Regulator (VREG)
Size (Bytes)
16 5 2 1 1 1 2 2 1 1 8 8 2 2 12 48 16 48 24 8 8 8 8 24 16 12 36 64 128 40 24 64 384 2048 4096 16384
$001A - $001B Device ID register (PARTID) $001C - $001D HCS12 Module Mapping Control $001E $001F $0020 - $0027 $0028 - $002F $0030 - $0031 $0032 - $0033 $0034 - $003F $0040 - $006F $0070 - $007F $0080 - $00AF HCS12 Multiplexed External Bus Interface HCS12 Interrupt Reserved HCS12 Breakpoint HCS12 Module Mapping Control HCS12 Multiplexed External Bus Interface Clock and Reset Generator (PLL, RTI, COP) Standard Timer Module16-bit 8-channels (TIM) Reserved Analog to Digital Converter 10-bit 16 channels (ATD)
$00B0 - $00C7 Reserved $00C8 - $00CF Serial Communications Interface 0 (SCI0) $00D0 - $00D7 Serial Communications Interface 1 (SCI1) $00D8 - $00DF Serial Peripheral Interface (SPI0) $00E0 - $00E7 Inter IC Bus (IIC) $00E8 - $00FF Reserved $0100- $010F $0110 - $011B $0140 - $017F $0180 - $01FF $0200 - $0227 $0228 - $023F $0240 - $027F $0280 - $03FF $0000 - $07FF $0000 - $0FFF $0000 - $3FFF Flash Control Register EEPROM Control Register Motorola Scalable Can (CAN0) Reserved PWM (Pulse Width Modulator 8 Bit 8 Channel) Reserved Port Integration Module (PIM) Reserved EEPROM array 1k Array mapped twice in the address space RAM array Fixed Flash EEPROM array
$011C - $013F Reserved
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Device User Guide — 9S12B128DGV1/D V01.13
Table 1-1 Device Memory Map
Address
$4000 - $7FFF
Module
Fixed Flash EEPROM array incl. 0.5K, 1K, 2K or 4K Protected Sector at start
Size (Bytes)
16384 16384 16384
$8000 - $BFFF Flash EEPROM Page Window (eight 16k windows) Fixed Flash EEPROM array $C000 - $FFFF incl. 0.5K, 1K, 2K or 4K Protected Sector at end and 256 bytes of Vector Space at $FF80 - $FFFF
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Device User Guide —9S12B128DGV1/D V01.13
Figure 1-2 MC9S12B128 Memory Map out of Reset
$0000 $0400
$03FF $0000
REGISTERS
(Mappable to any 2K Boundary within the first 32K)
$0800
$0000
1K Bytes EEPROM
(Mappable to any 2K Boundary; 1K mapped two times in the 2K address space)
$07FF
$1000
$0000
4K Bytes RAM
(Mappable to any 4K Boundary)
EXTERN
EXTERN
$0FFF $0000 $3FFF
16K Fixed Flash Page $3D = 61
(This is dependant on the state of the ROMHM bit) $0000-$0FFF hidden
$4000
$4000
16K Fixed Flash Page $3E = 62
(This is dependant on the state of the ROMHM bit)
$7FFF
$8000
$8000
EXTERN
$BFFF
16K Page Window 8 x 16K Flash EEPROM pages
$C000
$C000
16K Fixed Flash Page $3F = 63
$FFFF $FF00
$FF00 VECTORS $FFFF EXPANDED NORMAL SINGLE CHIP SPECIAL SINGLE CHIP VECTORS VECTORS
$FFFF
BDM (if active)
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Device User Guide — 9S12B128DGV1/D V01.13
Figure 1-3 MC9S12B64 using MC9S12B128 die Memory Map out of Reset
$0000 $0400
$03FF $0000
REGISTERS
(Mappable to any 2K Boundary within the first 32K)
$0800
$0000
1K Bytes EEPROM
(Mappable to any 2K Boundary; 1K mapped two times in the 2K address space)
$07FF
$1000
$0000
4K Bytes RAM
(Mappable to any 4K Boundary) upper 2K of RAM are reserved
EXTERN
EXTERN
$0FFF $0000 $3FFF
16K Fixed Flash Page $3D = 61
(This is dependant on the state of the ROMHM bit) $0000-$0FFF hidden
$4000
$4000
16K Fixed Flash Page $3E = 62
(This is dependant on the state of the ROMHM bit)
$7FFF
$8000
$8000
EXTERN
$BFFF
16K Page Window 8 x 16K Flash EEPROM pages pages $38-$3B of Flash EEPROM are reserved
$C000
$C000
16K Fixed Flash Page $3F = 63
$FFFF $FF00
$FF00 VECTORS $FFFF EXPANDED NORMAL SINGLE CHIP SPECIAL SINGLE CHIP VECTORS VECTORS
$FFFF
BDM (if active)
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Device User Guide —9S12B128DGV1/D V01.13
1.5.1 Detailed Register Map
$0000 - $000F
Address $0000 $0001 $0002 $0003 $0004 $0005 $0006 $0007 $0008 $0009 $000A $000B $000C $000D $000E $000F Name PORTA PORTB DDRA DDRB Reserved Reserved Reserved Reserved PORTE DDRE PEAR MODE PUCR RDRIV EBICTL Reserved
MEBI map 1 of 3 (HCS12 Multiplexed External Bus Interface)
Bit 7 Read: Bit 7 Write: Read: Bit 7 Write: Read: Bit 7 Write: Read: Bit 7 Write: Read: 0 Write: Read: 0 Write: Read: 0 Write: Read: 0 Write: Read: Bit 7 Write: Read: Bit 7 Write: Read: NOACCE Write: Read: MODC Write: Read: PUPKE Write: Read: RDPK Write: Read: 0 Write: Read: 0 Write: Bit 6 6 6 6 6 0 0 0 0 6 6 0 MODB 0 0 0 0 Bit 5 5 5 5 5 0 0 0 0 5 5 PIPOE MODA 0 0 0 0 Bit 4 4 4 4 4 0 0 0 0 4 4 NECLK 0 PUPEE RDPE 0 0 Bit 3 3 3 3 3 0 0 0 0 3 3 LSTRE IVIS 0 0 0 0 Bit 2 2 2 2 2 0 0 0 0 2 Bit 2 RDWE 0 0 0 0 0 Bit 1 1 1 1 1 0 0 0 0 Bit 1 0 0 EMK PUPBE RDPB 0 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 0 0 0 0 Bit 0 0 0 EME PUPAE RDPA ESTR 0
$0010 - $0014
Address $0010 $0011 $0012 $0013 $0014 Name INITRM INITRG INITEE MISC Reserved
MMC map 1 of 4 (HCS12 Module Mapping Control)
Bit 7 Read: RAM15 Write: Read: 0 Write: Read: EE15 Write: Read: 0 Write: Read: 0 Write: Bit 6 RAM14 REG14 EE14 0 0 Bit 5 RAM13 REG13 EE13 0 0 Bit 4 RAM12 REG12 EE12 0 0 Bit 3 RAM11 REG11 EE11 Bit 2 0 0 0 Bit 1 0 0 0 Bit 0 RAMHAL 0 EEON
EXSTR1 EXSTR0 ROMHM ROMON 0 0 0 0
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Device User Guide — 9S12B128DGV1/D V01.13
$0015 - $0016
Address $0015 $0016 Name ITCR ITEST Read: Write: Read: Write:
INT map 1 of 2 (HCS12 Interrupt)
Bit 7 0 INTE Bit 6 0 INTC Bit 5 0 INTA Bit 4 WRINT INT8 Bit 3 ADR3 INT6 Bit 2 ADR2 INT4 Bit 1 ADR1 INT2 Bit 0 ADR0 INT0
$0017 - $0017
Address $0017 Name Reserved Read: Write:
MMC map 2 of 4 (HCS12 Module Mapping Control)
Bit 7 0 Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 0 Bit 1 0 Bit 0 0
$0018 - $0018
Address $0018 Name Reserved Read: Write:
Reserved
Bit 7 0 Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 0 Bit 1 0 Bit 0 0
$0019 - $0019
Address $0019 Name VREGCTRL Read: Write:
VREG3V3 (Voltage Regulator)
Bit 7 0 Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 LVDS Bit 1 LVIE Bit 0 LVIF
$001A - $001B
Address $001A $001B Name PARTIDH PARTIDL Read: Write: Read: Write:
Miscellaneous Peripherals (Device User Guide, Table 1-3)
Bit 7 ID15 ID7 Bit 6 ID14 ID6 Bit 5 ID13 ID5 Bit 4 ID12 ID4 Bit 3 ID11 ID3 Bit 2 ID10 ID2 Bit 1 ID9 ID1 Bit 0 ID8 ID0
$001C - $001D
Address $001C $001D Name MEMSIZ0 MEMSIZ1
MMC map 3 of 4 (HCS12 Module Mapping Control, Table 1-4)
Bit 7 Bit 6 Bit 5 Bit 4 Read: reg_sw0 0 eep_sw1 eep_sw0 Write: Read: rom_sw1 rom_sw0 0 0 Write: Bit 3 0 0 Bit 2 Bit 1 Bit 0 ram_sw2 ram_sw1 ram_sw0 0 pag_sw1 pag_sw0
$001E - $001E
Address $001E Name INTCR Read: Write:
MEBI map 2 of 3 (HCS12 Multiplexed External Bus Interface)
Bit 7 IRQE Bit 6 IRQEN Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 0 Bit 1 0 Bit 0 0
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Device User Guide —9S12B128DGV1/D V01.13
$001F - $001F
Address $001F Name HPRIO Read: Write:
INT map 2 of 2 (HCS12 Interrupt)
Bit 7 PSEL7 Bit 6 PSEL6 Bit 5 PSEL5 Bit 4 PSEL4 Bit 3 PSEL3 Bit 2 PSEL2 Bit 1 PSEL1 Bit 0 0
$0020 - $0027
Address $0020 $0027 Name Reserved Read: Write:
Reserved
Bit 7 0 Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 0 Bit 1 0 Bit 0 0
$0028 - $002F
Address $0028 $0029 $002A $002B $002C $002D $002E $002F Name BKPCT0 BKPCT1 BKP0X BKP0H BKP0L BKP1X BKP1H BKP1L
BKP (HCS12 Breakpoint)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Read: 0 0 0 0 BKEN BKFULL BKBDM BKTAG Write: Read: BK0MBH BK0MBL BK1MBH BK1MBL BK0RWE BK0RW BK1RWE BK1RW Write: Read: 0 0 BK0V5 BK0V4 BK0V3 BK0V2 BK0V1 BK0V0 Write: Read: Bit 15 14 13 12 11 10 9 Bit 8 Write: Read: Bit 7 6 5 4 3 2 1 Bit 0 Write: Read: 0 0 BK1V5 BK1V4 BK1V3 BK1V2 BK1V1 BK1V0 Write: Read: Bit 15 14 13 12 11 10 9 Bit 8 Write: Read: Bit 7 6 5 4 3 2 1 Bit 0 Write:
$0030 - $0031
Address $0030 $0031 Name PPAGE Reserved Read: Write: Read: Write:
MMC map 4 of 4 (HCS12 Module Mapping Control)
Bit 7 0 0 Bit 6 0 0 Bit 5 PIX5 0 Bit 4 PIX4 0 Bit 3 PIX3 0 Bit 2 PIX2 0 Bit 1 PIX1 0 Bit 0 PIX0 0
$0032 - $0033
Address $0032 $0033 Name PORTK DDRK Read: Write: Read: Write:
MEBI map 3 of 3 (HCS12 Multiplexed External Bus Interface)
Bit 7 Bit 7 Bit 7 Bit 6 6 6 Bit 5 5 5 Bit 4 4 4 Bit 3 3 3 Bit 2 2 2 Bit 1 1 1 Bit 0 Bit 0 Bit 0
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Device User Guide — 9S12B128DGV1/D V01.13
$0034 - $003F
Address $0034 $0035 $0036 $0037 $0038 $0039 $003A $003B $003C $003D $003E $003F Name SYNR REFDV CTFLG test only CRGFLG CRGINT CLKSEL PLLCTL RTICTL COPCTL FORBYP test only CTCTL test only ARMCOP
CRG (Clock and Reset Generator)
Bit 7 Read: 0 Write: Read: 0 Write: Read: 0 Write: Read: RTIF Write: Read: RTIE Write: Read: PLLSEL Write: Read: CME Write: Read: 0 Write: Read: WCOP Write: Read: 0 Write: Read: 0 Write: Read: 0 Write: Bit 7 Bit 6 0 0 0 PORF 0 PSTP PLLON RTR6 RSBCK 0 0 0 6 Bit 5 SYN5 0 0 LVRF 0 Bit 4 SYN4 0 0 LOCKIF LOCKIE Bit 3 SYN3 Bit 2 SYN2 Bit 1 SYN1 Bit 0 SYN0
REFDV3 REFDV2 REFDV1 REFDV0 0 LOCK 0 PLLWAI 0 RTR3 0 0 0 0 3 0 TRACK 0 CWAI PRE RTR2 CR2 0 0 0 2 0 SCMIF SCMIE RTIWAI PCE RTR1 CR1 0 0 0 1 0 SCM 0 COPWAI SCME RTR0 CR0 0 0 0 Bit 0
SYSWAI ROAWAI AUTO RTR5 0 0 0 0 5 ACQ RTR4 0 0 0 0 4
$0040 - $006F
Address $0040 $0041 $0042 $0043 $0044 $0045 $0046 $0047 $0048 $0049 Name TIOS CFORC OC7M OC7D TCNT (hi) TCNT (lo) TSCR1 TTOV TCTL1 TCTL2
TIM (Timer 16 Bit 8 Channels)
Bit 7 Read: IOS7 Write: 0 Read: Write: FOC7 Read: OC7M7 Write: Read: OC7D7 Write: Read: Bit 15 Write: Bit 7 Read: Write: Read: TEN Write: Read: TOV7 Write: Read: OM7 Write: Read: OM3 Write: Bit 6 IOS6
0 FOC6
Bit 5 IOS5
0 FOC5
Bit 4 IOS4
0 FOC4
Bit 3 IOS3
0 FOC3
Bit 2 IOS2
0 FOC2
Bit 1 IOS1
0 FOC1
Bit 0 IOS0
0 FOC0
OC7M6 OC7D6
14 6
OC7M5 OC7D5
13 5
OC7M4 OC7D4
12 4
OC7M3 OC7D3
11 3
OC7M2 OC7D2
10 2
OC7M1 OC7D1
9 1
OC7M0 OC7D0
Bit 8 Bit 0
TSWAI TOV6 OL7 OL3
TSFRZ TOV5 OM6 OM2
TFFCA TOV4 OL6 OL2
0 TOV3 OM5 OM1
0 TOV2 OL5 OL1
0 TOV1 OM4 OM0
0 TOV0 OL4 OL0
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Device User Guide —9S12B128DGV1/D V01.13 Address $004A $004B $004C $004D $004E $004F $0050 $0051 $0052 $0053 $0054 $0055 $0056 $0057 $0058 $0059 $005A $005B $005C $005D $005E $005F $0060 $0061 Name TCTL3 TCTL4 TIE TSCR2 TFLG1 TFLG2 TC0 (hi) TC0 (lo) TC1 (hi) TC1 (lo) TC2 (hi) TC2 (lo) TC3 (hi) TC3 (lo) TC4 (hi) TC4 (lo) TC5 (hi) TC5 (lo) TC6 (hi) TC6 (lo) TC7 (hi) TC7 (lo) PACTL PAFLG Bit 7 Read: EDG7B Write: Read: EDG3B Write: Read: C7I Write: Read: TOI Write: Read: C7F Write: Read: TOF Write: Read: Bit 15 Write: Read: Bit 7 Write: Read: Bit 15 Write: Read: Bit 7 Write: Read: Bit 15 Write: Read: Bit 7 Write: Read: Bit 15 Write: Read: Bit 7 Write: Read: Bit 15 Write: Read: Bit 7 Write: Read: Bit 15 Write: Read: Bit 7 Write: Read: Bit 15 Write: Read: Bit 7 Write: Read: Bit 15 Write: Read: Bit 7 Write: 0 Read: Write: Read: 0 Write: Bit 6 EDG7A EDG3A C6I 0 C6F 0
14 6 14 6 14 6 14 6 14 6 14 6 14 6 14 6 PAEN
Bit 5 EDG6B EDG2B C5I 0 C5F 0
13 5 13 5 13 5 13 5 13 5 13 5 13 5 13 5 PAMOD
Bit 4 EDG6A EDG2A C4I 0 C4F 0
12 4 12 4 12 4 12 4 12 4 12 4 12 4 12 4 PEDGE
Bit 3 EDG5B EDG1B C3I TCRE C3F 0
11 3 11 3 11 3 11 3 11 3 11 3 11 3 11 3 CLK1
Bit 2 EDG5A EDG1A C2I PR2 C2F 0
10 2 10 2 10 2 10 2 10 2 10 2 10 2 10 2 CLK0
Bit 1 EDG4B EDG0B C1I PR1 C1F 0
9 1 9 1 9 1 9 1 9 1 9 1 9 1 9 1 PAOVI
Bit 0 EDG4A EDG0A C0I PR0 C0F 0
Bit 8 Bit 0 Bit 8 Bit 0 Bit 8 Bit 0 Bit 8 Bit 0 Bit 8 Bit 0 Bit 8 Bit 0 Bit 8 Bit 0 Bit 8 Bit 0 PAI
0
0
0
0
0
PAOVF
PAIF
35
Device User Guide — 9S12B128DGV1/D V01.13 Address $0062 $0063 $0064$006F Name PACNT (hi) PACNT (lo) Reserved Read: Write: Read: Write: Read: Write: Bit 7
Bit 15
Bit 6
14
Bit 5
13
Bit 4
12
Bit 3
11
Bit 2
10
Bit 1
9
Bit 0
Bit 8
Bit 7 0
6 0
5 0
4 0
3 0
2 0
1 0
Bit 0 0
$0070 - $007F
$0070 - $007F Reserved Read: Write:
Reserved
0 0 0 0 0 0 0 0
$0080 - $00AF
Address $0080 $0081 $0082 $0083 $0084 $0085 $0086 $0087 $0088 $0089 $008A $008B $008C $008D $008E $008F $0090 $0091 Name ATDCTL0 ATDCTL1 ATDCTL2 ATDCTL3 ATDCTL4 ATDCTL5 ATDSTAT0 Reserved ATDTEST0 ATDTEST1 ATDSTAT2 ATDSTAT1 ATDDIEN0 ATDDIEN1 PORTAD0 PORTAD1 ATDDR0H ATDDR0L
ATD (Analog to Digital Converter 10 Bit 16 Channel)
Bit 7 Read: 0 Write: Read: ETRIGSEL Write: Read: ADPU Write: Read: 0 Write: Read: SRES8 Write: Read: DJM Write: Read: SCF Write: Read: 0 Write: Read: 0 Write: Read: 0 Write: Read: CCF15 Write: Read: CCF7 Write: Read: IEN15 Write: Read: IEN7 Write: Read: PTAD15 Write: Read: PTAD7 Write: Read: Bit15 Write: Read: Bit7 Write: Bit 6 0 0 AFFC S8C SMP1 DSGN 0 0 0 0 CCF14 CCF6 IEN14 IEN6 PTAD14 PTAD6 14 Bit6 Bit 5 0 0 AWAI S4C SMP0 SCAN ETORF 0 0 0 CCF13 CCF5 IEN13 IEN5 PTAD13 PTAD5 13 0 Bit 4 0 0 Bit 3 WRAP3 ETRIGC H3 Bit 2 WRAP2 ETRIGC H2 ETRIG FIFO PRS2 CC CC2 0 0 0 CCF10 CCF2 IEN10 IEN2 PTAD10 PTAD2 10 0 Bit 1 WRAP1 ETRIGC H1 ASCIE FRZ1 PRS1 CB CC1 0 0 0 CCF9 CCF1 IEN9 IEN1 PTAD9 PTAD1 9 0 Bit 0 WRAP0 ETRIGC H0 ASCIF FRZ0 PRS0 CA CC0 0 0 SC CCF8 CCF0 IEN8 IEN0 PTAD8 PTAD0 Bit8 0
ETRIGLE ETRIGP S2C PRS4 MULT FIFOR 0 0 0 CCF12 CCF4 IEN12 IEN4 PTAD12 PTAD4 12 0 S1C PRS3 CD CC3 0 0 0 CCF11 CCF3 IEN11 IEN3 PTAD11 PTAD3 11 0
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Device User Guide —9S12B128DGV1/D V01.13
$0080 - $00AF
Address $0092 $0093 $0094 $0095 $0096 $0097 $0098 $0099 $009A $009B $009C $009D $009E $009F $00A0 $00A1 $00A2 $00A3 $00A4 $00A5 $00A6 $00A7 $00A8 $00A9 $00AA Name ATDDR1H ATDDR1L ATDDR2H ATDDR2L ATDDR3H ATDDR3L ATDDR4H ATDDR4L ATDDR5H ATDDR5L ATDDR6H ATDDR6L ATDDR7H ATDDR7L ATDDR8H ATDDR8L ATDDR9H ATDDR9L ATDDR10H ATDDR10L ATDDR11H ATDDR11L ATDDR12H ATDDR12L ATDDR13H Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write:
ATD (Analog to Digital Converter 10 Bit 16 Channel)
Bit 7 Bit15 Bit7 Bit15 Bit7 Bit15 Bit7 Bit15 Bit7 Bit15 Bit7 Bit15 Bit7 Bit15 Bit7 Bit15 Bit7 Bit15 Bit7 Bit15 Bit7 Bit15 Bit7 Bit15 Bit7 Bit15 Bit 6 14 Bit6 14 Bit6 14 Bit6 14 Bit6 14 Bit6 14 Bit6 14 Bit6 14 Bit6 14 Bit6 14 Bit6 14 Bit6 14 Bit6 14 Bit 5 13 0 13 0 13 0 13 0 13 0 13 0 13 0 13 0 13 0 13 0 13 0 13 0 13 Bit 4 12 0 12 0 12 0 12 0 12 0 12 0 12 0 12 0 12 0 12 0 12 0 12 0 12 Bit 3 11 0 11 0 11 0 11 0 11 0 11 0 11 0 11 0 11 0 11 0 11 0 11 0 11 Bit 2 10 0 10 0 10 0 10 0 10 0 10 0 10 0 10 0 10 0 10 0 10 0 10 0 10 Bit 1 9 0 9 0 9 0 9 0 9 0 9 0 9 0 9 0 9 0 9 0 9 0 9 0 9 Bit 0 Bit8 0 Bit8 0 Bit8 0 Bit8 0 Bit8 0 Bit8 0 Bit8 0 Bit8 0 Bit8 0 Bit8 0 Bit8 0 Bit8 0 Bit8
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Device User Guide — 9S12B128DGV1/D V01.13
$0080 - $00AF
Address $00AB $00AC $00AD $00AE $00AF Name ATDDR13L ATDDR14H ATDDR14L ATDDR15H ATDDR15L Read: Write: Read: Write: Read: Write: Read: Write: Read: Write:
ATD (Analog to Digital Converter 10 Bit 16 Channel)
Bit 7 Bit7 Bit15 Bit7 Bit15 Bit7 Bit 6 Bit6 14 Bit6 14 Bit6 Bit 5 0 13 0 13 0 Bit 4 0 12 0 12 0 Bit 3 0 11 0 11 0 Bit 2 0 10 0 10 0 Bit 1 0 9 0 9 0 Bit 0 0 Bit8 0 Bit8 0
$00B0 - $00C7
$00B0 - $00C7 Reserved Read: Write:
Reserved
0 0 0 0 0 0 0 0
$00C8 - $00CF
Address $00C8 $00C9 $00CA $00CB $00CC $00CD $00CE $00CF Name SCI0BDH SCI0BDL SCI0CR1 SCI0CR2 SCI0SR1 SCI0SR2 SCI0DRH SCI0DRL
SCI0 (Asynchronous Serial Interface)
Bit 7 Bit 6 Read: 0 0 Write: Read: SBR7 SBR6 Write: Read: LOOPS SCISWAI Write: Read: TIE TCIE Write: Read: TDRE TC Write: Read: 0 0 Write: Read: R8 T8 Write: Read: R7 R6 Write: T7 T6 Bit 5 0 SBR5 RSRC RIE RDRF 0 0 R5 T5 Bit 4 SBR12 SBR4 M ILIE IDLE 0 0 R4 T4 Bit 3 SBR11 SBR3 WAKE TE OR 0 0 R3 T3 Bit 2 SBR10 SBR2 ILT RE NF BRK13 0 R2 T2 Bit 1 SBR9 SBR1 PE RWU FE TXDIR 0 R1 T1 Bit 0 SBR8 SBR0 PT SBK PF RAF 0 R0 T0
$00D0 - $00D7
Address $00D0 $00D1 $00D2 $00D3 Name SCI1BDH SCI1BDL SCI1CR1 SCI1CR2
SCI1 (Asynchronous Serial Interface)
Bit 7 Bit 6 Read: 0 0 Write: Read: SBR7 SBR6 Write: Read: LOOPS SCISWAI Write: Read: TIE TCIE Write: Bit 5 0 SBR5 RSRC RIE Bit 4 SBR12 SBR4 M ILIE Bit 3 SBR11 SBR3 WAKE TE Bit 2 SBR10 SBR2 ILT RE Bit 1 SBR9 SBR1 PE RWU Bit 0 SBR8 SBR0 PT SBK
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Device User Guide —9S12B128DGV1/D V01.13
$00D0 - $00D7
Address $00D4 $00D5 $00D6 $00D7 Name SCI1SR1 SCI1SR2 SCI1DRH SCI1DRL Read: Write: Read: Write: Read: Write: Read: Write:
SCI1 (Asynchronous Serial Interface)
Bit 7 TDRE 0 R8 R7 T7 Bit 6 TC 0 T8 R6 T6 Bit 5 RDRF 0 0 R5 T5 Bit 4 IDLE 0 0 R4 T4 Bit 3 OR 0 0 R3 T3 Bit 2 NF BRK13 0 R2 T2 Bit 1 FE TXDIR 0 R1 T1 Bit 0 PF RAF 0 R0 T0
$00D8 - $00DF
Address $00D8 $00D9 $00DA $00DB $00DC $00DD $00DE $00DF Name SPI0CR1 SPI0CR2 SPI0BR SPI0SR Reserved SPI0DR Reserved Reserved Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write:
SPI0 (Serial Peripheral Interface)
Bit 7 SPIE 0 0 SPIF 0 Bit7 0 0 Bit 6 SPE 0 SPPR2 0 0 6 0 0 Bit 5 SPTIE 0 SPPR1 SPTEF 0 5 0 0 Bit 4 MSTR Bit 3 CPOL Bit 2 CPHA 0 SPR2 0 0 2 0 0 Bit 1 SSOE SPISWAI SPR1 0 0 1 0 0 Bit 0 LSBFE SPC0 SPR0 0 0 Bit0 0 0
MODFEN BIDIROE SPPR0 MODF 0 4 0 0 0 0 0 3 0 0
$00E0 - $00E7
Address $00E0 $00E1 $00E2 $00E3 $00E4 Name IBAD IBFD IBCR IBSR IBDR Read: Write: Read: Write: Read: Write: Read: Write: Read: Write:
IIC (Inter IC Bus)
Bit 7 ADR7 IBC7 IBEN TCF D7 Bit 6 ADR6 IBC6 IBIE IAAS D6 Bit 5 ADR5 IBC5 MS/SL IBB D5 Bit 4 ADR4 IBC4 TX/RX IBAL D4 Bit 3 ADR3 IBC3 TXAK 0 D3 Bit 2 ADR2 IBC2 0 RSTA SRW D2 Bit 1 ADR1 IBC1 0 IBIF D1 Bit 0 0 IBC0 IBSWAI RXAK D0
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Device User Guide — 9S12B128DGV1/D V01.13
$00E0 - $00E7
Address $00E5 $00E6 $00E7 Name Reserved Reserved Reserved Read: Write: Read: Write: Read: Write:
IIC (Inter IC Bus)
Bit 7 0 0 0 Bit 6 0 0 0 Bit 5 0 0 0 Bit 4 0 0 0 Bit 3 0 0 0 Bit 2 0 0 0 Bit 1 0 0 0 Bit 0 0 0 0
$00E8 - $00FF
Address $00E8 $00FF Name Reserved Read: Write:
Reserved
Bit 7 0 Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 0 Bit 1 0 Bit 0 0
$0100 - $010F
Address $0100 $0101 $0102 $0103 $0104 $0105 $0106 $0107 $0108 $0109 $010A $010B $010C $010F Name FCLKDIV FSEC Reserved FCNFG FPROT FSTAT FCMD Reserved FADDRHI FADDRLO FDATAHI FDATALO Reserved
Flash Control Register (fts128k1)
Bit 7 Bit 6 Bit 5 Bit 4 Read: FDIVLD PRDIV8 FDIV5 FDIV4 Write: Read: KEYEN1 KEYEN0 NV5 NV4 Write: Read: 0 0 0 0 Write: Read: 0 CBEIE CCIE KEYACC Write: Read: FPOPEN NV6 FPHDIS FPHS1 Write: Read: CCIF CBEIF PVIOL ACCERR Write: Read: 0 0 CMDB6 CMDB5 Write: Read: 0 0 0 0 Write: Read: Bit 15 Bit 14 13 12 Write: Read: Bit 7 6 5 4 Write: Read: Bit 15 14 13 12 Write: Read: Bit 7 6 5 4 Write: Read: 0 0 0 0 Write: Bit 3 FDIV3 NV3 0 0 FPHS0 0 0 0 11 3 11 3 0 Bit 2 FDIV2 NV2 0 0 FPLDIS BLANK CMDB2 0 10 2 10 2 0 Bit 1 FDIV1 SEC1 0 0 FPLS1 0 0 0 9 1 9 1 0 Bit 0 FDIV0 SEC0 0 0 FPLS0 0 CMDB0 0 Bit 8 Bit 0 Bit 8 Bit 0 0
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Device User Guide —9S12B128DGV1/D V01.13
$0110 - $011B
Address $0110 $0111 $0112 $0113 $0114 $0115 $0116 $0117 $0118 $0119 $011A $011B Name ECLKDIV Reserved Reserved ECNFG EPROT ESTAT ECMD Reserved EADDRHI EADDRLO EDATAHI EDATALO
EEPROM Control Register (eets1k)
Bit 7 Bit 6 Read: EDIVLD PRDIV8 Write: Read: 0 0 Write: Read: 0 0 Write: Read: CBEIE CCIE Write: Read: NV6 EPOPEN Write: Read: CCIF CBEIF Write: Read: 0 CMDB6 Write: Read: 0 0 Write: Read: 0 0 Write: Read: Bit7 6 Write: Read: Bit15 14 Write: Read: Bit7 6 Write: Bit 5 EDIV5 0 0 0 NV5 Bit 4 EDIV4 0 0 0 NV4 Bit 3 EDIV3 0 0 0 EPDIS 0 0 0 0 3 11 3 Bit 2 EDIV2 0 0 0 EP2 BLANK CMDB2 0 0 2 10 2 Bit 1 EDIV1 0 0 0 EP1 0 0 0 0 1 9 1 Bit 0 EDIV0 0 0 0 EP0 0 CMDB0 0 Bit8 Bit0 Bit8 Bit0
PVIOL CMDB5 0 0 5 13 5
ACCERR 0 0 0 4 12 4
$011C - $013F
Address $011C $013F Name Reserved Read: Write:
Reserved
Bit 7 0 Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 0 Bit 1 0 Bit 0 0
$0140 - $017F
Address $0140 $0141 $0142 $0143 $0144 $0145 $0146 Name CAN0CTL0 CAN0CTL1 CAN0BTR0 CAN0BTR1 CAN0RFLG CAN0RIER CAN0TFLG
CAN0 (Motorola Scalable CAN - MSCAN)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Read: RXACT SYNCH RXFRM CSWAI TIME WUPE SLPRQ INITRQ Write: Read: 0 SLPAK INITAK CANE CLKSRC LOOPB LISTEN WUPM Write: Read: SJW1 SJW0 BRP5 BRP4 BRP3 BRP2 BRP1 BRP0 Write: Read: SAMP TSEG22 TSEG21 TSEG20 TSEG13 TSEG12 TSEG11 TSEG10 Write: Read: RSTAT1 RSTAT0 TSTAT1 TSTAT0 WUPIF CSCIF OVRIF RXF Write: Read: WUPIE CSCIE RSTATE1 RSTATE0 TSTATE1 TSTATE0 OVRIE RXFIE Write: Read: 0 0 0 0 0 TXE2 TXE1 TXE0 Write:
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Device User Guide — 9S12B128DGV1/D V01.13
$0140 - $017F
Address $0147 $0148 $0149 $014A $014B $014C $014D $014E $014F $0150 $0153 $0154 $0157 $0158 $015B $015C $015F $0160 $016F $0170 $017F Name CAN0TIER CAN0TARQ CAN0TAAK CAN0TBSEL CAN0IDAC Reserved Reserved CAN0RXERR CAN0TXERR CAN0IDAR0 CAN0IDAR3 CAN0IDMR0 CAN0IDMR3 CAN0IDAR4 CAN0IDAR7 CAN0IDMR4 CAN0IDMR7 CAN0RXFG CAN0TXFG
CAN0 (Motorola Scalable CAN - MSCAN)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Read: 0 0 0 0 0 TXEIE2 TXEIE1 Write: Read: 0 0 0 0 0 ABTRQ2 ABTRQ1 Write: Read: 0 0 0 0 0 ABTAK2 ABTAK1 Write: Read: 0 0 0 0 0 TX2 TX1 Write: Read: 0 0 0 IDHIT2 IDHIT1 IDAM1 IDAM0 Write: Read: 0 0 0 0 0 0 0 Write: Read: 0 0 0 0 0 0 0 Write: Read: RXERR7 RXERR6 RXERR5 RXERR4 RXERR3 RXERR2 RXERR1 Write: Read: TXERR7 TXERR6 TXERR5 TXERR4 TXERR3 TXERR2 TXERR1 Write: Read: AC7 AC6 AC5 AC4 AC3 AC2 AC1 Write: Read: AM7 AM6 AM5 AM4 AM3 AM2 AM1 Write: Read: AC7 AC6 AC5 AC4 AC3 AC2 AC1 Write: Read: AM7 AM6 AM5 AM4 AM3 AM2 AM1 Write: Read: FOREGROUND RECEIVE BUFFER see Table 1-2 Write: Read: FOREGROUND TRANSMIT BUFFER see Table 1-2 Write: Bit 0 TXEIE0 ABTRQ0 ABTAK0 TX0 IDHIT0 0 0 RXERR0 TXERR0 AC0 AM0 AC0 AM0
Table 1-2 Detailed MSCAN Foreground Receive and Transmit Buffer Layout
Address $0160 Name Extended ID Standard ID CAN0RIDR0 Extended ID Standard ID CAN0RIDR1 Extended ID Standard ID CAN0RIDR2 Extended ID Standard ID CAN0RIDR3 CAN0RDSR0 CAN0RDSR7 Read: Read: Write: Read: Read: Write: Read: Read: Write: Read: Read: Write: Read: Write: Bit 7 ID28 ID10 ID20 ID2 ID14 Bit 6 ID27 ID9 ID19 ID1 ID13 Bit 5 ID26 ID8 ID18 ID0 ID12 Bit 4 ID25 ID7 SRR=1 RTR ID11 Bit 3 ID24 ID6 IDE=1 IDE=0 ID10 Bit 2 ID23 ID5 ID17 Bit 1 ID22 ID4 ID16 Bit 0 ID21 ID3 ID15
$0161
ID9
ID8
ID7
$0162
ID6
ID5
ID4
ID3
ID2
ID1
ID0
RTR
$0163 $0164$016B
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
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Device User Guide —9S12B128DGV1/D V01.13
Table 1-2 Detailed MSCAN Foreground Receive and Transmit Buffer Layout
Address $016C $016D $016E $016F Name CAN0RDLR Reserved CAN0RTSRH CAN0RTSRL Extended ID CAN0TIDR0 Standard ID Extended ID CAN0TIDR1 Standard ID Extended ID CAN0TIDR2 Standard ID Extended ID CAN0TIDR3 Standard ID CAN0TDSR0 CAN0TDSR7 CAN0TDLR CAN0TTBPR CAN0TTSRH CAN0TTSRL Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 DLC3 Bit 2 DLC2 Bit 1 DLC1 Bit 0 DLC0
TSR15 TSR7 ID28 ID10 ID20 ID2 ID14
TSR14 TSR6 ID27 ID9 ID19 ID1 ID13
TSR13 TSR5 ID26 ID8 ID18 ID0 ID12
TSR12 TSR4 ID25 ID7 SRR=1 RTR ID11
TSR11 TSR3 ID24 ID6 IDE=1 IDE=0 ID10
TSR10 TSR2 ID23 ID5 ID17
TSR9 TSR1 ID22 ID4 ID16
TSR8 TSR0 ID21 ID3 ID15
$0170
$0171
ID9
ID8
ID7
$0172
ID6
ID5
ID4
ID3
ID2
ID1
ID0
RTR
$0173 $0174$017B $017C $017D $017E $017F
DB7
DB6
DB5
DB4
DB3 DLC3
DB2 DLC2 PRIO2 TSR10 TSR2
DB1 DLC1 PRIO1 TSR9 TSR1
DB0 DLC0 PRIO0 TSR8 TSR0
PRIO7 TSR15 TSR7
PRIO6 TSR14 TSR6
PRIO5 TSR13 TSR5
PRIO4 TSR12 TSR4
PRIO3 TSR11 TSR3
$0180 - $01FF
Address $0180 $01FF Name Reserved Read: Write:
Reserved
Bit 7 0 Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 0 Bit 1 0 Bit 0 0
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Device User Guide — 9S12B128DGV1/D V01.13
$0200 - $0227
Address $0200 $0201 $0202 $0203 $0204 $0205 $0206 $0207 $0208 $0209 $020A $020B $020C $020D $020E $020F $0210 $0211 $0212 $0213 $0214 $0215 $0216 $0217 $0218 Name
PWM (Pulse Width Modulator 8 Bit 8 Channel)
Bit 6 PWME6 PPOL6 PCLK6 PCKB2 CAE6 CON45 0 0 6 6 0 0 6 0 6 0 6 0 6 0 6 0 6 0 6 0 6 0 6 6 6 6 6 Bit 5 PWME5 PPOL5 PCLK5 PCKB1 CAE5 CON23 0 0 5 5 0 0 5 0 5 0 5 0 5 0 5 0 5 0 5 0 5 0 5 5 5 5 5 Bit 4 PWME4 PPOL4 PCLK4 PCKB0 CAE4 CON01 0 0 4 4 0 0 4 0 4 0 4 0 4 0 4 0 4 0 4 0 4 0 4 4 4 4 4 Bit 3 PWME3 PPOL3 PCLK3 0 CAE3 PSWAI 0 0 3 3 0 0 3 0 3 0 3 0 3 0 3 0 3 0 3 0 3 0 3 3 3 3 3 Bit 2 PWME2 PPOL2 PCLK2 PCKA2 CAE2 PFRZ 0 0 2 2 0 0 2 0 2 0 2 0 2 0 2 0 2 0 2 0 2 0 2 2 2 2 2 Bit 1 PWME1 PPOL1 PCLK1 PCKA1 CAE1 0 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 1 1 1 Bit 0 PWME0 PPOL0 PCLK0 PCKA0 CAE0 0 0 0 Bit 0 Bit 0 0 0 Bit 0 0 Bit 0 0 Bit 0 0 Bit 0 0 Bit 0 0 Bit 0 0 Bit 0 0 Bit 0 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0
Bit 7 Read: PWME PWME7 Write: Read: PWMPOL PPOL7 Write: Read: PWMCLK PCLK7 Write: Read: 0 PWMPRCLK Write: Read: PWMCAE CAE7 Write: Read: PWMCTL CON67 Write: Read: 0 PWMTST Test Only Write: 0 PWMPRSC Read: Test Only Write: Read: PWMSCLA Bit 7 Write: Read: PWMSCLB Bit 7 Write: 0 PWMSCNTA Read: Test Only Write: 0 PWMSCNTB Read: Test Only Write: Read: Bit 7 PWMCNT0 Write: 0 Read: Bit 7 PWMCNT1 Write: 0 Read: Bit 7 PWMCNT2 Write: 0 Read: Bit 7 PWMCNT3 Write: 0 Read: Bit 7 PWMCNT4 Write: 0 Read: Bit 7 PWMCNT5 Write: 0 Read: Bit 7 PWMCNT6 Write: 0 Read: Bit 7 PWMCNT7 Write: 0 Read: PWMPER0 Bit 7 Write: Read: PWMPER1 Bit 7 Write: Read: PWMPER2 Bit 7 Write: Read: PWMPER3 Bit 7 Write: Read: PWMPER4 Bit 7 Write:
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Device User Guide —9S12B128DGV1/D V01.13
$0200 - $0227
Address $0219 $021A $021B $021C $021D $021E $021F $0220 $0221 $0222 $0223 $0224 $0225$0227 Name PWMPER5 PWMPER6 PWMPER7 PWMDTY0 PWMDTY1 PWMDTY2 PWMDTY3 PWMDTY4 PWMDTY5 PWMDTY6 PWMDTY7 PWMSDN Reserved
PWM (Pulse Width Modulator 8 Bit 8 Channel)
Bit 7 Read: Bit 7 Write: Read: Bit 7 Write: Read: Bit 7 Write: Read: Bit 7 Write: Read: Bit 7 Write: Read: Bit 7 Write: Read: Bit 7 Write: Read: Bit 7 Write: Read: Bit 7 Write: Read: Bit 7 Write: Read: Bit 7 Write: Read: PWMIF Write: Read: 0 Write: Bit 6 6 6 6 6 6 6 6 6 6 6 6 PWMIE 0 Bit 5 5 5 5 5 5 5 5 5 5 5 5
0
PWMRSTRT
Bit 4 4 4 4 4 4 4 4 4 4 4 4 PWMLVL 0
Bit 3 3 3 3 3 3 3 3 3 3 3 3 0 0
Bit 2 2 2 2 2 2 2 2 2 2 2 2 PWM7IN 0
Bit 1 1 1 1 1 1 1 1 1 1 1 1
Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0
PWM7INL PWM7ENA 0 0
0
$0228 - $023F
Address $0228 $023F Name Reserved Read: Write:
Reserved
Bit 7 0 Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 0 Bit 1 0 Bit 0 0
$0240 - $027F
Address $0240 $0241 $0242 $0243 $0244 $0245 Name PTT PTIT DDRT RDRT PERT PPST
PIM (Port Integration Module)
Bit 7 Read: PTT7 Write: Read: PTIT7 Write: Read: DDRT7 Write: Read: RDRT7 Write: Read: PERT7 Write: Read: PPST7 Write: Bit 6 PTT6 PTIT6 DDRT7 RDRT6 PERT6 PPST6 Bit 5 PTT5 PTIT5 DDRT5 RDRT5 PERT5 PPST5 Bit 4 PTT4 PTIT4 DDRT4 RDRT4 PERT4 PPST4 Bit 3 PTT3 PTIT3 DDRT3 RDRT3 PERT3 PPST3 Bit 2 PTT2 PTIT2 DDRT2 RDRT2 PERT2 PPST2 Bit 1 PTT1 PTIT1 DDRT1 RDRT1 PERT1 PPST1 Bit 0 PTT0 PTIT0 DDRT0 RDRT0 PERT0 PPST0
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Device User Guide — 9S12B128DGV1/D V01.13
$0240 - $027F
Address $0246 $0247 $0248 $0249 $024A $024B $024C $024D $024E $024F $0250 $0251 $0252 $0253 $0254 $0255 $0256 $0257 $0258 $0259 $025A $025B $025C $025D $025E Name Reserved Reserved PTS PTIS DDRS RDRS PERS PPSS WOMS Reserved PTM PTIM DDRM RDRM PERM PPSM WOMM MODRR PTP PTIP DDRP RDRP PERP PPSP PIEP Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write:
PIM (Port Integration Module)
Bit 7 0 0 PTS7 PTIS7 DDRS7 RDRS7 PERS7 PPSS7 WOMS7 0 PTM7 PTIM7 DDRM7 RDRM7 PERM7 PPSM7 Bit 6 0 0 PTS6 PTIS6 DDRS7 RDRS6 PERS6 PPSS6 WOMS6 0 PTM6 PTIM6 DDRM7 RDRM6 PERM6 PPSM6 Bit 5 0 0 PTS5 PTIS5 DDRS5 RDRS5 PERS5 PPSS5 WOMS5 0 PTM5 PTIM5 DDRM5 RDRM5 PERM5 PPSM5 Bit 4 0 0 PTS4 PTIS4 DDRS4 RDRS4 PERS4 PPSS4 WOMS4 0 PTM4 PTIM4 DDRM4 RDRM4 PERM4 PPSM4 Bit 3 0 0 PTS3 PTIS3 DDRS3 RDRS3 PERS3 PPSS3 WOMS3 0 PTM3 PTIM3 DDRM3 RDRM3 PERM3 PPSM3 Bit 2 0 0 PTS2 PTIS2 DDRS2 RDRS2 PERS2 PPSS2 WOMS2 0 PTM2 PTIM2 DDRM2 RDRM2 PERM2 PPSM2 Bit 1 0 0 PTS1 PTIS1 DDRS1 RDRS1 PERS1 PPSS1 WOMS1 0 PTM1 PTIM1 DDRM1 RDRM1 PERM1 PPSM1 Bit 0 0 0 PTS0 PTIS0 DDRS0 RDRS0 PERS0 PPSS0 WOMS0 0 PTM0 PTIM0 DDRM0 RDRM0 PERM0 PPSM0
WOMM7 WOMM6 WOMM5 WOMM4 WOMM3 WOMM2 WOMM1 WOMM0 0 PTP7 PTIP7 DDRP7 RDRP7 PERP7 PPSP7 PIEP7 0 PTP6 PTIP6 DDRP7 RDRP6 PERP6 PPSP6 PIEP6 0 PTP5 PTIP5 DDRP5 RDRP5 PERP5 PPSP5 PIEP5 MODRR4 PTP4 PTIP4 DDRP4 RDRP4 PERP4 PPSP4 PIEP4 0 PTP3 PTIP3 DDRP3 RDRP3 PERP3 PPSP3 PIEP3 0 PTP2 PTIP2 DDRP2 RDRP2 PERP2 PPSP2 PIEP2 0 PTP1 PTIP1 DDRP1 RDRP1 PERP1 PPSP1 PIEP1 0 PTP0 PTIP0 DDRP0 RDRP0 PERP0 PPSS0 PIEP0
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Device User Guide —9S12B128DGV1/D V01.13
$0240 - $027F
Address $025F $0260 $0261 $0262 $0263 $0264 $0265 $0266 $0267 $0268 $0269 $026A $026B $026C $026D $026E $026F $0270 $027F Name PIFP PTH PTIH DDRH RDRH PERH PPSH PIEH PIFH PTJ PTIJ DDRJ RDRJ PERJ PPSJ PIEJ PIFJ Reserved Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write:
PIM (Port Integration Module)
Bit 7 PIFP7 PTH7 PTIH7 DDRH7 RDRH7 PERH7 PPSH7 PIEH7 PIFH7 PTJ7 PTIJ7 DDRJ7 RDRJ7 PERJ7 PPSJ7 PIEJ7 PIFJ7 0 Bit 6 PIFP6 PTH6 PTIH6 DDRH7 RDRH6 PERH6 PPSH6 PIEH6 PIFH6 PTJ6 PTIJ6 DDRJ7 RDRJ6 PERJ6 PPSJ6 PIEJ6 PIFJ6 0 Bit 5 PIFP5 PTH5 PTIH5 DDRH5 RDRH5 PERH5 PPSH5 PIEH5 PIFH5 0 0 0 0 0 0 0 0 0 Bit 4 PIFP4 PTH4 PTIH4 DDRH4 RDRH4 PERH4 PPSH4 PIEH4 PIFH4 0 0 0 0 0 0 0 0 0 Bit 3 PIFP3 PTH3 PTIH3 DDRH3 RDRH3 PERH3 PPSH3 PIEH3 PIFH3 0 0 0 0 0 0 0 0 0 Bit 2 PIFP2 PTH2 PTIH2 DDRH2 RDRH2 PERH2 PPSH2 PIEH2 PIFH2 0 0 0 0 0 0 0 0 0 Bit 1 PIFP1 PTH1 PTIH1 DDRH1 RDRH1 PERH1 PPSH1 PIEH1 PIFH1 PTJ1 PTIJ1 DDRJ1 RDRJ1 PERJ1 PPSJ1 PIEJ1 PIFJ1 0 Bit 0 PIFP0 PTH0 PTIH0 DDRH0 RDRH0 PERH0 PPSH0 PIEH0 PIFH0 PTJ0 PTIJ0 DDRJ0 RDRJ0 PERJ0 PPSJ0 PIEJ0 PIFJ0 0
$0280 - $03FF
Address $0280 $03FF Name Reserved Read: Write:
Reserved
Bit 7 0 Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 0 Bit 1 0 Bit 0 0
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Device User Guide — 9S12B128DGV1/D V01.13
1.6 Part ID Assignments
The part ID is located in two 8-bit registers PARTIDH and PARTIDL (addresses $001A and $001B after reset). The read-only value is a unique part ID for each revision of the chip. Table 1-3 shows the assigned part ID number. Table 1-3 Assigned Part ID Numbers
Device MC9S12B128 MC9S12B128 MC9S12B128 MC9S12B128 Mask Set Number 0L80R 1L80R 2L80R 3L80R Part ID1 $2100 $2101 $2102 $2103
NOTES: 1. The coding is as follows: Bit 15-12: Major family identifier Bit 11-8: Minor family identifier Bit 7-4: Major mask set revision number including FAB transfers Bit 3-0: Minor - non full - mask set revision
The device memory sizes are located in two 8-bit registers MEMSIZ0 and MEMSIZ1 (addresses $001C and $001D after reset). Table 1-4 shows the read-only values of these registers. Refer to HCS12 Module Mapping Control (MMC) Block Guide for further details.
Table 1-4 Memory Size Registers
Register name MEMSIZ0 MEMSIZ1 Value $11 $C0
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Device User Guide —9S12B128DGV1/D V01.13
Section 2 Signal Description
This section describes signals that connect off-chip. It includes a pinout diagram, a table of signal properties and detailed discussion of signals. It is built from the signal description sections of the Block User Guides of the individual IP blocks on the device.
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Device User Guide — 9S12B128DGV1/D V01.13
2.1 System Pinout
The MC9S12B128 is available in a 112-pin low profile quad flat pack (LQFP) and in a 80-pin quad flat pack (QFP). Most pins perform two or more functions, as described in the Signal Descriptions. Figure 2-1 and Figure 2-2 show the pin assignments. Figure 2-1 Pin Assignments in 112-pin LQFP for MC9S12B128
50
ADDR5/DATA5/PB5 ADDR6/DATA6/PB6 ADDR7/DATA7/PB7 KWH7/PH7 KWH6/PH6 KWH5/PH5 KWH4/PH4 XCLKS/NOACC/PE7 MODB/IPIPE1/PE6 MODA/IPIPE0/PE5 ECLK/PE4 VSSR VDDR RESET VDDPLL XFC VSSPLL EXTAL XTAL TEST KWH3/PH3 KWH2/PH2 KWH1/PH1 KWH0/PH0 LSTRB/TAGLO/PE3 R/W/PE2 IRQ/PE1 XIRQ/PE0
29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56
PWM3/KWP3/PP3 PWM2/KWP2/PP2 PWM1/KWP1/PP1 PWM0/KWP0/PP0 XADDR17/PK3 XADDR16/PK2 XADDR15/PK1 XADDR14/PK0 IOC0/PT0 IOC1/PT1 IOC2/PT2 IOC3/PT3 VDD1 VSS1 IOC4/PT4 IOC5/PT5 IOC6/PT6 IOC7/PT7 XADDR19/PK5 XADDR18/PK4 KWJ1/PJ1 KWJ0/PJ0 MODC/TAGHI/BKGD ADDR0/DATA0/PB0 ADDR1/DATA1/PB1 ADDR2/DATA2/PB2 ADDR3/DATA3/PB3 ADDR4/DATA4/PB4
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85
PP4/KWP4/PWM4 PP5/KWP5/PWM5 PP6/KWP6/PWM6 PP7/KWP7/PWM7 PK7/ECS VDDX VSSX PM0/RXCAN0 PM1/TXCAN0 PM2/MISO PM3/SS PM4/MOSI PM5/SCK PJ6/KWJ6/SDA PJ7/KWJ7/SCL VREGEN PS7/SS0 PS6/SCK0 PS5/MOSI0 PS4/MISO0 PS3/TxD1 PS2/RxD1 PS1/TxD0 PS0/RxD0 PM6 PM7 VSSA VRL 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57
MC9S12B128
112LQFP
VRH VDDA PAD15/AN15 PAD07/AN07 PAD14/AN14 PAD06/AN06 PAD13/AN13 PAD05/AN05 PAD12/AN12 PAD04/AN04 PAD11/AN11 PAD03/AN03 PAD10/AN10 PAD02/AN02 PAD09/AN09 PAD01/AN01 PAD08/AN08 PAD00/AN00 VSS2 VDD2 PA7/ADDR15/DATA15 PA6/ADDR14/DATA14 PA5/ADDR13/DATA13 PA4/ADDR12/DATA12 PA3/ADDR11/DATA11 PA2/ADDR10/DATA10 PA1/ADDR9/DATA9 PA0/ADDR8/DATA8
Signals shown in Bold are not available on the 80 Pin Package
Device User Guide —9S12B128DGV1/D V01.13
Figure 2-2 Pin Assignments in 80-pin QFP for MC9S12B128
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
PP4/KWP4/PWM4 PP5/KWP5/PWM5 PP7/KWP7/PWM7 VDDX VSSX PM0/RxCAN0 PM1/TxCAN0 PM2/MISO PM3/SS PM4/MOSI PM5/SCK PJ6/KWJ6/SDA PJ7/KWJ7/SCL VREGEN PS3/TxD1 PS2/RxD1 PS1/TxD0 PS0/RxD0 VSSA VRL PWM3/KWP3/PP3 PWM2/KWP2/PP2 PWM1/KWP1/PP1 PWM0/KWP0/PP0 IOC0/PT0 IOC1/PT1 IOC2/PT2 IOC3/PT3 VDD1 VSS1 IOC4/PT4 IOC5/PT5 IOC6/PT6 IOC7/PT7 MODC/TAGHI/BKGD ADDR0/DATA0/PB0 ADDR1/DATA1/PB1 ADDR2/DATA2/PB2 ADDR3/DATA3/PB3 ADDR4/DATA4/PB4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
MC9S12B128
80 QFP
VRH VDDA PAD07/AN07 PAD06/AN06 PAD05/AN05 PAD04/AN04 PAD03/AN03 PAD02/AN02 PAD01/AN01 PAD00/AN00 VSS2 VDD2 PA7/ADDR15/DATA15 PA6/ADDR14/DATA14 PA5/ADDR13/DATA13 PA4/ADDR12/DATA12 PA3/ADDR11/DATA11 PA2/ADDR10/DATA10 PA1/ADDR9/DATA9 PA0/ADDR8/DATA8
ADDR5/DATA5/PB5 ADDR6/DATA6/PB6 ADDR7/DATA7/PB7 XCLKS/NOACC/PE7 MODB/IPIPE1/PE6 MODA/IPIPE0/PE5 ECLK/PE4 VSSR VDDR RESET VDDPLL XFC VSSPLL EXTAL XTAL TEST LSTRB/TAGLO/PE3 R/W/PE2 IRQ/PE1 XIRQ/PE0
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
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2.1.1 Signal Properties Summary
Table 2-1 summarizes the pin functionality. Signals shown in bold are not available in the 80 pin package. Table 2-1 Signal Properties
Pin Name Function1 EXTAL XTAL RESET TEST VREGEN XFC BKGD PAD[15:8] PAD[07:00] PA[7:0] PB[7:0] PE7 PE6 PE5 PE4 PE3 PE2 PE1 PE0 PH7 PH6 PH5 PH4 PH3 PH2 PH1 PH0 PJ7 PJ6 PJ[1:0] Pin Name Function2 — — — — — — TAGHI AN[15:8] AN[07:00] ADDR[15:8]/ DATA[15:8] ADDR[7:0]/ DATA[7:0] NOACC IPIPE1 IPIPE0 ECLK LSTRB R/W IRQ XIRQ KWH7 KWH6 KWH5 KWH4 KWH3 KWH2 KWH1 KWH0 KWJ7 KWJ6 KWJ[1:0] Pin Name Pin Name Powered Function Function by 3 4 — — — — — — MODC — — — — XCLKS MODB MODA — TAGLO — — — — — — — — — — — SCL SDA — — — — — — — — — VDDA — — — — — — — — — — — — — — — — — — — — — — VDDX PERJ/ PPSJ Up PERH/ PPSH Disabled VDDR PUCR/ PUPEE PUCR/ PUPAE PUCR/ PUPBE PUCR/ PUPEE None None VDDPLL VDDR N.A. VDDX VDDPLL VDDR Always Up Up None None Internal Pull Resistor CTRL Reset State
Description
Oscillator Pins External Reset Test Input Voltage Regulator Enable Input PLL Loop Filter Background Debug, Tag High, Mode Input Port AD Inputs, Analog Inputs AN[15:8] of ATD Port AD Inputs, Analog Inputs AN[7:0] of ATD Port A I/O, Multiplexed Address/Data Disabled Port B I/O, Multiplexed Address/Data Up Port E I/O, Access, Clock Select Port E I/O, Pipe Status, Mode Input Port E I/O, Pipe Status, Mode Input
While RESET pin is low: Down
Mode Port E I/O, Bus Clock Output depende Port E I/O, Byte Strobe, Tag Low nt1 Port E I/O, R/W in expanded modes Up Port E Input, Maskable Interrupt Port E Input, Non Maskable Interrupt Port H I/O, Interrupt Port H I/O, Interrupt Port H I/O, Interrupt Port H I/O, Interrupt Port H I/O, Interrupt Port H I/O, Interrupt Port H I/O, Interrupt Port H I/O, Interrupt Port J I/O, Interrupt, SCL of IIC, Port J I/O, Interrupt, SDA of IIC, Port J I/O, Interrupts
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Device User Guide —9S12B128DGV1/D V01.13
Internal Pull Resistor CTRL PUCR/ PUPKE Reset State Up
Pin Name Function1
Pin Name Function2
Pin Name Pin Name Powered Function Function by 3 4 ROMCTL — — — SCK MOSI SS0 MISO0 — — PWM7 PWM6 PWM5 PWM4 PWM3 PWM2 PWM1 PWM0 — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — VDDX
Description Port K I/O, Emulation Chip Select, ROM On Enable Port K I/O, Extended Addresses Port M I/O Port M I/O Port M I/O, SCK of SPI0
PK7 PK[5:0] PM7 PM6 PM5 PM4 PM3 PM2 PM1 PM0 PP7 PP6 PP5 PP4 PP3 PP2 PP1 PP0 PS7 PS6 PS5 PS4 PS3 PS2 PS1 PS0 PT[7:0]
ECS XADDR[19:14] — — — — — — TXCAN0 RXCAN0 KWP7 KWP6 KWP5 KWP4 KWP3 KWP2 KWP1 KWP0 SS0 SCK0 MOSI0 MISO0 TXD1 RXD1 TXD0 RXD0 IOC[7:0]
PERM/ PPSM
Port M I/O, MOSI of SPI0 Port M I/O, SS of SPI0 Port M I/O, MISO of SPI0 Port M I/O, TX of CAN0 Port M I/O, RX of CAN0 Disabled Port P I/O, Interrupt, Channel 7 of PWM Port P I/O, Interrupt, PWM Channel 6
PERP/ PPSP
Port P I/O, Interrupt, PWM Channel 5 Port P I/O, Interrupt, PWM Channel 4 Port P I/O, Interrupt, PWM Channel 3 Port P I/O, Interrupt, PWM Channel 2 Port P I/O, Interrupt, PWM Channel 1 Port P I/O, Interrupt, PWM Channel 0 Port S I/O, SS of SPI0 Port S I/O, SCK of SPI0 Port S I/O, MOSI of SPI0
PERS/ PPSS
Up
Port S I/O, MISO of SPI0 Port S I/O, TXD of SCI1 Port S I/O, RXD of SCI1 Port S I/O, TXD of SCI0 Port S I/O, RXD of SCI0
PERT/ PPST
Disabled Port T I/O, Timer channels
NOTES: 1. Refer to PEAR register description in HCS12 Multiplexed External Bus Interface (MEBI) Block Guide.
2.2 Detailed Signal Descriptions
2.2.1 EXTAL, XTAL — Oscillator Pins
EXTAL and XTAL are the crystal driver and external clock pins. On reset all the device clocks are derived from the EXTAL input frequency. XTAL is the crystal output.
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2.2.2 RESET — External Reset Pin
An active low bidirectional control signal, it acts as an input to initialize the MCU to a known start-up state, and an output when an internal MCU function causes a reset.
2.2.3 TEST — Test Pin
This input only pin is reserved for test.
NOTE:
The TEST pin must be tied to VSS in all applications.
2.2.4 VREGEN — Voltage Regulator Enable Pin
This input only pin enables or disables the on-chip voltage regulator.
2.2.5 XFC — PLL Loop Filter Pin
PLL loop filter. Please ask your Motorola representative for the interactive application note to compute PLL loop filter elements. Any current leakage on this pin must be avoided.
XFC R0 MCU CS VDDPLL VDDPLL
CP
Figure 2-3 PLL Loop Filter Connections
2.2.6 BKGD / TAGHI / MODC — Background Debug, Tag High, and Mode Pin
The BKGD/TAGHI/MODC pin is used as a pseudo-open-drain pin for the background debug communication. In MCU expanded modes of operation when instruction tagging is on, an input low on this pin during the falling edge of E-clock tags the high half of the instruction word being read into the instruction queue. It is used as a MCU operating mode select pin during reset. The state of this pin is latched to the MODC bit at the rising edge of RESET. This pin has a permanently enabled pull-up device.
2.2.7 PAD[15:0] / AN[15:0] — Port AD Input Pins ATD
PAD15 - PAD0 are general purpose input pins and analog inputs AN[15:0] of the analog to digital converter ATD.
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2.2.8 PA[7:0] / ADDR[15:8] / DATA[15:8] — Port A I/O Pins
PA7-PA0 are general purpose input or output pins. In MCU expanded modes of operation, these pins are used for the multiplexed external address and data bus.
2.2.9 PB[7:0] / ADDR[7:0] / DATA[7:0] — Port B I/O Pins
PB7-PB0 are general purpose input or output pins. In MCU expanded modes of operation, these pins are used for the multiplexed external address and data bus.
2.2.10 PE7 / NOACC / XCLKS — Port E I/O Pin 7
PE7 is a general purpose input or output pin. During MCU expanded modes of operation, the NOACC signal, when enabled, is used to indicate that the current bus cycle is an unused or “free” cycle. This signal will assert when the CPU is not using the bus. The XCLKS is an input signal which controls whether a crystal in combination with the internal Colpitts (low power) oscillator is used or whether Pierce oscillator/external clock circuitry is used. The state of this pin is latched at the rising edge of RESET. If the input is a logic low the EXTAL pin is configured for an external clock drive or a Pierce Oscillator. If input is a logic high a Colpitts oscillator circuit is configured on EXTAL and XTAL. Since this pin is an input with a pull-up device during reset, if the pin is left floating, the default configuration is a Colpitts oscillator circuit on EXTAL and XTAL.
EXTAL CDC * MCU XTAL C2 VSSPLL * Due to the nature of a translated ground Colpitts oscillator a DC voltage bias is applied to the crystal Please contact the crystal manufacturer for crystal DC bias conditions and recommended capacitor value CDC. C1 Crystal or ceramic resonator
Figure 2-4 Colpitts Oscillator Connections (PE7=1)
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EXTAL
C3
MCU RS* RB
Crystal or ceramic resonator C4
XTAL
VSSPLL
* Rs can be zero (shorted) when used with higher frequency crystals. Refer to manufacturer’s data.
Figure 2-5 Pierce Oscillator Connections (PE7=0)
EXTAL
MCU
CMOS-COMPATIBLE EXTERNAL OSCILLATOR (VDDPLL-Level)
XTAL
not connected
Figure 2-6 External Clock Connections (PE7=0)
2.2.11 PE6 / MODB / IPIPE1 — Port E I/O Pin 6
PE6 is a general purpose input or output pin. It is used as a MCU operating mode select pin during reset. The state of this pin is latched to the MODB bit at the rising edge of RESET. This pin is shared with the instruction queue tracking signal IPIPE1. This pin is an input with a pull-down device which is only active when RESET is low.
2.2.12 PE5 / MODA / IPIPE0 — Port E I/O Pin 5
PE5 is a general purpose input or output pin. It is used as a MCU operating mode select pin during reset. The state of this pin is latched to the MODA bit at the rising edge of RESET. This pin is shared with the instruction queue tracking signal IPIPE0. This pin is an input with a pull-down device which is only active when RESET is low.
2.2.13 PE4 / ECLK — Port E I/O Pin 4
PE4 is a general purpose input or output pin. It can be configured to drive the internal bus clock ECLK. ECLK can be used as a timing reference.
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2.2.14 PE3 / LSTRB / TAGLO — Port E I/O Pin 3
PE3 is a general purpose input or output pin. In MCU expanded modes of operation, LSTRB can be used for the low-byte strobe function to indicate the type of bus access and when instruction tagging is on, TAGLO is used to tag the low half of the instruction word being read into the instruction queue.
2.2.15 PE2 / R/W — Port E I/O Pin 2
PE2 is a general purpose input or output pin. In MCU expanded modes of operations, this pin drives the read/write output signal for the external bus. It indicates the direction of data on the external bus.
2.2.16 PE1 / IRQ — Port E Input Pin 1
PE1 is a general purpose input pin and the maskable interrupt request input that provides a means of applying asynchronous interrupt requests. This will wake up the MCU from STOP or WAIT mode.
2.2.17 PE0 / XIRQ — Port E Input Pin 0
PE0 is a general purpose input pin and the non-maskable interrupt request input that provides a means of applying asynchronous interrupt requests. This will wake up the MCU from STOP or WAIT mode.
2.2.18 PH7 / KWH7 — Port H I/O Pin 7
PH7 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode.
2.2.19 PH6 / KWH6 — Port H I/O Pin 6
PH6 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode.
2.2.20 PH5 / KWH5 — Port H I/O Pin 5
PH5 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode.
2.2.21 PH4 / KWH4 — Port H I/O Pin 2
PH4 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode.
2.2.22 PH3 / KWH3 — Port H I/O Pin 3
PH3 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode.
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2.2.23 PH2 / KWH2 — Port H I/O Pin 2
PH2 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode.
2.2.24 PH1 / KWH1 — Port H I/O Pin 1
PH1 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode.
2.2.25 PH0 / KWH0 — Port H I/O Pin 0
PH0 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode.
2.2.26 PJ7 / KWJ7 / SCL — Port J I/O Pins 7
PJ7 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode. It can be configured as the serial clock pin SCL of the IIC module.
2.2.27 PJ6 / KWJ6 / SDA — Port J I/O Pins 6
PJ6 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode. It can be configured as the serial data pin SDA of the IIC module.
2.2.28 PJ[1:0] / KWJ[1:0] — Port J I/O Pins [1:0]
PJ1 and PJ0 are general purpose input or output pins. They can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode.
2.2.29 PK7 / ECS / ROMCTL — Port K I/O Pin 7
PK7 is a general purpose input or output pin. During MCU expanded modes of operation, this pin is used as the emulation chip select output (ECS). While configurating MCU expanded modes this pin is used to enable the Flash EEPROM memory in the memory map (ROMCTL). At the rising edge of RESET, the state of this pin is latched to the ROMON bit. For a complete list of modes refer to 4.2 Chip Configuration Summary.
2.2.30 PK[5:0] / XADDR[19:14] — Port K I/O Pins [5:0]
PK5-PK0 are general purpose input or output pins. In MCU expanded modes of operation, these pins provide the expanded address XADDR[19:14] for the external bus.
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2.2.31 PM7 — Port M I/O Pin 7
PM7 is a general purpose input or output pin.
2.2.32 PM6 — Port M I/O Pin 6
PM6 is a general purpose input or output pin.
2.2.33 PM5 / SCK0 — Port M I/O Pin 5
PM5 is a general purpose input or output pin. It can be configured as the serial clock pin SCK of the Serial Peripheral Interface 0 (SPI0).
2.2.34 PM4 / MOSI0 — Port M I/O Pin 4
PM4 is a general purpose input or output pin. It can be configured as the master output (during master mode) or slave input pin (during slave mode) MOSI for the Serial Peripheral Interface 0 (SPI0).
2.2.35 PM3 / SS0 — Port M I/O Pin 3
PM3 is a general purpose input or output pin. It can be configured as the slave select pin SS of the Serial Peripheral Interface 0 (SPI0).
2.2.36 PM2 / MISO0 — Port M I/O Pin 2
PM2 is a general purpose input or output pin. It can be configured as the master input (during master mode) or slave output pin (during slave mode) MISO for the Serial Peripheral Interface 0 (SPI0).
2.2.37 PM1 / TXCAN0 — Port M I/O Pin 1
PM1 is a general purpose input or output pin. It can be configured as the transmit pin TXCAN of the Motorola Scalable Controller Area Network controller 0 (CAN0).
2.2.38 PM0 / RXCAN0 — Port M I/O Pin 0
PM0 is a general purpose input or output pin. It can be configured as the receive pin RXCAN of the Motorola Scalable Controller Area Network controller 0 (CAN0).
2.2.39 PP7 / KWP7 / PWM7 — Port P I/O Pin 7
PP7 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode. It can be configured as Pulse Width Modulator (PWM) channel 7 output.
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2.2.40 PP6 / KWP6 / PWM6 — Port P I/O Pin 6
PP6 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode. It can be configured as Pulse Width Modulator (PWM) channel 6 output.
2.2.41 PP5 / KWP5 / PWM5 — Port P I/O Pin 5
PP5 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode. It can be configured as Pulse Width Modulator (PWM) channel 5 output.
2.2.42 PP4 / KWP4 / PWM4 — Port P I/O Pin 4
PP4 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode. It can be configured as Pulse Width Modulator (PWM) channel 4 output.
2.2.43 PP3 / KWP3 / PWM3 — Port P I/O Pin 3
PP3 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode. It can be configured as Pulse Width Modulator (PWM) channel 3 output.
2.2.44 PP2 / KWP2 / PWM2 — Port P I/O Pin 2
PP2 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode. It can be configured as Pulse Width Modulator (PWM) channel 2 output.
2.2.45 PP1 / KWP1 / PWM1 — Port P I/O Pin 1
PP1 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode. It can be configured as Pulse Width Modulator (PWM) channel 1 output.
2.2.46 PP0 / KWP0 / PWM0 — Port P I/O Pin 0
PP0 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode. It can be configured as Pulse Width Modulator (PWM) channel 0 output.
2.2.47 PS7 / SS0 — Port S I/O Pin 7
PS6 is a general purpose input or output pin. It can be configured as the slave select pin SS of the Serial Peripheral Interface 0 (SPI0).
2.2.48 PS6 / SCK0 — Port S I/O Pin 6
PS6 is a general purpose input or output pin. It can be configured as the serial clock pin SCK of the Serial Peripheral Interface 0 (SPI0).
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2.2.49 PS5 / MOSI0 — Port S I/O Pin 5
PS5 is a general purpose input or output pin. It can be configured as master output (during master mode) or slave input pin (during slave mode) MOSI of the Serial Peripheral Interface 0 (SPI0).
2.2.50 PS4 / MISO0 — Port S I/O Pin 4
PS4 is a general purpose input or output pin. It can be configured as master input (during master mode) or slave output pin (during slave mode) MOSI of the Serial Peripheral Interface 0 (SPI0).
2.2.51 PS3 / TXD1 — Port S I/O Pin 3
PS3 is a general purpose input or output pin. It can be configured as the transmit pin TXD of Serial Communication Interface 1 (SCI1).
2.2.52 PS2 / RXD1 — Port S I/O Pin 2
PS2 is a general purpose input or output pin. It can be configured as the receive pin RXD of Serial Communication Interface 1 (SCI1).
2.2.53 PS1 / TXD0 — Port S I/O Pin 1
PS1 is a general purpose input or output pin. It can be configured as the transmit pin TXD of Serial Communication Interface 0 (SCI0).
2.2.54 PS0 / RXD0 — Port S I/O Pin 0
PS0 is a general purpose input or output pin. It can be configured as the receive pin RXD of Serial Communication Interface 0 (SCI0).
2.2.55 PT[7:0] / IOC[7:0] — Port T I/O Pins [7:0]
PT7-PT0 are general purpose input or output pins. They can be configured as input capture or output compare pins IOC7-IOC0 of the Timer (TIM).
2.3 Power Supply Pins
MC9S12B128 power and ground pins are described below.
NOTE:
All VSS pins must be connected together in the application.
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Table 2-2 MC9S12B128 Power and Ground Connection Summary
Mnemonic VDD1, 2 VSS1, 2 VDDR VSSR VDDX VSSX VDDA VSSA VRL VRH VDDPLL VSSPLL VREGEN Pin Number 112-pin QFP 13, 65 14, 66 41 40 107 106 83 86 85 84 43 45 97 Nominal Voltage 2.5V 0V 5.0V 0V 5.0V 0V 5.0V 0V 0V 5.0V 2.5V 0V 5.0V Description Internal power and ground generated by internal regulator External power and ground, supply to pin drivers and internal voltage regulator. External power and ground, supply to pin drivers. Operating voltage and ground for the analog-to-digital converters and the reference for the internal voltage regulator, allows the supply voltage to the A/D to be bypassed independently. Reference voltages for the analog-to-digital converter. Provides operating voltage and ground for the Phased-Locked Loop. This allows the supply voltage to the PLL to be bypassed independently. Internal power and ground generated by internal regulator. Internal Voltage Regulator enable/disable
2.3.1 VDDX, VSSX — Power & Ground Pins for I/O Drivers
External power and ground for I/O drivers. Because fast signal transitions place high, short-duration current demands on the power supply, use bypass capacitors with high-frequency characteristics and place them as close to the MCU as possible. Bypass requirements depend on how heavily the MCU pins are loaded. VDDX and VSSX are the supplies for Ports J, K, M, P, T and S.
2.3.2 VDDR, VSSR — Power & Ground Pins for I/O Drivers & for Internal Voltage Regulator
External power and ground for I/O drivers and input to the internal voltage regulator. Because fast signal transitions place high, short-duration current demands on the power supply, use bypass capacitors with high-frequency characteristics and place them as close to the MCU as possible. Bypass requirements depend on how heavily the MCU pins are loaded. VDDR and VSSR are the supplies for Ports A, B, E and H.
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2.3.3 VDD1, VDD2, VSS1, VSS2 — Internal Logic Power Supply Pins
Power is supplied to the MCU through VDD and VSS. Because fast signal transitions place high, short-duration current demands on the power supply, use bypass capacitors with high-frequency characteristics and place them as close to the MCU as possible. This 2.5V supply is derived from the internal voltage regulator. There is no static load on those pins allowed. The internal voltage regulator is turned off, if VREGEN is tied to ground.
NOTE:
No load allowed except for bypass capacitors.
2.3.4 VDDA, VSSA — Power Supply Pins for ATD and VREG
VDDA, VSSA are the power supply and ground input pins for the voltage regulator and the two analog to digital converters. It also provides the reference for the internal voltage regulator. This allows the supply voltage to ATD0/ATD1 and the reference voltage to be bypassed independently.
2.3.5 VRH, VRL — ATD Reference Voltage Input Pins
VRH and VRL are the reference voltage input pins for the analog to digital converter.
2.3.6 VDDPLL, VSSPLL — Power Supply Pins for PLL
Provides operating voltage and ground for the Oscillator and the Phased-Locked Loop. This allows the supply voltage to the Oscillator and PLL to be bypassed independently.This 2.5V voltage is generated by the internal voltage regulator.
NOTE:
No load allowed except for bypass capacitors.
2.3.7 VREGEN — On Chip Voltage Regulator Enable
Enables the internal 5V to 2.5V voltage regulator. If this pin is tied low, VDD1,2 and VDDPLL must be supplied externally.
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Section 3 System Clock Description
The Clock and Reset Generator provides the internal clock signals for the core and all peripheral modules. Figure 3-1 shows the clock connections from the CRG to all modules. Consult the CRG Block User Guide for details on clock generation.
HCS12_CORE
BDM CPU MEBI BKP
Core Clock
MMC INT
Flash RAM EEPROM EXTAL TIM ATD OSC XTAL CRG Bus Clock Oscillator Clock PWM SCI0, SCI1 SPI0 CAN0 PIM IIC
Figure 3-1 Clock Connections
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Section 4 Modes of Operation
4.1 Overview
Eight possible modes determine the operating configuration of the MC9S12B128. Each mode has an associated default memory map and external bus configuration. Three low power modes exist for the device.
4.2 Chip Configuration Summary
The operating mode out of reset is determined by the states of the MODC, MODB, and MODA pins during reset (Table 4-1). The MODC, MODB, and MODA bits in the MODE register show the current operating mode and provide limited mode switching during operation. The states of the MODC, MODB, and MODA pins are latched into these bits on the rising edge of the reset signal. The ROMCTL signal allows the setting of the ROMON bit in the MISC register thus controlling whether the internal Flash is visible in the memory map. ROMON = 1 mean the Flash is visible in the memory map. The state of the ROMCTL pin is latched into the ROMON bit in the MISC register on the rising edge of the reset signal. Table 4-1 Mode Selection
BKGD = MODC
0
PE6 = MODB
0
PE5 = MODA
0
PK7 = ROMCTL
X 0 1 X 0 1 X 0 1 X 0 1
ROMON Bit
1 1 0 0 1 0 1 0 1 1 0 1
Mode Description
Special Single Chip, BDM allowed and ACTIVE. BDM is allowed in all other modes but a serial command is required to make BDM active. Emulation Expanded Narrow, BDM allowed Special Test (Expanded Wide), BDM allowed Emulation Expanded Wide, BDM allowed Normal Single Chip, BDM allowed Normal Expanded Narrow, BDM allowed Peripheral; BDM allowed but bus operations would cause bus conflicts (must not be used) Normal Expanded Wide, BDM allowed
0 0 0 1 1 1 1
0 1 1 0 0 1 1
1 0 1 0 1 0 1
For further explanation on the modes refer to the HCS12 Multiplexed External Bus Interface Block Guide.
Table 4-2 Clock Selection Based on PE7
PE7 = XCLKS
1
Description
Colpitts Oscillator selected
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Table 4-2 Clock Selection Based on PE7
PE7 = XCLKS
0
Description
Pierce Oscillator/external clock selected
Table 4-3 Voltage Regulator VREGEN
VREGEN
1 0
Description
Internal Voltage Regulator enabled Internal Voltage Regulator disabled, VDD1,2 and VDDPLL must be supplied externally with 2.5V
4.3 Security
The device will make available a security feature preventing the unauthorized read and write of the memory contents. This feature allows: • • • • Protection of the contents of FLASH, Protection of the contents of EEPROM, Operation in single-chip mode, Operation from external memory with internal FLASH and EEPROM disabled.
The user must be reminded that part of the security must lie with the user’s code. An extreme example would be user’s code that dumps the contents of the internal program. This code would defeat the purpose of security. At the same time the user may also wish to put a back door in the user’s program. An example of this is the user downloads a key through the SCI which allows access to a programming routine that updates parameters stored in EEPROM.
4.3.1 Securing the Microcontroller
Once the user has programmed the FLASH and EEPROM (if desired), the part can be secured by programming the security bits located in the FLASH module. These non-volatile bits will keep the part secured through resetting the part and through powering down the part. The security byte resides in a portion of the Flash array. Check the Flash Block User Guide for more details on the security configuration.
4.3.2 Operation of the Secured Microcontroller
4.3.2.1 Normal Single Chip Mode This will be the most common usage of the secured part. Everything will appear the same as if the part was not secured with the exception of BDM operation. The BDM operation will be blocked.
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4.3.2.2 Executing from External Memory The user may wish to execute from external space with a secured microcontroller. This is accomplished by resetting directly into expanded mode. The internal FLASH and EEPROM will be disabled. BDM operations will be blocked.
4.3.3 Unsecuring the Microcontroller
In order to unsecure the microcontroller, the internal FLASH and EEPROM must be erased. This can be done through an external program in expanded mode or via a sequence of BDM commands. Unsecuring is also possible via the Backdoor Key Access. Refer to Flash Block Guide for details. Once the user has erased the FLASH and EEPROM, the part can be reset into special single chip mode. This invokes a program that verifies the erasure of the internal FLASH and EEPROM. Once this program completes, the user can erase and program the FLASH security bits to the unsecured state. This is generally done through the BDM, but the user could also change to expanded mode (by writing the mode bits through the BDM) and jumping to an external program (again through BDM commands). Note that if the part goes through a reset before the security bits are reprogrammed to the unsecure state, the part will be secured again.
4.4 Low Power Modes
The microcontroller features three main low power modes. Consult the respective Block User Guide for information on the module behavior in Stop, Pseudo Stop, and Wait Mode. An important source of information about the clock system is the Clock and Reset Generator User Guide (CRG).
4.4.1 Stop
Executing the CPU STOP instruction stops all clocks and the oscillator thus putting the chip in fully static mode. Wake up from this mode can be done via reset or external interrupts.
4.4.2 Pseudo Stop
This mode is entered by executing the CPU STOP instruction. In this mode the oscillator is still running and the Real Time Interrupt (RTI) or Watchdog (COP) sub module can stay active. Other peripherals are turned off. This mode consumes more current than the full STOP mode, but the wake up time from this mode is significantly shorter.
4.4.3 Wait
This mode is entered by executing the CPU WAI instruction. In this mode the CPU will not execute instructions. The internal CPU signals (address and databus) will be fully static. All peripherals stay active. For further power consumption the peripherals can individually turn off their local clocks.
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4.4.4 Run
Although this is not a low power mode, unused peripheral modules should not be enabled in order to save power.
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Section 5 Resets and Interrupts
5.1 Overview
Consult the Exception Processing section of the CPU12 Reference Manual for information on resets and interrupts.
5.2 Vectors
5.2.1 Vector Table
Table 5-1 lists interrupt sources and vectors in default order of priority. Table 5-1 Interrupt Vector Locations
Vector Address
$FFFE, $FFFF $FFFC, $FFFD $FFFA, $FFFB $FFF8, $FFF9 $FFF6, $FFF7 $FFF4, $FFF5 $FFF2, $FFF3 $FFF0, $FFF1 $FFEE, $FFEF $FFEC, $FFED $FFEA, $FFEB $FFE8, $FFE9 $FFE6, $FFE7 $FFE4, $FFE5 $FFE2, $FFE3 $FFE0, $FFE1 $FFDE, $FFDF $FFDC, $FFDD $FFDA, $FFDB $FFD8, $FFD9 $FFD6, $FFD7 $FFD4, $FFD5 $FFD2, $FFD3 $FFD0, $FFD1 $FFCE, $FFCF
Interrupt Source
External Reset, Power On Reset or Low Voltage Reset (see CRG Flags Register to determine reset source) Clock Monitor fail reset COP failure reset Unimplemented instruction trap SWI XIRQ IRQ Real Time Interrupt Standard Timer channel 0 Standard Timer channel 1 Standard Timer channel 2 Standard Timer channel 3 Standard Timer channel 4 Standard Timer channel 5 Standard Timer channel 6 Standard Timer channel 7 Standard Timer overflow Pulse accumulator A overflow Pulse accumulator input edge SPI0 SCI0 SCI1 ATD Reserved Port J
CCR Mask
None None None None None X-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit
Local Enable
None PLLCTL (CME, SCME) COP rate select None None None IRQCR (IRQEN) CRGINT (RTIE) TIE (C0I) TIE (C1I) TIE (C2I) TIE (C3I) TIE (C4I) TIE (C5I) TIE (C6I) TIE (C7I) TMSK2 (TOI) PACTL (PAOVI) PACTL (PAI) SPICR1 (SPIE, SPTIE) SCICR2 (TIE, TCIE, RIE, ILIE) SCICR2 (TIE, TCIE, RIE, ILIE) ATDCTL2 (ASCIE) Reserved PIEJ (PIEJ7, PIEJ6, PIEJ1, PIEJ0)
HPRIO Value to Elevate
– – – – – – $F2 $F0 $EE $EC $EA $E8 $E6 $E4 $E2 $E0 $DE $DC $DA $D8 $D6 $D4 $D2 $D0 $CE
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$FFCC, $FFCD $FFCA, $FFCB $FFC8, $FFC9 $FFC6, $FFC7 $FFC4, $FFC5 $FFC2, $FFC3 $FFC0, $FFC1 $FFBE, $FFBF $FFBC, $FFBD $FFBA, $FFBB $FFB8, $FFB9 $FFB6, $FFB7 $FFB4, $FFB5 $FFB2, $FFB3 $FFB0, $FFB1 $FFAE, $FFAF $FFAC, $FFAD $FFAA, $FFAB $FFA8, $FFA9 $FFA6, $FFA7 $FFA4, $FFA5 $FFA2, $FFA3 $FFA0, $FFA1 $FF9E, $FF9F $FF9C, $FF9D $FF9A, $FF9B $FF98, $FF99 $FF96, $FF97 $FF94, $FF95 $FF92, $FF93 $FF90, $FF91 $FF8E, $FF8F $FF8C, $FF8D $FF8A, $FF8B $FF80 to $FF89 Port P PWM Emergency Shutdown VREG LVI Reserved Port H Reserved CRG PLL lock CRG Self Clock Mode Reserved IIC Bus Reserved EEPROM FLASH CAN0 wake-up CAN0 errors CAN0 receive CAN0 transmit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit Reserved PIEP (PIEP7-0) PWMSDN (PWMIE) CTRL0 (LVIE) Reserved PIEH (PIEH7-0) Reserved CRGINT (LOCKIE) CRGINT (SCMIE) Reserved IBCR (IBIE) Reserved ECNFG (CCIE, CBEIE) FCNFG (CCIE, CBEIE) CANRIER (WUPIE) CANRIER (CSCIE, OVRIE) CANRIER (RXFIE) CANTIER (TXEIE2-TXEIE0) $CC $CA $C8 $C6 $C4 $C2 $C0 $BE $BC $BA $B8 $B6 $B4 $B2 $B0 $AE $AC $AA $A8 $A6 $A4 $A2 $A0 $9E $9C $9A $98 $96 $94 $92 $90 $8E $8C $8A
5.3 Resets
When a reset occurs, MCU registers and control bits are changed to known start-up states. Refer to the respective module Block User Guides for register reset states. For details on the different kind of resets refer to the HCS12 Interrupt, CRG and VREG_3V3 Block User Guides.
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5.3.1 I/O pins
Refer to the HCS12 Multiplexed External Bus Interface (MEBI) Block Guide for mode dependent pin configuration of port A, B, E and K out of reset. Refer to the PIM Block User Guide for reset configurations of all peripheral module ports.
NOTE:
For devices assembled in 80-pin QFP packages all non-bonded out pins should be configured as outputs after reset in order to avoid current drawn from floating inputs. Refer to Table 2-1 for affected pins.
5.3.2 Memory
Refer to Table 1-1 for locations of the memories depending on the operating mode after reset. The RAM array is not automatically initialized out of reset.
5.4 Interrupts
For details on the different kind of interrupts refer to the HCS12 Interrupt Block User Guide and according module Block User Guides.
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Section 6 HCS12 Core Block Description
6.1 CPU12 Block Description
Consult the CPU12 Reference Manual for information on the CPU.
6.1.1 Device-specific information
When the CPU12 Reference Manual refers to cycles this is equivalent to Bus Clock periods. So 1 cycle is equivalent to 1 Bus Clock period.
6.2 HCS12 Module Mapping Control (MMC) Block Description
Consult the MMC Block Guide for information on the HCS12 Module Mapping Control module.
6.2.1 Device-specific information
• INITEE – – • Reset state: $01 Bits EE11-EE15 are "Write once in Normal and Emulation modes and write anytime in Special modes". Reset state: $00 Register is "Write anytime in all modes"
PPAGE – –
•
For Memory Size Registers see Table 1-4.
6.3 HCS12 Multiplexed External Bus Interface (MEBI) Block Description
Consult the MEBI Block Guide for information on HCS12 Multiplexed External Bus Interface module.
6.3.1 Device-specific information
• PUCR – Reset state: $90
6.4 HCS12 Interrupt (INT) Block Description
Consult the INT Block Guide for information on the HCS12 Interrupt module.
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6.5 HCS12 Background Debug (BDM) Block Description
Consult the BDM Block Guide for information on the HCS12 Background Debug module.
6.5.1 Device-specific information
When the BDM Block Guide refers to alternate clock this is equivalent to Oscillator Clock.
6.6 HCS12 Breakpoint (BKP) Block Description
Consult the BKP Block Guide for information on the HCS12 Breakpoint module.
Section 7 Voltage Regulator (VREG3V3) Block Description
Consult the VREG3V3 Block User Guide for information about the dual output linear voltage regulator. VREGEN is accessible externally.
Section 8 Clock and Reset Generator (CRG) Block Description
Consult the CRG Block User Guide for information about the Clock and Reset Generator module.
8.1 Device-specific information
The Low Voltage Reset feature of the CRG is available on this device.
NOTE:
If the voltage regulator is shut downed by connecting VREGEN to the corresponding ground pin then the LVRF flag in the CRG Flags Register (CRGFLG) is undefined.
Section 9 Oscillator (OSC) Block Description
Consult the OSC Block User Guide for information about the Oscillator module.
9.1 Device-specific information
The XCLKS input signal is active low (see 2.2.10 PE7 / NOACC / XCLKS — Port E I/O Pin 7).
Section 10 Standard Timer (TIM) Block Description
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Consult the TIM_16B8C Block User Guide for information about the Standard Timer module. When the TIM_16B8C Block User Guide refers to freeze mode this is equivalent to active BDM mode.
Section 11 Analog to Digital Converter (ATD) Block Description
Consult the ATD_10B16C Block User Guide for information about the Analog to Digital Converter module. When the ATD_10B16C Block User Guide refers to freeze mode this is equivalent to active BDM mode. The ETRIG pin option is not available, but the external trigger feature is available on ATD channels.
NOTE:
In QFP80 package ATDIEN0 should be set always to $00.
Section 12 Inter-IC Bus (IIC) Block Description
Consult the IIC Block User Guide for information about the Inter-IC Bus module.
Section 13 Serial Communications Interface (SCI) Block Description
There are two Serial Communications Interfaces (SCI1 and SCI0) implemented on the MC9S12B128 device. Consult the SCI Block User Guide for information about each Serial Communications Interface module.
Section 14 Serial Peripheral Interface (SPI) Block Description
Consult the SPI Block User Guide for information about the Serial Peripheral Interface module.
Section 15 Flash EEPROM 128K1 Block Description
Consult the FTS128K1 Block User Guide for information about the flash module. The "S12 LRAE" is a generic Load RAM and Execute (LRAE) program which will be programmed into the flash memory of this device during manufacture. This LRAE program will provide greater programming flexibility to the end users by allowing the device to be programmed directly using CAN or SCI after it is assembled on the PCB. Use of the LRAE program is at the discretion of the end user and, if not required, it must simply be erased prior to flash programming. For more details of the S12 LRAE and its implementation, please see the S12 LREA Application Note (AN2546/D).
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Section 16 EEPROM 1K Block Description
Consult the EETS1K Block User Guide for information about the EEPROM module.
Section 17 RAM Block Description
This module supports single-cycle misaligned word accesses.
Section 18 MSCAN Block Description
Consult the MSCAN Block User Guide for information about the Motorola Scalable CAN Module.
Section 19 Pulse Width Modulator (PWM) Block Description
Consult the PWM_8B8C Block User Guide for information about the Pulse Width Modulator module. When the PWM_8B8C Block User Guide refers to freeze mode this is equivalent to active BDM mode.
Section 20 Port Integration Module (PIM) Block Description
Consult the PIM_9B128 Block User Guide for information about the Port Integration Module.
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Section 21 Printed Circuit Board Layout Proposals
Table 21-1 Suggested External Component Values
Component
C1 C2 C3 C4 C5 C6 C7 C8 C9 / CS C10 / CP C11 / CDC R1 R2 / RB R3 / RS Q1
Purpose
VDD1 filter cap VDD2 filter cap VDDA filter cap VDDR filter cap VDDPLL filter cap VDDX filter cap OSC load cap
Type
ceramic X7R ceramic X7R ceramic X7R X7R/tantalum ceramic X7R X7R/tantalum
Value
100 .. 220nF 100 .. 220nF 100nF >=100nF 100nF >=100nF
See PLL specification chapter OSC load cap PLL loop filter cap See PLL specification chapter PLL loop filter cap DC cutoff cap PLL loop filter res OSC res Pierce mode only OSC res Quartz Colpitts mode only, if recommended by quartz manufacturer See PLL specification chapter
The PCB must be carefully laid out to ensure proper operation of the voltage regulator as well as of the MCU itself. The following rules must be observed: • • • • • • • Every supply pair must be decoupled by a ceramic capacitor connected as near as possible to the corresponding pins(C1 - C6). Central point of the ground star should be the VSSR pin. Use low ohmic low inductance connections between VSS1, VSS2 and VSSR. VSSPLL must be directly connected to VSSR. Keep traces of VSSPLL, EXTAL and XTAL as short as possible and occupied board area for C7, C8, C11 and Q1 as small as possible. Do not place other signals or supplies underneath area occupied by C7, C8, C10 and Q1 and the connection area to the MCU. Central power input should be fed in at the VDDA/VSSA pins.
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Figure 21-1 Recommended PCB Layout 112LQFP Colpitts Oscillator
VDDX
VREGEN
C6 VSSX
VSSA
C3
VDDA
VDD1 C1 VSS1 VSS2 C2 VDD2
VSSR C4 VDDR C5 C9 R1 C10 C8 Q1 VSSPLL VDDPLL C7 C11
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Figure 21-2 Recommended PCB Layout for 80QFP Colpitts Oscillator
VDDX
C6
VREGEN
VSSX
VSSA
C3
VDDA
VDD1 VSS2
C1 C2
VSS1 VDD2
VSSR C4 C5 VDDR C11
C8
C7 Q1
C10
R1
C9
VSSPLL VDDPLL
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Figure 21-3 Recommended PCB Layout for 112LQFP Pierce Oscillator
VREGEN VDDX C6 VSSX
VSSA
C3
VDDA
VDD1 C1 VSS1 VSS2 C2 VDD2
VSSR R3 C5 R2 Q1 C9 C10 C8 C7 VSSPLL C4 VDDR VDDPLL R1
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Figure 21-4 Recommended PCB Layout for 80QFP Pierce Oscillator
VDDX
C6
VREGEN
VSSX
VSSA
C3
VDDA
VDD1 VSS2
C1 C2
VSS1 VDD2
VSSPLL
VSSR C4 C5 VDDR
R2 Q1 C8 C7 R3
C10
R1
C9
VSSPLL VDDPLL
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Appendix A Electrical Characteristics
A.1 General
NOTE:
The part is specified and tested over the 5V and 3.3V ranges. For the intermediate range, generally the electrical specifications for the 3.3V range apply, but the part is not tested in production test in the intermediate range.
This introduction is intended to give an overview on several common topics like power supply, current injection etc.
A.1.1 Parameter Classification
The electrical parameters shown in this supplement are guaranteed by various methods. To give the customer a better understanding the following classification is used and the parameters are tagged accordingly in the tables where appropriate.
NOTE:
P:
This classification is shown in the column labeled “C” in the parameter tables where appropriate.
Those parameters are guaranteed during production testing on each individual device. C: Those parameters are achieved by the design characterization by measuring a statistically relevant sample size across process variations. T: Those parameters are achieved by design characterization on a small sample size from typical devices under typical conditions unless otherwise noted. All values shown in the typical column are within this category. D: Those parameters are derived mainly from simulations.
A.1.2 Power Supply
The MC9S12B128 utilizes several pins to supply power to the I/O ports, A/D converter, oscillator, PLL and internal logic. The VDDA, VSSA pair supplies the A/D converter and the internal voltage regulator. The VDDX, VSSX, VDDR and VSSR pairs supply the I/O pins, VDDR supplies also the internal voltage regulator.
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VDD1, VSS1, VDD2 and VSS2 are the supply pins for the internal logic, VDDPLL, VSSPLL supply the oscillator and the PLL. VSS1 and VSS2 are internally connected by metal. VDDA, VDDX, VDDR as well as VSSA, VSSX, VSSR are connected by anti-parallel diodes for ESD protection.
NOTE:
In the following context VDD5 is used for either VDDA, VDDR and VDDX; VSS5 is used for either VSSA, VSSR and VSSX unless otherwise noted. IDD5 denotes the sum of the currents flowing into the VDDA, VDDX and VDDR pins. VDD is used for VDD1, VDD2 and VDDPLL, VSS is used for VSS1, VSS2 and VSSPLL. IDD is used for the sum of the currents flowing into VDD1 and VDD2.
A.1.3 Pins
There are four groups of functional pins. A.1.3.1 5V I/O pins Those I/O pins have a nominal level of 5V. This class of pins is comprised of all port I/O pins, the analog inputs, BKGD and the RESET pins.The internal structure of all those pins is identical, however some of the functionality may be disabled. E.g. for the analog inputs the output drivers, pull-up and pull-down resistors are disabled permanently. A.1.3.2 Analog Reference This group is made up by the VRH and VRL pins. A.1.3.3 Oscillator The pins XFC, EXTAL, XTAL dedicated to the oscillator have a nominal 2.5V level. They are supplied by VDDPLL. A.1.3.4 TEST This pin is used for production testing only. A.1.3.5 VREGEN This pin is used to enable the on chip voltage regulator.
A.1.4 Current Injection
Power supply must maintain regulation within operating VDD5 or VDD range during instantaneous and operating maximum current conditions. If positive injection current (Vin > VDD5) is greater than IDD5, the
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injection current may flow out of VDD5 and could result in external power supply going out of regulation. Ensure external VDD5 load will shunt current greater than maximum injection current. This will be the greatest risk when the MCU is not consuming power; e.g. if no system clock is present, or if clock rate is very low which would reduce overall power consumption.
A.1.5 Absolute Maximum Ratings
Absolute maximum ratings are stress ratings only. A functional operation under or outside those maxima is not guaranteed. Stress beyond those limits may affect the reliability or cause permanent damage of the device. This device contains circuitry protecting against damage due to high static voltage or electrical fields; however, it is advised that normal precautions be taken to avoid application of any voltages higher than maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (e.g., either VSS5 or VDD5). Table A-1 Absolute Maximum Ratings1
Num
1 2 3 4 5 6 7 8 9 10 11 12 15
Rating
I/O, Regulator and Analog Supply Voltage Internal Logic Supply Voltage 2 PLL Supply Voltage 2 Voltage difference VDDX to VDDR and VDDA Voltage difference VSSX to VSSR and VSSA Digital I/O Input Voltage Analog Reference XFC, EXTAL, XTAL inputs TEST input Instantaneous Maximum Current Single pin limit for all digital I/O pins 3 Instantaneous Maximum Current Single pin limit for XFC, EXTAL, XTAL4 Instantaneous Maximum Current Single pin limit for TEST 5 Storage Temperature Range
Symbol
VDD5 VDD VDDPLL ∆VDDX ∆VSSX VIN VRH, VRL VILV VTEST ID I
Min
-0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -25 -25 -0.25 – 65
Max
6.5 3.0 3.0 0.3 0.3 6.5 6.5 3.0 10.0 +25 +25 0 155
Unit
V V V V V V V V V mA mA mA °C
DL
IDT T
stg
NOTES: 1. Beyond absolute maximum ratings device might be damaged. 2. The device contains an internal voltage regulator to generate the logic and PLL supply out of the I/O supply. The absolute maximum ratings apply when the device is powered from an external source. 3. All digital I/O pins are internally clamped to VSSX and VDDX, VSSR and VDDR or VSSA and VDDA. 4. Those pins are internally clamped to VSSPLL and VDDPLL. 5. This pin is clamped low to VSSR, but not clamped high. This pin must be tied low in applications.
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A.1.6 ESD Protection and Latch-up Immunity
All ESD testing is in conformity with CDF-AEC-Q100 Stress test qualification for Automotive Grade Integrated Circuits. During the device qualification ESD stresses were performed for the Human Body Model (HBM), the Machine Model (MM) and the Charge Device Model. A device will be defined as a failure if after exposure to ESD pulses the device no longer meets the device specification. Complete DC parametric and functional testing is performed per the applicable device specification at room temperature followed by hot temperature, unless specified otherwise in the device specification. Table A-2 ESD and Latch-up Test Conditions
Model
Series Resistance Storage Capacitance Human Body Number of Pulse per pin positive negative Series Resistance Storage Capacitance Machine Number of Pulse per pin positive negative Minimum input voltage limit Latch-up Maximum input voltage limit 7.5 V
Description
Symbol
R1 C R1 C -
Value
1500 100 3 3 0 200 3 3 -2.5
Unit
Ohm pF
Ohm pF
V
Table A-3 ESD and Latch-Up Protection Characteristics
Num C
1 2 3 4
Rating
Symbol
VHBM VMM VCDM ILAT
Min
2000 200 500 +100 -100 +200 -200
Max
-
Unit
V V V mA
T Human Body Model (HBM) T Machine Model (MM) T Charge Device Model (CDM) Latch-up Current at TA = 125°C T positive negative Latch-up Current at TA = 27°C T positive negative
5
ILAT
-
mA
A.1.7 Operating Conditions
This chapter describes the operating conditions of the device. Unless otherwise noted those conditions apply to all the following data.
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NOTE:
Please refer to the temperature rating of the device (C, V, M) with regards to the ambient temperature TA and the junction temperature TJ. For power dissipation calculations refer to Section A.1.8 Power Dissipation and Thermal Characteristics. Table A-4 Operating Conditions
Rating Symbol
VDD5 VDD VDDPLL ∆VDDX ∆VSSX fbus
Min
2.97 2.35 2.35 -0.1 -0.1 0.252
Typ
5 2.5 2.5 0 0 -
Max
5.5 2.75 2.75 0.1 0.1 253
Unit
V V V V V MHz
I/O, Regulator and Analog Supply Voltage Internal Logic Supply Voltage 1 PLL Supply Voltage 1 Voltage Difference VDDX to VDDR and VDDA Voltage Difference VSSX to VSSR and VSSA Bus Frequency MC9S12B128C Operating Junction Temperature Range Operating Ambient Temperature Range 4 MC9S12B128V Operating Junction Temperature Range Operating Ambient Temperature Range 4 MC9S12B128M Operating Junction Temperature Range Operating Ambient Temperature Range 4
T T
J
-40 -40
27
100 85
°C °C
A
TJ TA
-40 -40
27
120 105
°C °C
TJ TA
-40 -40
27
140 125
°C °C
NOTES: 1. The device contains an internal voltage regulator to generate the logic and PLL supply out of the I/O supply. This applies when this regulator is disabled and the device is powered from an external source. 2. Some blocks e.g. ATD (conversion) and NVMs (program/erase) require higher bus frequencies for proper operation. 3. See bus speed option at Table 0-1 Derivative Differences 4. Please refer to Section A.1.8 Power Dissipation and Thermal Characteristics for more details about the relation between ambient temperature TA and device junction temperature TJ.
A.1.8 Power Dissipation and Thermal Characteristics
Power dissipation and thermal characteristics are closely related. The user must assure that the maximum operating junction temperature is not exceeded. The average chip-junction temperature (TJ) in °C can be obtained from: T J = T A + ( P D • Θ JA ) T J = Junction Temperature, [ ° C ] T A = Ambient Temperature, [ ° C ]
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P D = Total Chip Power Dissipation, [W] Θ JA = Package Thermal Resistance, [ ° C/W] The total power dissipation can be calculated from: P D = P INT + P IO P INT = Chip Internal Power Dissipation, [W]
Two cases with internal voltage regulator enabled and disabled must be considered: 1. Internal Voltage Regulator disabled P INT = I DD ⋅ V DD + I DDPLL ⋅ V DDPLL + I DDA ⋅ V DDA 2 P IO = R DSON ⋅ I IO i i
∑
PIO is the sum of all output currents on I/O ports associated with VDDX and VDDR. For RDSON is valid: V OL R DSON = ----------- ;for outputs driven low I OL
V DD5 – V OH R DSON = ----------------------------------- ;for outputs driven high I OH 2. Internal voltage regulator enabled P INT = I DDR ⋅ V DDR + I DDA ⋅ V DDA IDDR is the current shown in Table A-8 and not the overall current flowing into VDDR, which additionally contains the current flowing into the external loads with output high. 2 P IO = R DSON ⋅ I IO i i
respectively
∑
PIO is the sum of all output currents on I/O ports associated with VDDX and VDDR.
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Table A-5 Thermal Package Characteristics1
Num C
1 2 3 4 5 6 7 8 9 10
Rating
Symbol
θJA θJA θJB θJC ΨJT θJA θJA θJB θJC ΨJT
Min
– – – – – – – – – –
Typ
– – – – – – – – – –
Max
54 41 31 11 2 51 41 27 14 3
Unit
o
T Thermal Resistance LQFP112, single sided PCB2 T Thermal Resistance LQFP112, double sided PCB with 2 internal planes3
C/W C/W
o
T Junction to Board LQFP112 T Junction to Case LQFP112 T Junction to Package Top LQFP112 T Thermal Resistance QFP 80, single sided PCB T Thermal Resistance QFP 80, double sided PCB with 2 internal planes
oC/W o o
C/W C/W
oC/W oC/W oC/W oC/W oC/W
T Junction to Board QFP80 T Junction to Case QFP80 T Junction to Package Top QFP80
NOTES: 1. The values for thermal resistance are achieved by package simulations 2. PC Board according to EIA/JEDEC Standard 51-3 3. PC Board according to EIA/JEDEC Standard 51-7
A.1.9 I/O Characteristics
This section describes the characteristics of all 5V I/O pins. All parameters are not always applicable, e.g. not all pins feature pull up/down resistances.
87
Device User Guide — 9S12B128DGV1/D V01.13
Table A-6 5V I/O Characteristics
Conditions are 4.5< VDDX
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