MCM64Z836ZP8.5

MOTOROLA Freescale Semiconductor, Inc. SEMICONDUCTOR TECHNICAL DATA Order this document by MCM64Z836/D Product Preview 256K x 36 and 512K x 18 Bit ZBTr Fast Static RAM MCM64Z836 MCM64Z918 Freescale Semiconductor, Inc... The ZBT RAM is an 8M–bit synchronous fast static RAM designed to provide Zero Bus Turnaroundr. The ZBT RAM allows 100% use of bus cycles during back–to–back read/write and write/read cycles. The MCM64Z836 (organized as 256K words by 36 bits) and the MCM64Z918 (organized as 512K words by 18 bits) are fabricated in Motorola’s high performance silicon gate CMOS technology. This device integrates input registers, an output register, a 2–bit address counter, and high speed SRAM onto a single monolithic circuit for reduced parts count in communication applications. Synchronous design allows precise cycle control with the use of an external positive–edge–triggered clock (CK). CMOS circuitry reduces the overall power consumption of the integrated functions for greater reliability. Addresses (SA), data inputs (DQ), and all control signals except output enable (G) and linear burst order (LBO) are clock (CK) controlled through positive– edge–triggered noninverting registers. Write cycles are internally self–timed and are initiated by the rising edge of the clock (CK) input. This feature eliminates complex off–chip write pulse generation and provides increased timing flexibility for incoming signals. Write data is supplied to the memory one cycle after the write sequence initiation for the flow– through device, and two cycles after the write sequence initiation for the pipelined device. For flow–through read cycles, the SRAM allows output data to simply flow freely from the memory array. For pipelined read cycles, the SRAM output data is temporarily stored by an edge–triggered output register and then released to the output buffers at the next rising edge of clock (CK). The MCM64Z836 and MCM64Z918 operate from a 2.5 V core power supply and all outputs operate on a 2.5 V power supply. All inputs and outputs are JEDEC Standard JESD8–5 compatible. • 2.5 V ±200 mV Core Power Supply, 2.5 V I/O Supply • MCM64Z836 / 918–7 = 7 ns Flow–Through Access / 2.6 ns Pipelined Access (225 MHz) MCM64Z836 / 918–8 = 8 ns Flow–Through Access / 3 ns Pipelined Access (200 MHz) MCM64Z836 / 918–8.5 = 8.5 ns Flow–Through Access / 3.5 ns Pipelined Access (166 MHz) • Selectable Read/Write Functionality (Flow–Through/Pipelined) • Selectable Burst Sequencing Order (Linear/Interleaved) • Internally Self–Timed Write Cycle • Two–Cycle Deselect (Pipelined) • Byte Write Control • ADV Controlled Burst • Simplified JTAG • 100–Pin TQFP and 119–Bump PBGA Packages TQ PACKAGE TQFP CASE 983A–01 ZP PACKAGE PBGA CASE 999–02 ZBT and Zero Bus Turnaround are trademarks of Integrated Device Technology, Inc., and the architecture is supported by Micron Technology, Inc. and Motorola, Inc. This document contains information on a new product under development. Motorola reserves the right to change or discontinue this product without notice. REV 3 9/1/99 © Motorola, Inc. 1999 MOTOROLA FAST SRAM For More Information On This Product, Go to: www.freescale.com MCM64Z836•MCM64Z918 1 Freescale Semiconductor, Inc. LOGIC BLOCK DIAGRAM LBO BURST ADDRESS COUNTER ADDRESS REGISTER MEMORY ARRAY SA DATA–IN REGISTER CK CONTROL LOGIC CKE K WRITE ADDRESS REGISTER WRITE ADDRESS REGISTER K Freescale Semiconductor, Inc... K DATA–IN REGISTER* SE1 SE2 SE3 ADV SW SBx G CONTROL REGISTER CONTROL LOGIC K DATA–OUT REGISTER* DQ * Valid only for pipelined device. MCM64Z836•MCM64Z918 2 For More Information On This Product, Go to: www.freescale.com MOTOROLA FAST SRAM Freescale Semiconductor, Inc. MCM64Z836 PIN ASSIGNMENTS SA SA SE1 SE2 SBd SBc SBb SBa SE3 VDD VSS CK SW CKE G ADV NC SA SA SA 1 DQb DQb DQb VDDQ VSS DQb DQb DQb DQb VSS VDDQ DQb DQb VSS FT VDD VSS DQa DQa VDDQ VSS DQa DQa DQa DQa VSS VDDQ DQa DQa DQa A B NC C D DQc E DQc F G DQc H DQc J K DQd L DQd M VDDQ N DQd P DQd R T NC U NC SA TDI SA TCK SA NC VSS VDDQ TMS TDO TRST VDDQ VDD DQd SA VSS LBO SA0 VDD VSS FT DQa SA DQa NC DQd VSS SA1 VSS DQa DQa DQd VSS CKE VSS DQa VDDQ DQd SBd NC SBa DQa DQa DQd VSS CK VSS DQa DQa DQc VSS SW VSS FT DQb DQb VDDQ VDD VDD VDD VDD VDDQ DQc SBc SA SBb DQb DQb VDDQ DQc DQc VSS VSS SE1 G VSS VSS DQb DQb DQb VDDQ DQc VSS NC VSS DQb DQb NC SE2 SA SA SA ADV VDD SA SA SE3 SA NC NC VDDQ 2 SA 3 SA 4 NC 5 SA 6 SA 7 VDDQ Freescale Semiconductor, Inc... DQc DQc DQc VDDQ VSS DQc DQc DQc DQc VSS VDDQ DQc DQc FT VDD VDD VSS DQd DQd VDDQ VSS DQd DQd DQd DQd VSS VDDQ DQd DQd DQd 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 1 80 2 79 3 78 4 77 5 76 6 75 7 74 8 73 9 72 10 71 11 70 12 69 13 68 14 67 15 66 16 65 17 64 18 63 19 62 20 61 21 60 22 59 23 58 24 57 25 56 26 55 27 54 28 53 29 52 30 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 LBO SA SA SA SA SA1 SA0 NC NC VSS VDD NC NC SA SA SA SA SA SA SA 100–PIN TQFP TOP VIEW 119–BUMP PGBA TOP VIEW Not to Scale MOTOROLA FAST SRAM For More Information On This Product, Go to: www.freescale.com MCM64Z836•MCM64Z918 3 Freescale Semiconductor, Inc. MCM64Z836 TQFP PIN DESCRIPTIONS Pin Locations 85 89 87 (a) 51, 52, 53, 56, 57, 58, 59, 62, 63 (b) 68, 69, 72, 73, 74, 75, 78, 79, 80 (c) 1, 2, 3, 6, 7, 8, 9, 12, 13 (d) 18, 19, 22, 23, 24, 25, 28, 29, 30 14, 66 Symbol ADV CK CKE DQx Type Input Input Input I/O Description Synchronous Load/Advance: Loads a new address into counter when low. RAM uses internally generated burst addresses when high. Clock: This signal registers the address, data in, and all control signals except G and LBO. Clock Enable: Disables the CK input when CKE is high. Synchronous Data I/O: “x” refers to the byte being read or written (byte a, b, c, d). FT Input Flow–Through Option Input: This pin must remain in steady state (this signal is not registered or latched). It must be tied high or low. Low — flow–through functionality. High — pipelined functionality. Asynchronous Output Enable. Linear Burst Order Input: This pin must remain in steady state (this signal not registered or latched). It must be tied high or low. Low — linear burst counter. High — interleaved burst counter. Synchronous Address Inputs: These inputs are registered and must meet setup and hold times. Synchronous Burst Address Inputs: The two LSB’s of the address field. These pins must preset the burst address counter values. These inputs are registered and must meet setup and hold times. Synchronous Byte Write Inputs: Enables write to byte “x” (byte a, b, c, d) in conjunction with SW. Has no effect on read cycles. Synchronous Chip Enable: Active low to enable chip. Synchronous Chip Enable: Active high for depth expansion. Synchronous Chip Enable: Active low for depth expansion. Synchronous Write: This signal writes only those bytes that have been selected using the byte write SBx pins. Core Power Supply. I/O Power Supply. Ground. No Connection: There is no connection to the chip. 86 G LBO Input Input Freescale Semiconductor, Inc... 31 32, 33, 34, 35, 44, 45, 46, 47, 48, 49, 50, 81, 82, 83, 99, 100 37, 36 SA SA0, SA1 Input Input 93, 94, 95, 96 (a) (b) (c) (d) 98 97 92 88 15, 16, 41, 65, 91 4, 11, 20, 27, 54, 61, 70, 77 5, 10, 17, 21, 26, 40, 55, 60, 64, 67, 71, 76, 90 38, 39, 42, 43, 84 SBx SE1 SE2 SE3 SW VDD VDDQ VSS NC Input Input Input Input Input Supply Supply Supply — MCM64Z836•MCM64Z918 4 For More Information On This Product, Go to: www.freescale.com MOTOROLA FAST SRAM Freescale Semiconductor, Inc. MCM64Z836 PBGA PIN DESCRIPTIONS Pin Locations 4B 4K 4M (a) 6K, 7K, 6L, 7L, 6M, 6N, 7N, 6P, 7P (b) 6D, 7D, 6E, 7E, 6F, 6G, 7G, 6H, 7H (c) 1D, 2D, 1E, 2E, 2F, 1G, 2G, 1H, 2H (d) 1K, 2K, 1L, 2L, 2M, 1N, 2N, 1P, 2P 5J, 5R Symbol ADV CK CKE DQx Type Input Input Input I/O Description Synchronous Load/Advance: Loads a new address into counter when low. RAM uses internally generated burst addresses when high. Clock: This signal registers the address, data in, and all control signals except G and LBO. Clock Enable: Disables the CK input when CKE is high. Synchronous Data I/O: “x” refers to the byte being read or written (byte a, b, c, d). FT Input Flow–Through Option Input: This pin must remain in steady state (this signal is not registered or latched). It must be tied high or low. Low — flow–through functionality. High — pipelined functionality. Asynchronous Output Enable. Linear Burst Order Input: This pin must remain in steady state (this signal not registered or latched). It must be tied high or low. Low — linear burst counter. High — interleaved burst counter. Synchronous Address Inputs: These inputs are registered and must meet setup and hold times. Synchronous Burst Address Inputs: The two LSBs of the address field. These pins must preset the burst address counter values. These inputs are registered and must meet setup and hold times. Synchronous Byte Write Inputs: Enables write to byte “x” (byte a, b, c, d) in conjunction with SW. Has no effect on read cycles. Synchronous Chip Enable: Active low to enable chip. Synchronous Chip Enable: Active high for depth expansion. Synchronous Chip Enable: Active low for depth expansion. Synchronous Write: This signal writes only those bytes that have been selected using the byte write SBx pins. Boundary Scan Pin, Test Clock: If boundary scan is not used, TCK must be tied to VDD or VSS. Boundary Scan Pin, Test Data In. Boundary Scan Pin, Test Data Out. Boundary Scan Pin, Test Mode Select. Boundary Scan Pin, Asynchronous Test Reset. If boundary scan is not used, TRST must be tied to VSS. Core Power Supply. I/O Power Supply. Ground. No Connection: There is no connection to the chip. 4F G LBO Input Input Freescale Semiconductor, Inc... 3R 2A, 3A, 5A, 6A, 3B, 5B, 2C, 3C, 5C, 6C, 4G, 2R, 6R, 3T, 4T, 5T 4N, 4P SA SA1, SA0 Input Input 5L, 5G, 3G, 3L (a) (b) (c) (d) 4E 2B 6B 4H 4U 3U 5U 2U 6U 4C, 2J, 3J, 4J, 6J, 1R, 4R 1A, 7A, 1F, 7F, 1J, 7J, 1M, 7M, 1U, 7U 3D, 5D, 3E, 5E, 3F, 5F, 3H, 5H, 3K, 5K, 3L, 3M, 5M, 3N, 5N, 3P, 5P, 7T 4A, 1B, 7B, 1C, 7C, 4D, 7R, 1T, 2T, 6T SBx SE1 SE2 SE3 SW TCK TDI TDO TMS TRST VDD VDDQ VSS NC Input Input Input Input Input Input Input Output Input Input Supply Supply Supply — MOTOROLA FAST SRAM For More Information On This Product, Go to: www.freescale.com MCM64Z836•MCM64Z918 5 Freescale Semiconductor, Inc. MCM64Z918 PIN ASSIGNMENTS SA SA SE1 SE2 NC NC SBb SBa SE3 VDD VSS CK SW CKE G ADV NC SA SA SA 1 SA NC NC VDDQ VSS NC DQa DQa DQa VSS VDDQ DQa DQa VSS FT VDD VSS DQa DQa VDDQ VSS DQa DQa NC NC VSS VDDQ NC NC NC A VDDQ B NC C NC D DQb E NC F G H DQb J K NC L DQb M N DQb P NC R VDD T NC U VDDQ NC 2 3 4 5 6 7 Freescale Semiconductor, Inc... NC NC NC VDDQ VSS NC NC DQb DQb VSS VDDQ DQb DQb FT VDD VDD VSS DQb DQb VDDQ VSS DQb DQb DQb NC VSS VDDQ NC NC NC 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 1 80 2 79 3 78 4 77 5 76 6 75 7 74 8 73 9 72 10 71 11 70 12 69 13 68 14 67 15 66 16 65 17 64 18 63 19 62 20 61 21 60 22 59 23 58 24 57 25 56 26 55 27 54 28 53 29 52 30 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 LBO SA SA SA SA SA1 SA0 NC NC VSS VDD NC NC SA SA SA SA SA SA SA SA SE2 SA NC DQb NC DQb NC SA SA SA VSS VSS VSS SBb VSS NC ADV VDD NC SE1 G SA SW SA SA SA VSS VSS VSS VSS VSS FT VSS SBa VSS VSS VSS FT SA SA SE3 SA DQa NC DQa NC DQa VDDQ NC NC NC DQa VDDQ DQa NC VDDQ VDD DQb NC VDD VDD VSS VSS VSS VSS VSS LBO SA TDI CK NC CKE SA1 SA0 VDD NC TCK VDD VDDQ NC DQa NC DQa NC SA SA DQa NC VDDQ NC DQa NC VSS VDDQ DQb NC DQb SA SA VDDQ TMS TDO TRST VDDQ 100–PIN TQFP TOP VIEW 119–BUMP PGBA TOP VIEW Not to Scale MCM64Z836•MCM64Z918 6 For More Information On This Product, Go to: www.freescale.com MOTOROLA FAST SRAM Freescale Semiconductor, Inc. MCM64Z918 TQFP PIN DESCRIPTIONS Pin Locations 85 89 87 (a) 58, 59, 62, 63, 68, 69, 72, 73, 74 (b) 8, 9, 12, 13, 18, 19, 22, 23, 24 14, 66 Symbol ADV CK CKE DQx FT Type Input Input Input I/O Input Description Synchronous Load/Advance: Loads a new address into counter when low. RAM uses internally generated burst addresses when high. Clock: This signal registers the address, data in, and all control signals except G and LBO. Clock Enable: Disables the CK input when CKE is high. Synchronous Data I/O: “x” refers to the byte being read or written (byte a, b). Flow–Through Option Input: This pin must remain in steady state (this signal is not registered or latched). It must be tied high or low. Low — flow–through functionality. High — pipelined functionality. Asynchronous Output Enable. Linear Burst Order Input: This pin must remain in steady state (this signal not registered or latched). It must be tied high or low. Low — linear burst counter. High — interleaved burst counter. Synchronous Address Inputs: These inputs are registered and must meet setup and hold times. Synchronous Burst Address Inputs: The two LSB’s of the address field. These pins must preset the burst address counter values. These inputs are registered and must meet setup and hold times. Synchronous Byte Write Inputs: Enables write to byte “x” (byte a, b) in conjunction with SW. Has no effect on read cycles. Synchronous Chip Enable: Active low to enable chip. Synchronous Chip Enable: Active high for depth expansion. Synchronous Chip Enable: Active low for depth expansion. Synchronous Write: This signal writes only those bytes that have been selected using the byte write SBx pins. Core Power Supply. I/O Power Supply. Ground. No Connection: There is no connection to the chip. 86 31 G LBO Input Input Freescale Semiconductor, Inc... 32, 33, 34, 35, 44, 45, 46, 47, 48, 49, 50, 80, 81, 82, 83, 99, 100 37, 36 SA SA0, SA1 Input Input 93, 94 (a) (b) 98 97 92 88 15, 16, 41, 65, 91 4, 11, 20, 27, 54, 61, 70, 77 5, 10, 17, 21, 26, 40, 55, 60, 64, 67, 71, 76, 90 1, 2, 3, 6, 7, 25, 28, 29, 30, 38, 39, 42, 43, 51, 52, 53, 56, 57, 75, 78, 79, 84, 95, 96 SBx SE1 SE2 SE3 SW VDD VDDQ VSS NC Input Input Input Input Input Supply Supply Supply — MOTOROLA FAST SRAM For More Information On This Product, Go to: www.freescale.com MCM64Z836•MCM64Z918 7 Freescale Semiconductor, Inc. MCM64Z918 PBGA PIN DESCRIPTIONS Pin Locations 4B 4K 4M (a) 6D, 7E, 6F, 7G, 6H, 7K, 6L, 6N, 7P (b) 1D, 2E, 2G, 1H, 2K, 1L, 2M, 1N, 2P 5J, 5R Symbol ADV CK CKE DQx FT Type Input Input Input I/O Input Description Synchronous Load/Advance: Loads a new address into counter when low. RAM uses internally generated burst addresses when high. Clock: This signal registers the address, data in, and all control signals except G and LBO. Clock Enable: Disables the CK input when CKE is high. Synchronous Data I/O: “x” refers to the byte being read or written (byte a, b). Flow–Through Option Input: This pin must remain in steady state (this signal is not registered or latched). It must be tied high or low. Low — flow–through functionality. High — pipelined functionality. Asynchronous Output Enable. Linear Burst Order Input: This pin must remain in steady state (this signal not registered or latched). It must be tied high or low. Low — linear burst counter. High — interleaved burst counter. Synchronous Address Inputs: These inputs are registered and must meet setup and hold times. Synchronous Address Inputs: These pins must be wired to the two LSBs of the address bus for proper burst operation. These inputs are registered and must meet setup and hold times. Synchronous Byte Write Inputs: Enables write to byte “x” (byte a, b) in conjunction with SW. Has no effect on read cycles. Synchronous Chip Enable: Active low to enable chip. Synchronous Chip Enable: Active high for depth expansion. Synchronous Chip Enable: Active low for depth expansion. Synchronous Write: This signal writes only those bytes that have been selected using the byte write SBx pins. Boundary Scan Pin, Test Clock: If boundary scan is not used, TCK must be tied to VDD or VSS. Boundary Scan Pin, Test Data In. Boundary Scan Pin, Test Data Out. Boundary Scan Pin, Test Mode Select. Boundary Scan Pin, Asynchronous Test Reset. If boundary scan is not used, TRST must be tied to VSS. Core Power Supply. I/O Power Supply. Ground. No Connection: There is no connection to the chip. 4F 3R G LBO Input Input Freescale Semiconductor, Inc... 2A, 3A, 5A, 6A, 3B, 5B, 2C, 3C, 5C, 6C, 4G, 2R, 6R, 2T, 3T, 5T, 6T 4N, 4P SA SA1, SA0 Input Input 5L, 3G (a) (b) 4E 2B 6B 4H 4U 3U 5U 2U 6U 4C, 2J, 3J, 4J, 6J, 1R, 4R 1A, 7A, 1F, 7F, 1J, 7J, 1M, 7M, 1U, 7U 3D, 5D, 3E, 5E, 3F, 5F, 5G, 3H, 5H, 3K, 5K, 3L, 3M, 5M, 3N, 5N, 3P, 5P, 7T 4A, 1B, 7B, 1C, 7C, 2D, 4D, 7D, 1E, 6E, 2F, 1G, 6G, 2H, 7H, 1K, 6K, 2L, 4L, 7L, 6M, 2N, 7N, 1P, 6P, 7R, 1T, 4T SBx SE1 SE2 SE3 SW TCK TDI TDO TMS TRST VDD VDDQ VSS NC Input Input Input Input Input Input Input Output Input Input Supply Supply Supply — MCM64Z836•MCM64Z918 8 For More Information On This Product, Go to: www.freescale.com MOTOROLA FAST SRAM Freescale Semiconductor, Inc. TRUTH TABLE CK L–H L–H L–H L–H L–H CKE 1 0 0 0 0 E X False True True X SW X X 0 1 X SBx X X V X V (W) X (R, D) ADV X 0 0 0 1 SA0 – SAx X X V V X Hold Deselect Load Address, New Write Load Address, New Read Burst Continue Next Operation Input Command Code H D W R B Notes 1, 2 1, 2 1, 2, 3, 4, 5 1, 2 1, 2, 4, 6, 67 Freescale Semiconductor, Inc... NOTES: 1. X = don‘t care, 1 = logic high, 0 = logic low, V = valid signal, according to AC Operating Conditions and Characteristics. 2. E = true if SE1 and SE3 = 0, and SE2 = 1. 3. Byte write enables, SBx are evaluated only as new write addresses are loaded. 4. No control inputs except CKE, SBx, and ADV are recognized in a clock cycle where ADV is sampled high. 5. A write with SBx not valid does load addresses. 6. A burst write with SBx not valid does increment address. 7. ADV controls whether the RAM enters burst mode. If the previous cycle was a write, then ADV = 1 results in a burst write. If the previous cycle is a read, then ADV = 1 results in a burst read. ADV = 1 will also continue a deslect cycle. ASYNCHRONOUS TRUTH TABLE Operation Read Read Write Deselected G L H X X I/O Status Data Out (DQx) High–Z High–Z High–Z WRITE TRUTH TABLE Cycle Type Read Write Byte a Write Byte b Write Byte c (See Note 1) Write Byte d (See Note 1) Write All Bytes NOTE: 1. Valid only for the MCM64Z836. SW H L L L L L SBa X L H H H L SBb X H L H H L SBc (See Note 1) X H H L H L SBd (See Note 1) X H H H L L LINEAR BURST ADDRESS TABLE (LBO = VSS) 1st Address (External) X . . . X00 X . . . X01 X . . . X10 X . . . X11 2nd Address (Internal) X . . . X01 X . . . X10 X . . . X11 X . . . X00 3rd Address (Internal) X . . . X10 X . . . X11 X . . . X00 X . . . X01 4th Address (Internal) X . . . X11 X . . . X00 X . . . X01 X . . . X10 INTERLEAVED BURST ADDRESS TABLE (LBO = VDD) 1st Address (External) X . . . X00 X . . . X01 X . . . X10 X . . . X11 2nd Address (Internal) X . . . X01 X . . . X00 X . . . X11 X . . . X10 3rd Address (Internal) X . . . X10 X . . . X11 X . . . X00 X . . . X01 4th Address (Internal) X . . . X11 X . . . X10 X . . . X01 X . . . X00 MOTOROLA FAST SRAM For More Information On This Product, Go to: www.freescale.com MCM64Z836•MCM64Z918 9 Freescale Semiconductor, Inc. INPUT COMMAND CODE AND STATE NAME DEFINITION DIAGRAM INPUT COMMAND CODE CK D DESELECT B W NEW WRITE B R NEW READ B H HOLD CONTINUE DESELECT BURST WRITE BURST READ CKE E FALSE TRUE TRUE SA0 – SAx VALID VALID Freescale Semiconductor, Inc... ADV SW SBX VALID VALID NOTE: Cycles are named for their control inputs, not for data I/O state. MCM64Z836•MCM64Z918 10 For More Information On This Product, Go to: www.freescale.com MOTOROLA FAST SRAM Freescale Semiconductor, Inc. B B D R BURST READ W R B NEW WRITE W D BURST WRITE W D B D R NEW READ W R B Freescale Semiconductor, Inc... R DESELECT W KEY: CURRENT STATE (n) ƒ TRANSITION NEXT STATE (n + 1) D INPUT COMMAND CODE NOTES: 1. Input command codes (D, W, R, and B) represent control pin inputs as indicated in the Truth Table. 2. Hold (i.e., CKE sampled high) is not shown simply because CKE = 1 blocks clock input and therefore, blocks any state change. Figure 1. ZBT RAM State Diagram MOTOROLA FAST SRAM For More Information On This Product, Go to: www.freescale.com MCM64Z836•MCM64Z918 11 Freescale Semiconductor, Inc. STATE CK n n+1 n+2 n+3 COMMAND CODE ƒ DQ CURRENT STATE NEXT STATE Figure 2. State Definitions for ZBT RAM State Diagram (Flow–Through) Freescale Semiconductor, Inc... STATE CK n n+1 n+2 n+3 COMMAND CODE ƒ DQ CURRENT STATE NEXT STATE Figure 3. State Definitions for ZBT RAM State Diagram (Pipelined) MCM64Z836•MCM64Z918 12 For More Information On This Product, Go to: www.freescale.com MOTOROLA FAST SRAM Freescale Semiconductor, Inc. D B HIGH–Z R W Freescale Semiconductor, Inc... R B DATA OUT (Q VALID) D D W R HIGH–Z (DATA IN) W B KEY: CURRENT STATE (n) ƒ INPUT COMMAND CODE NEXT STATE n+1 NOTES: 1. Input command codes (D, W, R, and B) represent control pin inputs as indicated in the Truth Table. 2. Hold (i.e., CKE sampled high) is not shown simply because CKE = 1 blocks clock input and therefore, blocks any state change. Figure 4. Data I/O State Diagram (Flow–Through) STATE CK n n+1 n+2 n+3 COMMAND CODE ƒ DQ CURRENT STATE NEXT STATE Figure 5. State Definitions for ZBT RAM State Diagram (Flow–Through) MOTOROLA FAST SRAM For More Information On This Product, Go to: www.freescale.com MCM64Z836•MCM64Z918 13 Freescale Semiconductor, Inc. INTERMEDIATE D B HIGH–Z R W INTERMEDIATE INTERMEDIATE Freescale Semiconductor, Inc... R B INTERMEDIATE DATA OUT (Q VALID) D D W INTERMEDIATE R HIGH–Z (DATA IN) W B INTERMEDIATE KEY: CURRENT STATE (n) ƒ INTERMEDIATE STATE (n + 1) TRANSITION TRANSITION NEXT STATE (n + 2) NOTES: 1. Input command codes (D, W, R, and B) represent control pin inputs as indicated in the Truth Table. 2. Hold (i.e., CKE sampled high) is not shown simply because CKE = 1 blocks clock input and therefore, blocks any state change. INPUT COMMAND CODE Figure 6. Data I/O State Diagram (Pipelined) STATE CK n n+1 n+2 n+3 COMMAND CODE ƒ DQ STATE NAME CURRENT STATE INTERMEDIATE STATE NEXT STATE Figure 7. State Definitions for I/O State Diagram (Pipelined) MCM64Z836•MCM64Z918 14 For More Information On This Product, Go to: www.freescale.com MOTOROLA FAST SRAM Freescale Semiconductor, Inc. ABSOLUTE MAXIMUM RATINGS (See Note 1) Rating Power Supply Voltage I/O Supply Voltage Input Voltage Relative to VSS for Any Pin Except VDD Input Voltage (Three State I/O) Output Current (per I/O) Package Power Dissipation Temperature Under Bias Storage Temperature Symbol VDD VDDQ Vin, Vout VIT Iout PD Tbias Tstg Value –0.5 to 3.6 VSS – 0.5 to VDD –0.5 to VDD + 0.5 VSS – 0.5 to VDDQ + 0.5 ±20 1.3 –10 to 85 –55 to 125 Unit V V V V mA W °C °C 3 2 2 2 Notes This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this high–impedance circuit. Freescale Semiconductor, Inc... NOTES: 1. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to RECOMMENDED OPERATING CONDITIONS. Exposure to higher than recommended voltages for extended periods of time could affect device reliability. 2. This is a steady–state DC parameter that is in effect after the power supply has achieved its nominal operating level. Power sequencing is not necessary. 3. Power dissipation capability is dependent upon package characteristics and use environment. See Package Thermal Characteristics. PACKAGE THERMAL CHARACTERISTICS Thermal Resistance Junction to Ambient (@ 200 lfm) Junction to Board (Bottom) Junction to Case (Top) Single–Layer Board Four–Layer Board Symbol RθJA RθJB RθJC Max 40 25 17 9 Unit °C/W °C/W °C/W Notes 1, 2 3 4 NOTES: 1. Junction temperature is a function of on–chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, board population, and board thermal resistance. 2. Per SEMI G38–87. 3. Indicates the average thermal resistance between the die and the printed circuit board. 4. Indicates the average thermal resistance between the die and the case top surface via the cold plate method (MIL SPEC–883 Method 1012.1). MOTOROLA FAST SRAM For More Information On This Product, Go to: www.freescale.com MCM64Z836•MCM64Z918 15 Freescale Semiconductor, Inc. DC OPERATING CONDITIONS AND CHARACTERISTICS (VDD = 2.5 V ±200 mV, TA = 0 to 70°C Unless Otherwise Noted) RECOMMENDED OPERATING CONDITIONS AND DC CHARACTERISTICS (Voltages Referenced to VSS = 0 V) Parameter Supply Voltage I/O Supply Voltage Input Low Voltage Input High Voltage Input High Voltage I/O Pins Output Low Voltage (IOL = 2 mA) Output High Voltage (IOL = –2 mA) Symbol VDD VDDQ VIL VIH VIH2 VOL VOH Min 2.3 2.3 –0.3 1.7 1.7 — 1.7 Typ 2.5 2.5 — — — — — Max 2.7 VDD 0.7 VDD + 0.3 VDDQ + 0.3 0.7 — Unit V V V V V V V Freescale Semiconductor, Inc... VIH VSS VSS – 1.0 V 20% tKHKH (MIN) Figure 8. Undershoot Voltage DC CHARACTERISTICS AND SUPPLY CURRENTS Parameter Input Leakage Current (0 V ≤ Vin ≤ VDD) Output Leakage Current (0 V ≤ Vin ≤ VDDQ) AC Supply Current (Device Selected, All Outputs Open, Freq = Max) Includes Supply Current for Both VDD and VDDQ CMOS Standby Supply Current (Device Deselected, Freq = 0, VDD = Max, VDDQ = Max, All Inputs Static at CMOS Levels) Clock Running (Device Deselected, Freq = Max, VDD = Max, All Inputs Toggling at CMOS Levels) Hold Supply Current (Device Selected, Freq = Max, VDD = Max, VDDQ = Max, CKE ≥ VDD – 0.2 V, All Inputs Static at CMOS Levels) Symbol Ilkg(I) Ilkg(O) IDDA–7 IDDA–8 IDDA–8.5 ISB2 Min — — — — — — Typ — — — — — — Max ±1 ±1 270/300 250/290 250/280 10 Unit µA µA mA 2, 3, 4, 5 6, 7 Notes 1 mA ISB4–7 ISB4–8 ISB4–8.5 IDD1 — — — — — — — — 100/100 100/100 90/90 15 mA 5, 6, 8 mA 7 NOTES: 1. LBO has an internal pull–up will exhibit leakage currents of ±5 µA. 2. Reference AC Operating Conditions and Characteristics for input and timing. 3. All addresses transition simultaneously low (LSB) then high (MSB). 4. Data states are all zero. 5. Flow–through/pipelined current. 6. Device in deselected mode as defined by the Truth Table. 7. CMOS levels for I/Os are VIT ≤ VSS + 0.2 V or ≥ VDDQ – 0.2 V. CMOS levels for other inputs are Vin ≤ VSS + 0.2 V or ≥ VDD – 0.2 V. 8. TTL levels for I/Os are VIT ≤ VIL or ≥ VIH2. TTL levels for other inputs are Vin ≤ VIL or ≥ VIH. MCM64Z836•MCM64Z918 16 For More Information On This Product, Go to: www.freescale.com MOTOROLA FAST SRAM Freescale Semiconductor, Inc. CAPACITANCE (f = 1.0 MHz, TA = 0 to 70°C, Periodically Sampled Rather Than 100% Tested) Parameter Input Capacitance Input/Output Capacitance Symbol Cin CI/O Min — — Typ 2 3 Max 4 5 Unit pF pF AC OPERATING CONDITIONS AND CHARACTERISTICS (VDD = 2.5 V ±5%, TA = 0 to 70°C Unless Otherwise Noted) Input Timing Measurement Reference Level . . . . . . . . . . . . . . 1.25 V Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 2.5 V Input Rise/Fall Time (Flow–Through) . . . . . . 1.0 V/ns (20% to 80%) Input Rise/Fall Time (Pipelined) . . . . . . . . . . 2.5 V/ns (20% to 80%) Output Timing Reference Level . . . . . . . . . . . . . . . . . . . . . . . . . 1.25 V Output Load . . . . . . . . . . . . . . See Figure 9 Unless Otherwise Noted FLOW–THROUGH READ/WRITE CYCLE TIMING (See Notes 1 and 2) MCM64Z836–7 MCM64Z918–7 MCM64Z836–8 MCM64Z918–8 Min 10.5 4.2 4.2 — — 4 2 0 — 1.5 1.5 1.5 1.5 1.5 1.5 1.5 0.5 Max — — — 8 3.5 — — — 3.5 4 — MCM64Z836–8.5 MCM64Z918–8.5 Min 11 4.4 4.4 — — 4 2 0 — 1.5 2 2 2 2 2 2 0.5 Max — — — 8.5 5 — — — 5 4 — Unit Ui ns ns ns ns ns ns ns ns ns ns ns 4, 5 4 4, 5 4, 5 4, 5 3 3 Notes N Freescale Semiconductor, Inc... Parameter P Cycle Time Clock High Pulse Width Clock Low Pulse Width Clock Access Time Output Enable to Output Valid Clock High to Output Active Output Hold Time Output Enable to Output Active Output Disable to Q High–Z Clock High to Q High–Z Setup Times: Address ADV Data In Write Chip Enable Clock Enable Address ADV Data In Write Chip Enable Clock Enable Symbol S bl tKHKH tKHKL tKLKH tKHQV tGLQV tKHQX1 tKHQX tGLQX tGHQZ tKHQZ tADKH tLVKH tDVKH tWVKH tEVKH tCVKH tKHAX tKHLX tKHDX tKHWX tKHEX tKHCX Min 8.5 3.4 3.4 — — 4 2 0 — 1.5 1.5 1.5 1.5 1.5 1.5 1.5 0.5 Max — — — 7 3.5 — — — 3.5 3.5 — Hold Times: — — — ns NOTES: 1. Write is defined as any SBx and SW low. Chip enable is defined as SE1 low, SE2 high, and SE3 low whenever ADV is low. 2. All read and write cycle timings are referenced from CK or G. 3. In order to reduce test correlation issues and to reduce the effects of application specific input edge rate variations on correlation between data sheet parameters and actual system performance, FSRAM AC parametric specifications are always specified at VDDQ/2. In some design exercises, it is desirable to evaluate timing using other reference levels. Since the maximum test input edge rate is known and is given in the AC Test Conditions section of the data sheet as 1 V/ns, one can easily interpolate timing values to other reference levels. 4. This parameter is sampled and not 100% tested. 5. Measured at ±200 mV from steady state. MOTOROLA FAST SRAM For More Information On This Product, Go to: www.freescale.com MCM64Z836•MCM64Z918 17 Freescale Semiconductor, Inc. PIPELINED READ/WRITE CYCLE TIMING (See Notes 1 and 2) MCM64Z836–7 MCM64Z918–7 225 MHz Parameter P Cycle Time Clock High Pulse Width Clock Low Pulse Width Clock Access Time Output Enable to Output Valid Clock High to Output Active Output Hold Time Output Enable to Output Active Output Disable to Q High–Z Symbol S bl tKHKH tKHKL tKLKH tKHQV tGLQV tKHQX1 tKHQX tGLQX tGHQZ tKHQZ tADKH tLVKH tDVKH tWVKH tEVKH tCVKH tKHAX tKHLX tKHDX tKHWX tKHEX tKHCX Min 4.4 1.7 1.7 — — 0.8 0.7 0 — 0.8 1.3 1.3 1.2 1.3 1.3 1.3 0.5 Max — — — 2.6 2.6 — — — 2.3 2.4 — MCM64Z836–8 MCM64Z918–8 200 MHz Min 5 2 2 — — 0.8 0.7 0 — 1 1.3 1.3 1.2 1.3 1.3 1.3 0.5 Max — — — 3 3 — — — 3 2.5 — MCM64Z836–8.5 MCM64Z918–8.5 166 MHz Min 6 2.4 2.4 — — 0.8 0.7 0 — 1 1.3 1.3 1.2 1.3 1.3 1.3 0.5 Max — — — 3.5 3.5 — — — 3.5 3 — Unit Ui ns ns ns ns ns ns ns ns ns ns ns 4, 5 4 4, 5 4, 5 4, 5 3 3 Notes N Freescale Semiconductor, Inc... Clock High to Q High–Z Setup Times: Address ADV Data In Write Chip Enable Clock Enable Address ADV Data In Write Chip Enable Clock Enable Hold Times: — — — ns NOTES: 1. Write is defined as any SBx and SW low. Chip Enable is defined as SE1 low, SE2 high, and SB3 low whenever ADV is low. 2. All read and write cycle timings are referenced from CK or G. 3. In order to reduce test correlation issues and to reduce the effects of application specific input edge rate variations on correlation between data sheet parameters and actual system performance, FSRAM AC parametric specifications are always specified at VDDQ/2. In some design exercises, it is desirable to evaluate timing using other reference levels. Since the maximum test input edge rate is known and is given in the AC test conditions section of the data sheet as 2.5 V/ns, one can easily interpolate timing values to other reference levels. 4. This parameter is sampled and not 100% tested. 5. Measured at ±200 mV from steady state. OUTPUT Z0 = 50 Ω RL = 50 Ω 1.25 V Figure 9. AC Test Loads MCM64Z836•MCM64Z918 18 For More Information On This Product, Go to: www.freescale.com MOTOROLA FAST SRAM Freescale Semiconductor, Inc. tKHKH tKHKL CK tAVKH tKHAX SA0 – SAx tWVKH SW tWVKH SBx tKLKH tKHWX tKHWX Freescale Semiconductor, Inc... tEVKH tKHEX E tLVKH ADV tCVKH CKE tKHLX tKHCX G tGLQX tGLQV DQ tDVKH tKHDX DQ tKHQV tKHQX1 DQ Q D tKHQX tKHQZ Q Q tGHQZ Figure 10. AC Timing Parameter Definitions (Flow–Through) MOTOROLA FAST SRAM For More Information On This Product, Go to: www.freescale.com MCM64Z836•MCM64Z918 19 Freescale Semiconductor, Inc. tKHKH tKHKL CK tAVKH tKHAX SA0 – SAx tWVKH tKHWX SW tWVKH tKHWX SBx tKLKH Freescale Semiconductor, Inc... tEVKH tKHEX E tLVKH tKHLX ADV tCVKH tKHCX CKE G tGLQX tGLQV DQ tDVKH tKHDX DQ tKHQV tKHQX1 DQ Q D tKHQX tKHQZ Q Q tGHQZ NOTE: E is true if SE1 = SE3 = low and SE2 = high. tGLQX, tGLQV, and tGHQZ only apply if G is toggled. If G is tied low tKHQX, tKHQV, and tKHQZ apply. Figure 11. AC Timing Parameter Definitions (Pipelined) MCM64Z836•MCM64Z918 20 For More Information On This Product, Go to: www.freescale.com MOTOROLA FAST SRAM Freescale Semiconductor, Inc... MOTOROLA FAST SRAM READ/WRITE CYCLES WITH HOLD AND DESELECT CYCLES B C D E F G H I J W D H R W R H W R D W R D Q(A0) D(B0) Q(C0) D(D0) Q(E0) D(F0) Q(G0) D(H0) Q(I0) CK ADDRESS A COMMAND CODE R DQ (FLOW–THROUGH) Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com Q(A0) D(B0) Q(C0) D(D0) Q(E0) D(F0) DQ (PIPELINED) Q(G0) D(H0) Q(I0) NOTE: Command code definitions are shown in Truth Table. MCM64Z836•MCM64Z918 21 Freescale Semiconductor, Inc... MCM64Z836•MCM64Z918 22 READ CYCLES (SINGLE, BURST, AND BURST WRAP–AROUND) CK A B C R R R B B B B B B B Q(A0) Q(B3) Q(B0) Q(B1) Q(B2) Q(C0) Q(C1) Q(C2) Q(C3) Q(C0) Q(A0) Q(B0) Q(B1) Q(B2) Q(B3) Q(C0) Q(C1) Q(C2) Q(C3) Q(C0) ADDRESS COMMAND CODE DQ (FLOW–THROUGH) Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com DQ (PIPELINED) NOTE: Command code definitions are shown in Truth Table. MOTOROLA FAST SRAM Freescale Semiconductor, Inc... MOTOROLA FAST SRAM WRITE CYCLES (SINGLE, BURST, AND BURST WRAP–AROUND) CK A B C W W W B B B B B B B D(A0) D(B0) D(B3) D(B1) D(B2) D(C0) D(C1) D(C2) D(C3) D(C0) ADDRESS COMMAND CODE DQ (FLOW–THROUGH) Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com D(A0) D(B0) D(B1) D(B2) D(B3) D(C0) D(C1) D(C2) DQ (PIPELINED) D(C3) D(C0) NOTE: Command code definitions are shown in Truth Table. MCM64Z836•MCM64Z918 23 Freescale Semiconductor, Inc... MCM64Z836•MCM64Z918 24 READ, WRITE, READ COHERENCY WITH HOLD, AND DESELECT CYCLES A B B C C D D E R R W R W B B D W H R R Q(A0) D(C1) D(B0) Q(B0) D(C0) Q(C0) Q(C1) D(D0) Q(D0) Q(E0) Q(A0) D(B0) Q(B0) D(C0) D(C1) Q(C0) Q(C1) D(D0) Q(D0) Q(E0) CK ADDRESS COMMAND CODE DQ (FLOW–THROUGH) Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com DQ (PIPELINED) NOTE: Command code definitions are shown in Truth Table. MOTOROLA FAST SRAM Freescale Semiconductor, Inc. SERIAL BOUNDARY SCAN TEST ACCESS PORT OPERATION OVERVIEW The serial boundary scan test access port (TAP) on this RAM is designed to operate in a manner consistent with IEEE Standard 1149.1–1990 (commonly referred to as JTAG), but does not implement all of the functions required for IEEE 1149.1 compliance. Certain functions have been modified or eliminated because their implementation places extra delays in the RAMs critical speed path. Nevertheless, the RAM supports the standard TAP controller architecture (the TAP controller is the state machine that controls the TAPs operation) and can be expected to function in a manner that does not conflict with the operation of devices with IEEE Standard 1149.1 compliant TAPs. The TAP operates using a 2.5 V tolerant logic level signaling. DISABLING THE TEST ACCESS PORT It is possible to use this device without utilizing the TAP. To disable the TAP controller without interfering with normal operation of the device, TRST should be tied low and TCK, TDI, and TMS should be pulled through a resistor to 2.5 V. TDO should be left unconnected. TAP DC OPERATING CHARACTERISTICS (TA = 0 to 70°C, Unless Otherwise Noted) Freescale Semiconductor, Inc... Parameter Input Logic Low Input Logic High Input Leakage Current Output Logic Low Output Logic High NOTES: 1. 0 V ≤ Vin ≤ VDDQ for all logic input pins. 2. For VOL = 0.4 V, 14 mA ≤ IOL ≤ 28 mA. Symbol VIL1 VIH1 Ilkg VOL1 VOH1 Min –0.5 1.7 — — 1.7 Max 0.7 3 ±10 0.7 — Unit V V µA V V Notes 1 2 MOTOROLA FAST SRAM For More Information On This Product, Go to: www.freescale.com MCM64Z836•MCM64Z918 25 Freescale Semiconductor, Inc. TAP AC OPERATING CONDITIONS AND CHARACTERISTICS (TA = 0 to 70°C, Unless Otherwise Noted) AC TEST CONDITIONS Parameter Input Timing Reference Level Input Pulse Levels Input Rise/Fall Time (20% to 80%) Output Timing Reference Level Output Load (See Figure 6 Unless Otherwise Noted) Value 1.25 0 to 2.5 1 1.25 — Unit V V V/ns V — TAP CONTROLLER TIMING Parameter TCK Cycle Time Symbol tTHTH tTH tTL tTLQV tTSRT Capture TDI TMS Capture TDI TMS tCS tDVTH tMVTH tCH tTHDX tTHMX Min 60 25 25 1 40 5 5 5 13 14 14 Max — — — 10 — — Unit ns ns ns ns ns ns 1 Notes Freescale Semiconductor, Inc... TCK Clock High Time TCK Clock Low Time TDO Access Time TRST Pulse Width Setup Times Hold Times — ns 1 NOTE: 1. tCS and tCH define the minimum pauses in RAM I/O transitions to assure accurate pad data capture. TAP CONTROLLER TIMING DIAGRAM tTHTH tTLTH TEST CLOCK (TCK) tTHTL tMVTH TEST MODE SELECT (TMS) tTHDX tDVTH TEST DATA IN (TDI) tTLQV TEST DATA OUT (TDO) tTHMX MCM64Z836•MCM64Z918 26 For More Information On This Product, Go to: www.freescale.com MOTOROLA FAST SRAM Freescale Semiconductor, Inc. MCM64Z836 BOUNDARY SCAN ORDER Bit No. 1 2 3 4 5 6 7 8 9 10 11 Signal Name SA SA SA SA SA SA SA DQa DQa DQa DQa DQa DQa DQa DQa DQa VSS DQb DQb DQb DQb DQb DQb DQb DQb DQb SA SA SA ADV G CKE SW CK SE3 Bump ID TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD 52 TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 VDD DQd DQd DQd DQd DQd DQd DQd DQd DQd LBO SA SA SA SA SA1 SA0 TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD DQc TBD Bit No. 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 Signal Name SBa SEb SBc SBd SE2 SE1 SA SA DQc DQc DQc DQc DQc DQc DQc DQc Bump ID TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD Freescale Semiconductor, Inc... 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 MOTOROLA FAST SRAM For More Information On This Product, Go to: www.freescale.com MCM64Z836•MCM64Z918 27 Freescale Semiconductor, Inc. MCM64Z918 BOUNDARY SCAN ORDER Bit No. 1 2 3 4 5 6 7 8 9 10 11 Signal Name SA SA SA SA SA SA SA DQa DQa DQa DQa VSS DQa DQa DQa DQa DQa SA SA SA SA ADV G CKE SW Bump ID TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD Bit No. 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Signal Name CK SE3 SBa SBb SB2 SE1 SA SA DQb DQb DQb DQb VDD DQb DQb DQb DQb DQb LBO SA SA SA SA SA1 SA0 Bump ID TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD Freescale Semiconductor, Inc... 12 13 14 15 16 17 18 19 20 21 22 23 24 25 MCM64Z836•MCM64Z918 28 For More Information On This Product, Go to: www.freescale.com MOTOROLA FAST SRAM Freescale Semiconductor, Inc. TEST ACCESS PORT PINS TCK — TEST CLOCK (INPUT) Clocks all TAP events. All inputs are captured on the rising edge of TCK and all outputs propagate from the falling edge of TCK. TMS — TEST MODE SELECT (INPUT) The TMS input is sampled on the rising edge of TCK. This is the command input for the TAP controller state machine. An undriven TMS input will not produce the same result as a logic 1 input level (not IEEE 1149.1 compliant). TDI — TEST DATA IN (INPUT) The TDI input is sampled on the rising edge of TCK. This is the input side of the serial registers placed between TDI and TDO. The register placed between TDI and TDO is determined by the state of the TAP controller state machine and the instruction that is currently loaded in the TAP instruction register (refer to Figure 13). An undriven TDI pin will not produce the same result as a logic 1 input level (not IEEE 1149.1 compliant). TDO — TEST DATA OUT (OUTPUT) Output that is active depending on the state of the TAP state machine (refer to Figure 13). Output changes in response to the falling edge of TCK. This is the output side of the serial registers placed between TDI and TDO. TRST — TAP RESET The TRST is an asynchronous input that resets the TAP controller and preloads the instruction register with the IDCODE command. This type of reset does not affect the operation of the system logic. The reset affects test logic only. BOUNDARY SCAN REGISTER The boundary scan register is identical in length to the number of active input and I/O connections on the RAM (not counting the TAP pins). This also includes a number of place holder locations (always set to a logic 0) reserved for density upgrade address pins. There are a total of 67 bits in the case of the x36 device and 48 bits in the case of the x18 device. The boundary scan register, under the control of the TAP controller, is loaded with the contents of the RAMs I/O ring when the controller is in capture–DR state and then is placed between the TDI and TDO pins when the controller is moved to shift–DR state. The Bump/Bit Scan Order table describes which device bump connects to each boundary scan register location. The first column defines the bit’s position in the boundary scan register. The shift register bit nearest TDO (i.e., first to be shifted out) is defined as bit 1. The second column is the name of the input or I/O at the bump and the third column is the bump number. IDENTIFICATION (ID) REGISTER The ID register is a 32–bit register that is loaded with a device and vendor specific 32–bit code when the controller is put in capture–DR state with the IDCODE command loaded in the instruction register. The code is loaded from a 32–bit on–chip ROM. It describes various attributes of the RAM as indicated below. The register is then placed between the TDI and TDO pins when the controller is moved into shift–DR state. Bit 0 in the register is the LSB and the first to reach TDO when shifting begins. ID Register Presence Indicator Bit No. Value 0 1 Freescale Semiconductor, Inc... TEST ACCESS PORT REGISTERS OVERVIEW The various TAP registers are selected (one at a time) via the sequences of 1s and 0s input to the TMS pin as the TCK is strobed. Each of the TAPs registers are serial shift registers that capture serial input data on the rising edge of TCK and push serial data out on the subsequent falling edge of TCK. When a register is selected, it is “placed” between the TDI and TDO pins. INSTRUCTION REGISTER The instruction register holds the instructions that are executed by the TAP controller when it is moved into the run test/idle or the various data register states. The instructions are 3 bits long. The register can be loaded when it is placed between the TDI and TDO pins. The parallel outputs of the instruction register are automatically preloaded with the IDCODE instruction when TRST is asserted or whenever the controller is placed in the test–logic–reset state. The two least significant bits of the serial instruction register are loaded with a binary “or” pattern in the capture–IR state. BYPASS REGISTER The bypass register is a single bit register that can be placed between TDI and TDO. It allows serial test data to be passed through the RAMs TAP to another device in the scan chain with as little delay as possible. Motorola JEDEC ID Code (Compressed Format, per IEEE Standard 1149.1–1990 Bit No. Value 11 0 10 0 9 0 8 0 7 0 6 0 5 0 4 1 3 1 2 1 1 0 Reserved For Future Use Bit No. Value 17 x 16 x 15 x 14 x 13 x 12 x Device Width Bit No. 256K x 36 512K x 18 22 0 0 21 0 0 20 1 0 19 0 1 18 0 1 Device Depth Bit No. 256K x 36 512K x 18 27 0 0 26 0 0 25 1 1 24 1 1 23 0 1 Revision Number Bit No. Value 31 0 30 0 29 0 28 0 Figure 12. ID Register Bit Meanings MOTOROLA FAST SRAM For More Information On This Product, Go to: www.freescale.com MCM64Z836•MCM64Z918 29 Freescale Semiconductor, Inc. TAP CONTROLLER INSTRUCTION SET OVERVIEW There are two classes of instructions defined in the IEEE Standard 1149.1–1990; the standard (public) instructions and device specific (private) instructions. Some public instructions, are mandatory for IEEE 1149.1 compliance. Optional public instructions must be implemented in prescribed ways. Although the TAP controller in this device follows the IEEE 1149.1 conventions, it is not IEEE 1149.1 compliant because some of the mandatory instructions are not fully implemented. The TAP on this device may be used to monitor all input and I/O pads, but can not be used to load address, data, or control signals into the RAM or to preload the I/O buffers. In other words, the device will not perform IEEE 1149.1 EXTEST, INTEST, or the preload portion of the SAMPLE/PRELOAD command. When the TAP controller is placed in capture–IR state, the two least significant bits of the instruction register are loaded with 01. When the controller is moved to the shift–IR state the instruction register is placed between TDI and TDO. In this state, the desired instruction is serially loaded through the TDI input (while the previous contents are shifted out at TDO). For all instructions, the TAP executes newly loaded instructions only when the controller is moved to update–IR state. The TAP instruction sets for this device are listed in the following tables. possible for the TAP to attempt to capture the I/O ring contents while the input buffers are in transition (i.e., in a metastable state). Although allowing the TAP to sample metastable inputs will not harm the device, repeatable results can not be expected. RAM input signals must be stabilized for long enough to meet the TAPs input data capture setup plus hold time (tCS plus tCH). The RAMs clock inputs need not be paused for any other TAP operation except capturing the I/O ring contents into the boundary scan register. Moving the controller to shift–DR state then places the boundary scan register between the TDI and TDO pins. Because the PRELOAD portion of the command is not implemented in this device, moving the controller to the update–DR state with the SAMPLE/PRELOAD instruction loaded in the instruction register has the same effect as the pause–DR command. This functionality is not IEEE 1149.1 compliant. EXTEST EXTEST is an IEEE 1149.1 mandatory public instruction. It is to be executed whenever the instruction register, whatever length it may be in the device, is loaded with all logic 0s. EXTEST is not implemented in this device. IDCODE The IDCODE instruction causes the ID ROM to be loaded into the ID register when the controller is in capture–DR mode and places the ID register between the TDI and TDO pins in shift–DR mode. The IDCODE instruction is the default instruction loaded in at TRST assertion and any time the controller is placed in the test–logic–reset state. Freescale Semiconductor, Inc... STANDARD (PUBLIC) INSTRUCTIONS BYPASS The BYPASS instruction is loaded in the instruction register when the bypass register is placed between TDI and TDO. This occurs when the TAP controller is moved to the shift–DR state. This allows the board level scan path to be shortened to facilitate testing of other devices in the scan path. SAMPLE/PRELOAD SAMPLE/PRELOAD is an IEEE 1149.1 mandatory public instruction. When the SAMPLE/PRELOAD instruction is loaded in the instruction register, moving the TAP controller out of the capture–DR state loads the data in the RAMs input and I/O buffers into the boundary scan register. Because the RAM clock(s) are independent from the TAP clock (TCK), it is THE DEVICE SPECIFIC (PUBLIC) INSTRUCTION SAMPLE–Z If the HIGH–Z instruction is loaded in the instruction register, all DQ pins are forced to an inactive drive state (High–Z) and the bypass register is connected between TDI and TDO when the TAP controller is moved to the shift–DR state. THE DEVICE SPECIFIC (PRIVATE) INSTRUCTION NO OP Do not use these instructions; they are reserved for future use. MCM64Z836•MCM64Z918 30 For More Information On This Product, Go to: www.freescale.com MOTOROLA FAST SRAM Freescale Semiconductor, Inc. STANDARD AND DEVICE SPECIFIC (PUBLIC) INSTRUCTION CODES Instruction IDCODE HIGH–Z BYPASS SAMPLE/PRELOAD Code* 001** 010 011 100 Description Preloads ID register and places it between TDI and TDO. Does not affect RAM operation. Captures I/O ring contents. Places the bypass register between TDI and TDO. Forces all DQ pins to High–Z. NOT IEEE 1149.1 COMPLIANT. Places bypass register between TDI and TDO. Does not affect RAM operation. NOT IEEE 1149.1 COMPLIANT. Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Does not affect RAM operation. Does not implement IEEE 1149.1 Preload function. NOT IEEE 1149.1 COMPLIANT. * Instruction codes expressed in binary, MSB on left, LSB on right. ** Default instruction automatically loaded when TRST asserted or in test–logic–reset state. STANDARD (PRIVATE) INSTRUCTION CODES Instruction Code* 000 101 110 111 Description Do not use these instructions; they are reserved for future use. Do not use these instructions; they are reserved for future use. Do not use these instructions; they are reserved for future use. Do not use these instructions; they are reserved for future use. NO OP NO OP NO OP NO OP Freescale Semiconductor, Inc... * Instruction codes expressed in binary, MSB on left, LSB on right. 1 TEST–LOGIC RESET 0 RUN–TEST/ IDLE 1 SELECT DR–SCAN 0 1 CAPTURE–DR 0 SHIFT–DR 0 1 1 EXIT1–DR 0 PAUSE–DR 1 0 EXIT2–DR 1 UPDATE–DR 1 0 1 0 0 EXIT1–IR 0 PAUSE–IR 1 EXIT2–IR 1 UPDATE–IR 0 0 1 1 1 1 SELECT IR–SCAN 0 CAPTURE–IR 0 SHIFT–IR 0 1 0 NOTE: The value adjacent to each state transition represents the signal present at TMS at the rising edge of TCK. Figure 13. TAP Controller State Diagram MOTOROLA FAST SRAM For More Information On This Product, Go to: www.freescale.com MCM64Z836•MCM64Z918 31 Freescale Semiconductor, Inc. ORDERING INFORMATION (Order by Full Part Number) MCM Motorola Memory Prefix Part Number 64Z836 64Z918 XX X X Blank = Trays, R = Tape and Reel Speed (7 = 7 ns Flow–Through or 225 MHz Pipelined, 8 = 8 ns Flow–Through or 200 MHz Pipelined, 8.5 = 8.5 ns Flow–Through or 166 MHz Pipelined) Package (TQ = TQFP, ZP = PBGA) Full Part Numbers — MCM64Z836TQ7 MCM64Z836TQ7R MCM64Z918TQ7 MCM64Z918TQ7R MCM64Z836ZP7 MCM64Z836ZP7R MCM64Z918ZP7 MCM64Z918ZP7R MCM64Z836TQ8 MCM64Z836TQ8R MCM64Z918TQ8 MCM64Z918TQ8R MCM64Z836ZP8 MCM64Z836ZP8R MCM64Z918ZP8 MCM64Z918ZP8R MCM64Z836TQ8.5 MCM64Z836TQ8.5R MCM64Z918TQ8.5 MCM64Z918TQ8.5R MCM64Z836ZP8.5 MCM64Z836ZP8.5R MCM64Z918ZP8.5 MCM64Z918ZP8.5R Freescale Semiconductor, Inc... MCM64Z836•MCM64Z918 32 For More Information On This Product, Go to: www.freescale.com MOTOROLA FAST SRAM Freescale Semiconductor, Inc. PACKAGE DIMENSIONS TQ PACKAGE TQFP CASE 983A–01 4X e 0.20 (0.008) H A–B D 2X 30 TIPS e/2 0.20 (0.008) C A–B D –D– 80 81 51 50 B E/2 B VIEW Y E1 E E1/2 BASE METAL PLATING –X– X=A, B, OR D –A– –B– b1 c Freescale Semiconductor, Inc... 100 1 30 31 D1/2 D1 D 2X 20 TIPS D/2 0.13 (0.005) 0.20 (0.008) C A–B D A –H– –C– SEATING PLANE q 2 0.10 (0.004) C q 3 VIEW AB 0.05 (0.002) S S q 1 0.25 (0.010) GAGE PLANE NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DATUM PLANE –H– IS LOCATED AT BOTTOM OF LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING LINE. 4. DATUMS –A–, –B– AND –D– TO BE DETERMINED AT DATUM PLANE –H–. 5. DIMENSIONS D AND E TO BE DETERMINED AT SEATING PLANE –C–. 6. DIMENSIONS D1 AND E1 DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.25 (0.010) PER SIDE. DIMENSIONS D1 AND B1 DO INCLUDE MOLD MISMATCH AND ARE DETERMINED AT DATUM PLANE –H–. 7. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION. DAMBAR PROTRUSION SHALL NOT CAUSE THE b DIMENSION TO EXCEED 0.45 (0.018). DIM A A1 A2 b b1 c c1 D D1 E E1 e L L1 L2 S R1 R2 q A2 R2 A1 R1 L2 L L1 VIEW AB q 1 2 q3 q q MOTOROLA FAST SRAM For More Information On This Product, Go to: www.freescale.com ÇÇÇÇ ÉÉÉÉ ÇÇÇÇ ÉÉÉÉ ÇÇÇÇ b M MILLIMETERS MIN MAX ––– 1.60 0.05 0.15 1.35 1.45 0.22 0.38 0.22 0.33 0.09 0.20 0.09 0.16 22.00 BSC 20.00 BSC 16.00 BSC 14.00 BSC 0.65 BSC 0.45 0.75 1.00 REF 0.50 REF 0.20 ––– 0.08 ––– 0.08 0.20 0_ 7_ 0_ ––– 11 _ 13 _ 11 _ 13 _ c1 C A–B S D S SECTION B–B INCHES MIN MAX ––– 0.063 0.002 0.006 0.053 0.057 0.009 0.015 0.009 0.013 0.004 0.008 0.004 0.006 0.866 BSC 0.787 BSC 0.630 BSC 0.551 BSC 0.026 BSC 0.018 0.030 0.039 REF 0.020 REF 0.008 ––– 0.003 ––– 0.003 0.008 0_ 7_ 0_ ––– 11 _ 13 _ 11 _ 13 _ MCM64Z836•MCM64Z918 33 Freescale Semiconductor, Inc. ZP PACKAGE 7 x 17 BUMP PBGA CASE 999–02 4X 0.20 119X C E B 7 6 54 3 2 1 A B C D E F G H J K L M N P R T U b 0.3 0.15 M M ABC A NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. ALL DIMENSIONS IN MILLIMETERS. 3. DIMENSION b IS THE MAXIMUM SOLDER BALL DIAMETER MEASURED PARALLEL TO DATUM A. 4. DATUM A, THE SEATING PLANE, IS DEFINED BY THE SPHERICAL CROWNS OF THE SOLDER BALLS. DIM A A1 A2 A3 D D1 D2 E E1 E2 b e MILLIMETERS MIN MAX ––– 2.40 0.50 0.70 1.30 1.70 0.80 1.00 22.00 BSC 20.32 BSC 19.40 19.60 14.00 BSC 7.62 BSC 11.90 12.10 0.60 0.90 1.27 BSC D2 D D1 16X e E2 6X e E1 BOTTOM VIEW Freescale Semiconductor, Inc... TOP VIEW 0.25 A A3 0.35 A 0.20 A A A2 SIDE VIEW SEATING PLANE A1 A Motorola reserves the right to make changes without further notice to any products herein. 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