MMDF2C02HD

MOTOROLA Designer's SEMICONDUCTOR TECHNICAL DATA Order this document by MMDF2C02HD/D ™ Data Sheet Medium Power Surface Mount Products MiniMOS™ devices are an advanced series of power MOSFETs which utilize Motorola’s High Cell Density HDTMOS process. These miniature surface mount MOSFETs feature ultra low RDS(on) and true logic level performance. They are capable of withstanding high energy in the avalanche and commutation modes and the drain–to–source diode has a very low reverse recovery time. MiniMOS devices are designed for use in low voltage, high speed switching applications where power efficiency is important. Typical applications are dc–dc converters, and power management in portable and battery powered products such as computers, printers, cellular and cordless phones. They can also be used for low voltage motor controls in mass storage products such as disk drives and tape drives. The avalanche energy is specified to eliminate the guesswork in designs where inductive loads are switched and offer additional safety margin against unexpected voltage transients. • Ultra Low RDS(on) Provides Higher Efficiency and Extends Battery Life • Logic Level Gate Drive — Can Be Driven by Logic ICs • Miniature SO–8 Surface Mount Package — Saves Board Space • Diode Is Characterized for Use In Bridge Circuits • Diode Exhibits High Speed, With Soft Recovery • Avalanche Energy Specified • Mounting Information for SO–8 Package Provided MAXIMUM RATINGS (TJ = 25°C unless otherwise noted)(1) Rating Drain–to–Source Voltage Gate–to–Source Voltage Drain–to–Gate Voltage (RGS = 1.0 mΩ) Drain Current — Continuous — Pulsed N–Channel P–Channel N–Channel P–Channel Complementary TMOS Field Effect Transistors MMDF2C02HD Motorola Preferred Device ™ D N–Channel COMPLEMENTARY DUAL TMOS POWER FET 2.0 AMPERES 20 VOLTS RDS(on) = 0.090 OHM (N–CHANNEL) RDS(on) = 0.160 OHM (P–CHANNEL) G CASE 751–05, Style 14 SO–8 S D P–Channel N–Source N–Gate P–Source G S Symbol VDSS VGS VDGR ID IDM TJ, Tstg PD EAS N–Channel P–Channel RθJA TL 405 324 62.5 260 °C/W °C P–Gate 1 2 3 4 8 7 6 5 N–Drain N–Drain P–Drain P–Drain Top View Value 20 ± 20 20 3.8 3.3 19 20 – 55 to 150 2.0 Unit Vdc Vdc Vdc A Operating and Storage Temperature Range Total Power Dissipation @ TA= 25°C (2) Single Pulse Drain–to–Source Avalanche Energy — Starting TJ = 25°C (VDD = 20 V, VGS = 5.0 V, Peak IL = 9.0 A, L = 10 mH, RG = 25 Ω) (VDD = 20 V, VGS = 5.0 V, Peak IL = 6.0 A, L = 18 mH, RG = 25 Ω) Thermal Resistance — Junction to Ambient (2) °C Watts mJ Maximum Lead Temperature for Soldering, 0.0625″ from case. Time in Solder Bath is 10 seconds. DEVICE MARKING D2C02 (1) Negative signs for P–Channel device omitted for clarity. (2) Mounted on 2” square FR4 board (1” sq. 2 oz. Cu 0.06” thick single sided) with one die operating, 10 sec. max. ORDERING INFORMATION Device MMDF2C02HDR2 Reel Size 13″ Tape Width 12 mm embossed tape Quantity 2500 units Designer’s Data for “Worst Case” Conditions — The Designer’s Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit curves — representing boundaries on device characteristics — are given to facilitate “worst case” design. HDTMOS and MiniMOS are trademarks of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc. Thermal Clad is a trademark of the Bergquist Company. Preferred devices are Motorola recommended choices for future use and best overall value. REV 5 ©Motorola TMOS Power MOSFET Transistor Device Data Motorola, Inc. 1996 1 MMDF2C02HD ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise noted)(1) Characteristic OFF CHARACTERISTICS Drain–Source Breakdown Voltage (VGS = 0 Vdc, ID = 250 µAdc) Zero Gate Voltage Drain Current (VDS = 20 Vdc, VGS = 0 Vdc) Gate–Body Leakage Current (VGS = ± 20 Vdc, VDS = 0) ON CHARACTERISTICS(2) Gate Threshold Voltage (VDS = VGS, ID = 250 µAdc) Drain–to–Source On–Resistance (VGS = 4.5 Vdc, ID = 1.5 Adc) (VGS = 4.5 Vdc, ID = 1.0 Adc) Drain–to–Source On–Resistance (VGS = 10 Vdc, ID = 3.0 Adc) (VGS = 10 Vdc, ID = 2.0 Adc) Forward Transconductance (VDS = 3.0 Vdc, ID = 1.5 Adc) (VDS = 3.0 Vdc, ID = 1.0 Adc) DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance Transfer Capacitance SWITCHING CHARACTERISTICS(3) Turn–On Delay Time Rise Time Turn–Off Delay Time Fall Time Turn–On Delay Time Rise Time Turn–Off Delay Time Fall Time Total Gate Charge Gate–Source Charge Gate–Drain Charge (VDS = 16 Vdc, ID = 3.0 Adc, VGS = 10 Vdc) (VDS = 16 Vdc, ID = 2.0 Adc, VGS = 10 Vdc) (VDD = 10 Vdc, ID = 3.0 Adc, VGS = 10 Vdc, RG = 6.0 Ω) (VDD = 10 Vdc, ID = 2.0 Adc, VGS = 10 Vdc, RG = 6.0 Ω) (VDD = 10 Vdc, ID = 3.0 Adc, VGS = 4.5 Vdc, RG = 6.0 Ω) (VDD = 10 Vdc, ID = 2.0 Adc, VGS = 4.5 Vdc, RG = 6.0 Ω) td(on) tr td(off) tf td(on) tr td(off) tf QT Q1 Q2 Q3 (1) Negative signs for P–Channel device omitted for clarity. (2) Pulse Test: Pulse Width ≤ 300 µs, Duty Cycle ≤ 2%. (3) Switching characteristics are independent of operating junction temperature. (N) (P) (N) (P) (N) (P) (N) (P) (N) (P) (N) (P) (N) (P) (N) (P) (N) (P) (N) (P) (N) (P) (N) (P) — — — — — — — — — — — — — — — — — — — — — — — — 11 19 58 66 17 25 20 37 7.0 11 32 21 27 45 21 36 12.5 15 1.3 1.2 2.8 5.0 2.4 4.0 22 38 116 132 35 50 40 74 21 22 64 42 54 90 42 72 18 20 — — — — — — (continued) nC ns (VDS = 16 Vdc, VGS = 0 Vdc, f = 1.0 MHz) Ciss Coss Crss (N) (P) (N) (P) (N) (P) — — — — — — 455 420 184 290 45 116 630 588 250 406 90 232 pF VGS(th) — RDS(on) (N) (P) RDS(on) (N) (P) gFS (N) (P) 2.0 2.0 3.88 3.0 — — — — 0.058 0.118 0.090 0.160 mhos — — 0.074 0.152 0.100 0.180 Ohm 1.0 1.5 2.0 Ohm Vdc V(BR)DSS — IDSS IGSS (N) (P) — 20 — — — — — — — — 1.0 1.0 100 µAdc nAdc Vdc Symbol Polarity Min Typ Max Unit 2 Motorola TMOS Power MOSFET Transistor Device Data MMDF2C02HD ELECTRICAL CHARACTERISTICS — continued (TA = 25°C unless otherwise noted)(1) Characteristic SOURCE–DRAIN DIODE CHARACTERISTICS (TC = 25°C) Forward Voltage(2) (IS = 3.0 Adc, VGS = 0 Vdc) (IS = 2.0 Adc, VGS = 0 Vdc) Reverse Recovery Time (IS = 3.0 Adc, VAS = 0 Vdc, dIS/dt = 100 A/µs) (IS = 2.0 Adc, VAS = 0 Vdc, dIS/dt = 100 A/µs) Reverse Recovery Stored Charge (1) Negative signs for P–Channel device omitted for clarity. (2) Pulse Test: Pulse Width ≤ 300 µs, Duty Cycle ≤ 2%. Symbol Polarity Min Typ Max Unit VSD trr ta tb QRR (N) (P) (N) (P) (N) (P) (N) (P) (N) (P) — — — — — — — — — — 0.79 1.5 23 38 18 17 5.0 21 0.025 0.034 1.3 2.1 — — — — — — — — Vdc ns µC TYPICAL ELECTRICAL CHARACTERISTICS N–Channel VGS = 10 V 4.5 V 5 3.9 V 4 3.1 V 3 2.9 V 2 2.7 V 1 2.5 V 0 0 0.2 1.6 VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS) 0.4 0.6 0.8 1 1.2 1.4 1.8 2 0 0 0.2 0.4 0.6 0.8 1 1.2 6 3.5 V 3.7 V 3.3 V TJ = 25°C I D , DRAIN CURRENT (AMPS) 4 VGS = 10 V 4.5 V P–Channel 3.9 V 3.7 V 3.5 V TJ = 25°C I D , DRAIN CURRENT (AMPS) 3 3.3 V 2 3.1 V 1 2.9 V 2.7 V 2.5 V 1.4 1.6 1.8 2 VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS) Figure 1. On–Region Characteristics Figure 1. On–Region Characteristics 6 VDS ≥ 10 V I D , DRAIN CURRENT (AMPS) I D , DRAIN CURRENT (AMPS) 4 VDS ≥ 10 V 3 4 TJ = 100°C 25°C 2 – 55°C 2 1 100°C 0 1.0 TJ = – 55°C 25°C 0 1 1.4 1.8 2.2 2.6 3 VGS, GATE–TO–SOURCE VOLTAGE (VOLTS) 3.4 1.5 2.0 2.5 3.0 VGS, GATE–TO–SOURCE VOLTAGE (VOLTS) 3.5 Figure 2. Transfer Characteristics Figure 2. Transfer Characteristics Motorola TMOS Power MOSFET Transistor Device Data 3 MMDF2C02HD TYPICAL ELECTRICAL CHARACTERISTICS N–Channel RDS(on) , DRAIN–TO–SOURCE RESISTANCE (OHMS) RDS(on) , DRAIN–TO–SOURCE RESISTANCE (OHMS) 0.6 0.6 P–Channel ID = 1.5 A TJ = 25°C ID = 1 A TJ = 25°C 0.4 0.4 0.2 0.2 0 0 1 5 6 7 8 3 4 VGS, GATE–TO–SOURCE VOLTAGE (VOLTS) 2 9 10 0 0 2 4 6 8 10 VGS, GATE–TO–SOURCE VOLTAGE (VOLTS) Figure 3. On–Resistance versus Gate–To–Source Voltage RDS(on) , DRAIN–TO–SOURCE RESISTANCE (OHMS) RDS(on) , DRAIN–TO–SOURCE RESISTANCE (OHMS) 0.08 0.20 TJ = 25°C 0.16 Figure 3. On–Resistance versus Gate–To–Source Voltage TJ = 25°C VGS = 4.5 V VGS = 4.5 V 0.07 0.12 10 V 0.06 10 V 0.08 0.05 0.04 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 ID, DRAIN CURRENT (AMPS) 0 1 2 3 4 ID, DRAIN CURRENT (AMPS) 5 6 Figure 4. On–Resistance versus Drain Current and Gate Voltage 1.6 VGS = 10 V ID = 1.5 A 1.6 Figure 4. On–Resistance versus Drain Current and Gate Voltage RDS(on) , DRAIN–TO–SOURCE RESISTANCE (NORMALIZED) RDS(on) , DRAIN–TO–SOURCE RESISTANCE (NORMALIZED) 1.4 VGS = 10 V ID = 2 A 1.4 1.2 1.2 1 1.0 0.8 0.8 0.6 – 50 – 25 0 25 50 75 100 125 150 0.6 – 50 – 25 0 25 50 75 100 125 150 TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C) Figure 5. On–Resistance Variation with Temperature Figure 5. On–Resistance Variation with Temperature 4 Motorola TMOS Power MOSFET Transistor Device Data MMDF2C02HD TYPICAL ELECTRICAL CHARACTERISTICS N–Channel 1000 VGS = 0 V TJ = 125°C 100°C 10 25°C 100 VGS = 0 V P–Channel TJ = 125°C I DSS , LEAKAGE (nA) 100 I DSS, LEAKAGE (nA) 10 100°C 1 0 12 16 8 VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS) 4 20 1 0 5 10 15 20 VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS) Figure 6. Drain–To–Source Leakage Current versus Voltage Figure 6. Drain–To–Source Leakage Current versus Voltage POWER MOSFET SWITCHING Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (∆t) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because drain–gate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG – VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turn–on and turn–off delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG – VGSP)] td(off) = RG Ciss In (VGG/VGSP) The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the off–state condition when calculating td(on) and is read at a voltage corresponding to the on–state when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses. Motorola TMOS Power MOSFET Transistor Device Data 5 MMDF2C02HD N–Channel 1400 1200 C, CAPACITANCE (pF) 1000 800 600 400 Coss 200 10 5 VGS 0 VDS 5 200 Crss 10 15 20 0 10 5 VGS 0 VDS 5 10 Crss Ciss VDS = 0 V Ciss C, CAPACITANCE (pF) VGS = 0 V TJ = 25°C 1200 1000 800 600 Crss 400 Coss Crss 15 20 Ciss VDS = 0 V Ciss P–Channel VGS = 0 V TJ = 25°C GATE–TO–SOURCE OR DRAIN–TO–SOURCE VOLTAGE (Volts) GATE–TO–SOURCE OR DRAIN–TO–SOURCE VOLTAGE (Volts) Figure 7. Capacitance Variation Figure 7. Capacitance Variation VGS, GATE–TO–SOURCE VOLTAGE (VOLTS) VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) 12 QT 10 VGS 8 6 4 2 Q3 0 0 2 4 6 8 10 VDS 12 QT, TOTAL GATE CHARGE (nC) Q1 Q2 ID = 3 A TJ = 25°C 24 20 16 12 8 4 0 14 12 QT 10 VGS 8 6 4 Q1 2 Q3 0 0 4 8 12 Q2 ID = 2 A TJ = 25°C VDS 18 15 12 9 6 3 0 16 VDS , DRAIN-TO-SOURCE VOLTAGE (VOLTS) v DS , DRAIN–TO–SOURCE VOLTAGE (VOLTS) QT, TOTAL GATE CHARGE (nC) Figure 8. Gate–To–Source and Drain–To–Source Voltage versus Total Charge Figure 8. Gate–To–Source and Drain–To–Source Voltage versus Total Charge 100 VDD = 10 V ID = 3 A VGS = 10 V tr TJ = 25°C t d(off) 10 tf td(on) 1000 VDD = 10 V ID = 2 A VGS = 10 V TJ = 25°C t, TIME (ns) t, TIME (ns) 100 td(off) tf tr 1 1 10 RG, GATE RESISTANCE (OHMS) 100 10 1 td(on) 10 RG, GATE RESISTANCE (OHMS) 100 Figure 9. Resistive Switching Time Variation versus Gate Resistance Figure 9. Resistive Switching Time Variation versus Gate Resistance 6 Motorola TMOS Power MOSFET Transistor Device Data MMDF2C02HD DRAIN–TO–SOURCE DIODE CHARACTERISTICS The switching characteristics of a MOSFET body diode are very important in systems using it as a freewheeling or commutating diode. Of particular interest are the reverse recovery characteristics which play a major role in determining switching losses, radiated noise, EMI and RFI. System switching losses are largely due to the nature of the body diode itself. The body diode is a minority carrier device, therefore it has a finite reverse recovery time, trr, due to the storage of minority carrier charge, QRR, as shown in the typical reverse recovery wave form of Figure 15. It is this stored charge that, when cleared from the diode, passes through a potential and defines an energy loss. Obviously, repeatedly forcing the diode through reverse recovery further increases switching losses. Therefore, one would like a diode with short t rr and low QRR specifications to minimize these losses. The abruptness of diode reverse recovery effects the amount of radiated noise, voltage spikes, and current ringing. The mechanisms at work are finite irremovable circuit parasitic inductances and capacitances acted upon by high N–Channel 3.0 2.5 I S , SOURCE CURRENT (AMPS) 2.0 1.5 1.0 0.5 0 0.50 VGS = 0 V TJ = 25°C I S , SOURCE CURRENT (AMPS) 2.0 VGS = 0 V TJ = 25°C 1.6 di/dts. The diode’s negative di/dt during ta is directly controlled by the device clearing the stored charge. However, the positive di/dt during tb is an uncontrollable diode characteristic and is usually the culprit that induces current ringing. Therefore, when comparing diodes, the ratio of tb/ta serves as a good indicator of recovery abruptness and thus gives a comparative estimate of probable noise generated. A ratio of 1 is considered ideal and values less than 0.5 are considered snappy. Compared to Motorola standard cell density low voltage MOSFETs, high cell density MOSFET diodes are faster (shorter trr), have less stored charge and a softer reverse recovery characteristic. The softness advantage of the high cell density diode means they can be forced through reverse recovery at a higher di/dt than a standard cell MOSFET diode without increasing the current ringing or the noise generated. In addition, power dissipation incurred from switching the diode will be less due to the shorter recovery time and lower switching losses. P–Channel 1.2 0.8 0.4 0.55 0.60 0.65 0.70 0.75 0.80 0 0.5 0.7 0.9 1.1 1.3 1.5 VSD, SOURCE–TO–DRAIN VOLTAGE (VOLTS) VSD, SOURCE–TO–DRAIN VOLTAGE (VOLTS) Figure 10. Diode Forward Voltage versus Current Figure 10. Diode Forward Voltage versus Current Motorola TMOS Power MOSFET Transistor Device Data 7 MMDF2C02HD di/dt = 300 A/µs I S , SOURCE CURRENT Standard Cell Density trr High Cell Density trr tb ta t, TIME Figure 11. Reverse Recovery Time (trr) SAFE OPERATING AREA The Forward Biased Safe Operating Area curves define the maximum simultaneous drain–to–source voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25°C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, “Transient Thermal Resistance – General Data and Its Use.” Switching between the off–state and the on–state may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded, and that the transition time (tr, tf) does not exceed 10 µs. In addition the total power averaged over a complete switching cycle must not exceed (TJ(MAX) – TC)/(RθJC). A power MOSFET designated E–FET can be safely used in switching circuits with unclamped inductive loads. For reliN–Channel 100 I D , DRAIN CURRENT (AMPS) VGS = 20 V SINGLE PULSE TC = 25°C Mounted on 2” sq. FR4 board (1” sq. 2 oz. Cu 0.06” thick single sided) with one die operating, 10s max. able operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and must be adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases non–linearly with an increase of peak current in avalanche and peak junction temperature. Although many E–FETs can withstand the stress of drain– to–source avalanche at currents up to rated pulsed current (IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the accompanying graph (Figure 13). Maximum energy at currents below rated continuous ID can safely be assumed to equal the values indicated. P–Channel 100 I D , DRAIN CURRENT (AMPS) VGS = 20 V SINGLE PULSE TC = 25°C Mounted on 2” sq. FR4 board (1” sq. 2 oz. Cu 0.06” thick single sided) with one die operating, 10s max. 10 100 µs 1 ms 10 ms 10 100 µs 1 ms 10 ms 1 dc 1 dc 0.1 RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 1 10 100 0.1 RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 1 10 100 0.01 0.1 0.01 0.1 VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS) VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS) Figure 12. Maximum Rated Forward Biased Safe Operating Area Figure 12. Maximum Rated Forward Biased Safe Operating Area 8 Motorola TMOS Power MOSFET Transistor Device Data MMDF2C02HD N–Channel 450 E , SINGLE PULSE DRAIN–TO–SOURCE AS AVALANCHE ENERGY (mJ) 400 350 300 250 200 150 100 50 0 25 50 75 100 125 150 E , SINGLE PULSE DRAIN–TO–SOURCE AS AVALANCHE ENERGY (mJ) ID = 9 A 350 ID = 6 A 300 250 200 150 100 50 0 25 50 75 100 125 150 P–Channel TJ, STARTING JUNCTION TEMPERATURE (°C) TJ, STARTING JUNCTION TEMPERATURE (°C) Figure 13. Maximum Avalanche Energy versus Starting Junction Temperature Figure 13. Maximum Avalanche Energy versus Starting Junction Temperature TYPICAL ELECTRICAL CHARACTERISTICS 10 Rthja(t), EFFECTIVE TRANSIENT THERMAL RESISTANCE 1 D = 0.5 0.2 0.1 0.05 0.02 0.01 0.1 Normalized to θja at 10s. Chip 0.0175 Ω 0.0710 Ω 0.2706 Ω 0.5776 Ω 0.7086 Ω 0.01 SINGLE PULSE 0.001 1.0E–05 1.0E–04 1.0E–03 1.0E–02 0.0154 F 0.0854 F 0.3074 F 1.7891 F 107.55 F Ambient 1.0E+03 1.0E–01 t, TIME (s) 1.0E+00 1.0E+01 1.0E+02 Figure 14. Thermal Response di/dt IS trr ta tb TIME tp IS 0.25 IS Figure 15. Diode Reverse Recovery Waveform Motorola TMOS Power MOSFET Transistor Device Data 9 MMDF2C02HD INFORMATION FOR USING THE SO–8 SURFACE MOUNT PACKAGE MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to ensure proper solder connection interface between the board and the package. With the correct pad geometry, the packages will self–align when subjected to a solder reflow process. 0.060 1.52 0.275 7.0 0.155 4.0 0.024 0.6 0.050 1.270 inches mm SO–8 POWER DISSIPATION The power dissipation of the SO–8 is a function of the input pad size. This can vary from the minimum pad size for soldering to the pad size given for maximum power dissipation. Power dissipation for a surface mount device is determined by TJ(max), the maximum rated junction temperature of the die, RθJA, the thermal resistance from the device junction to ambient; and the operating temperature, TA. Using the values provided on the data sheet for the SO–8 package, PD can be calculated as follows: PD = TJ(max) – TA RθJA the equation for an ambient temperature TA of 25°C, one can calculate the power dissipation of the device which in this case is 2.0 Watts. 150°C – 25°C = 2.0 Watts 62.5°C/W PD = The values for the equation are found in the maximum ratings table on the data sheet. Substituting these values into The 62.5°C/W for the SO–8 package assumes the recommended footprint on a glass epoxy printed circuit board to achieve a power dissipation of 2.0 Watts using the footprint shown. Another alternative would be to use a ceramic substrate or an aluminum core board such as Thermal Clad™. Using board material such as Thermal Clad, the power dissipation can be doubled using the same footprint. SOLDERING PRECAUTIONS The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. • Always preheat the device. • The delta temperature between the preheat and soldering should be 100°C or less.* • When preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When using infrared heating with the reflow soldering method, the difference shall be a maximum of 10°C. • The soldering temperature and time shall not exceed • When shifting from preheating to soldering, the maximum • After soldering has been completed, the device should be allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. • Mechanical stress or shock should not be applied during cooling. * Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device. temperature gradient shall be 5°C or less. 260°C for more than 10 seconds. 10 Motorola TMOS Power MOSFET Transistor Device Data MMDF2C02HD TYPICAL SOLDER HEATING PROFILE For any given circuit board, there will be a group of control settings that will give the desired heat pattern. The operator must set temperatures for several heating zones and a figure for belt speed. Taken together, these control settings make up a heating “profile” for that particular circuit board. On machines controlled by a computer, the computer remembers these profiles from one operating session to the next. Figure 16 shows a typical heating profile for use when soldering a surface mount device to a printed circuit board. This profile will vary among soldering systems, but it is a good starting point. Factors that can affect the profile include the type of soldering system in use, density and types of components on the board, type of solder used, and the type of board or substrate material being used. This profile shows temperature versus time. The line on the graph shows the actual temperature that might be experienced on the surface of a test board at or near a central solder joint. The two profiles are based on a high density and a low density board. The Vitronics SMD310 convection/infrared reflow soldering system was used to generate this profile. The type of solder used was 62/36/2 Tin Lead Silver with a melting point between 177 –189°C. When this type of furnace is used for solder reflow work, the circuit boards and solder joints tend to heat first. The components on the board are then heated by conduction. The circuit board, because it has a large surface area, absorbs the thermal energy more efficiently, then distributes this energy to the components. Because of this effect, the main body of a component may be up to 30 degrees cooler than the adjacent solder joints. STEP 1 PREHEAT ZONE 1 “RAMP” 200°C STEP 2 STEP 3 VENT HEATING “SOAK” ZONES 2 & 5 “RAMP” DESIRED CURVE FOR HIGH MASS ASSEMBLIES 150°C STEP 5 STEP 4 HEATING HEATING ZONES 3 & 6 ZONES 4 & 7 “SPIKE” “SOAK” 170°C 160°C STEP 6 VENT STEP 7 COOLING 205° TO 219°C PEAK AT SOLDER JOINT 150°C 100°C 100°C 140°C SOLDER IS LIQUID FOR 40 TO 80 SECONDS (DEPENDING ON MASS OF ASSEMBLY) 50°C DESIRED CURVE FOR LOW MASS ASSEMBLIES TIME (3 TO 7 MINUTES TOTAL) TMAX Figure 16. Typical Solder Heating Profile Motorola TMOS Power MOSFET Transistor Device Data 11 MMDF2C02HD PACKAGE DIMENSIONS –A– B M 8 5 X 45 _ J 1 4 4X –B– M_ G F NOTES: 1. DIMENSIONS A AND B ARE DATUMS AND T IS A DATUM SURFACE. 2. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 3. DIMENSIONS ARE IN MILLIMETER. 4. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 5. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE. 6. DIMENSION D DOES NOT INCLUDE MOLD PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. DIM A B C D F G J K M P R MILLIMETERS MIN MAX 4.80 5.00 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.18 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50 P 0.25 (0.010) M –T– 8X C SEATING PLANE D 0.25 (0.010) M K TB S A S R CASE 751–05 SO–8 ISSUE P STYLE 14: PIN 1. 2. 3. 4. 5. 6. 7. 8. N-SOURCE N-GATE P-SOURCE P-GATE P-DRAIN P-DRAIN N-DRAIN N-DRAIN Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of others. 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