MTE125N20E

MOTOROLA SEMICONDUCTOR TECHNICAL DATA Order this document by MTE125N20E/D ™ Data Sheet ISOTOP™ TMOS E-FET.™ Power Field Effect Transistor Designer's MTE125N20E Motorola Preferred Device N–Channel Enhancement–Mode Silicon Gate This advanced high voltage TMOS E–FET is designed to withstand high energy in the avalanche mode and switch efficiently. This new high energy device also offers a drain–to–source diode with fast recovery time. Designed for high voltage, high speed switching applications such as power supplies, PWM motor controls and other inductive loads, the avalanche energy capability is specified to eliminate the guesswork in designs where inductive loads are switched and offer additional safety margin against unexpected voltage transients. • 2500 V RMS Isolated Isotop Package • Avalanche Energy Specified • Source–to–Drain Diode Recovery Time Comparable to a Discrete Fast Recovery Diode • Diode is Characterized for Use in Bridge Circuits • Very Low Internal Parasitic Inductance • IDSS and VDS(on) Specified at Elevated Temperature • U.L. Recognized, File #E69369 G S Symbol VDSS VDGR VGS ID ID IDM PD TJ, Tstg EAS TMOS POWER FET 125 AMPERES 200 VOLTS RDS(on) = 0.015 OHM ® 4 1 2 3 D SOT–227B 1. 2. 3. 4. Source Gate Drain Source 2 MAXIMUM RATINGS (TC = 25°C unless otherwise noted) Rating Drain–Source Voltage Drain–Gate Voltage (RGS = 1.0 MΩ) Gate–Source Voltage — Continuous Drain Current — Continuous Drain Current — Continuous @ 100°C Drain Current — Single Pulse (tp ≤ 10 µs) Total Power Dissipation Derate above 25°C Operating and Storage Temperature Range Single Pulse Drain–to–Source Avalanche Energy (VDD = 50 Vdc, VGS = 10 Vdc, IL = 125 Apk, L = 0.05mH, RG = 25 Ω) RMS Isolation Voltage Thermal Resistance — Junction to Case Thermal Resistance — Junction to Ambient Maximum Lead Temperature for Soldering Purposes, 1/8″ from case for 10 seconds Value 200 200 ± 20 125 79 500 460 3.70 – 40 to 150 400 Unit Vdc Vdc Vdc Adc Watts W/°C °C mJ VISO RθJC RθJA TL 2500 0.28 62.5 260 Vac °C/W °C Designer’s Data for “Worst Case” Conditions — The Designer’s Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit curves — representing boundaries on device characteristics — are given to facilitate “worst case” design. E–FET is a trademark of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc. ISOTOP is a trademark of SGS–THOMSON Microelectronics. Preferred devices are Motorola recommended choices for future use and best overall value. REV 1 ©Motorola TMOS Power MOSFET Transistor Device Data Motorola, Inc. 1995 1 MTE125N20E ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted) Characteristic OFF CHARACTERISTICS Drain–Source Breakdown Voltage (VGS = 0 Vdc, ID = 250 µAdc) Temperature Coefficient (Positive) Zero Gate Voltage Drain Current (VDS = 200 Vdc, VGS = 0 Vdc) (VDS = 200 Vdc, VGS = 0 Vdc, TJ = 125°C) Gate–Body Leakage Current (VGS = ± 20 Vdc, VDS = 0) ON CHARACTERISTICS (1) Gate Threshold Voltage (VDS = VGS, ID = 250 µAdc) Threshold Temperature Coefficient (Negative) Static Drain–Source On–Resistance (VGS = 10 Vdc, ID = 62.5 Adc) Drain–Source On–Voltage (VGS = Vdc) (ID = 125 Adc) (ID = 62.5 Adc, TJ = 125°C) Forward Transconductance (VDS = 15 Vdc, ID = 62.5 Adc) DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance Reverse Transfer Capacitance SWITCHING CHARACTERISTICS (2) Turn–On Delay Time Rise Time Turn–Off Delay Time Fall Time Gate Charge (VDS = 160 Vdc, ID = 125 Adc, VGS =10 Vdc) (VDD = 250 Vdc, ID = 125 Adc, VGS = 10 Vdc, RG = 4.7 Ω) td(on) tr td(off) tf QT Q1 Q2 Q3 SOURCE–DRAIN DIODE CHARACTERISTICS Forward On–Voltage (1) (IS = 125 Adc, VGS = 0 Vdc) (IS = 125 Adc, VGS = 0 Vdc, TJ = 125°C) VSD — — trr (IS = 125 Adc, VGS = 0 Vdc, dIS/dt = 100 A/µs) Reverse Recovery Stored Charge INTERNAL PACKAGE INDUCTANCE Internal Drain Inductance (Measured from contact screw on tab to center of die) (Measured from the drain lead 0.25″ from package to center of die) Internal Source Inductance (Measured from the source lead 0.25″ from package to source bond pad) (1) Pulse Test: Pulse Width ≤ 300 µs, Duty Cycle ≤ 2%. (2) Switching characteristics are independent of operating junction temperature. LD — — LS — 3.5 5.0 5.0 — — — nH nH ta tb QRR — — — — 1.00 1.00 310 220 90 9.2 1.5 — — — — — µC ns Vdc — — — — — — — — 72 574 327 376 510 100 245 158 — — — — — — — — nC ns (VDS = 25 Vdc, VGS = 0 Vdc, f = 1.0 MHz) Ciss Coss Crss — — — 14400 3600 920 — — — pF VGS(th) 2.0 — RDS(on) VDS(on) — — gFS 50 — — 80 2.1 1.9 — mhos — 3.0 — 12 4.0 — 15 Vdc mV/°C mOhm Vdc V(BR)DSS 200 — IDSS — — IGSS — — — — 10 100 200 nAdc 215 250 — — Vdc mV/°C µAdc Symbol Min Typ Max Unit Reverse Recovery Time 2 Motorola TMOS Power MOSFET Transistor Device Data MTE125N20E TYPICAL ELECTRICAL CHARACTERISTICS 210 TJ = 25°C I D , DRAIN CURRENT (AMPS) VGS = 10 V 9V 140 6V 8V 7V I D , DRAIN CURRENT (AMPS) 120 160 VDS ≥ 10 V 80 70 5V 40 100°C 25°C TJ = – 55°C 4V 0 0 4 5 1 2 3 VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS) 6 0 3 4 6 5 VGS, GATE–TO–SOURCE VOLTAGE (VOLTS) 7 Figure 1. On–Region Characteristics RDS(on) , DRAIN–TO–SOURCE RESISTANCE (OHMS) RDS(on) , DRAIN–TO–SOURCE RESISTANCE (OHMS) Figure 2. Transfer Characteristics 0.028 VGS = 10 V 0.024 0.02 0.016 0.012 – 55°C 0.008 0.004 0 40 80 120 ID, DRAIN CURRENT (AMPS) 160 200 TJ = 100°C 0.02 TJ = 25°C 0.018 VGS = 10 V 25°C 0.016 15 V 0.014 0.012 0 40 80 120 ID, DRAIN CURRENT (AMPS) 160 200 Figure 3. On–Resistance versus Drain Current and Temperature Figure 4. On–Resistance versus Drain Current and Gate Voltage RDS(on) , DRAIN–TO–SOURCE RESISTANCE (NORMALIZED) 2.2 VGS = 10 V ID = 62.5 A 100000 VGS = 0 V 10000 I DSS, LEAKAGE (nA) TJ = 125°C 100°C 1.8 1.4 1000 1 100 25°C 0.6 10 0.2 – 50 – 25 0 50 100 25 75 TJ, JUNCTION TEMPERATURE (°C) 125 150 1 0 50 100 150 VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS) 200 Figure 5. On–Resistance Variation with Temperature Figure 6. Drain–To–Source Leakage Current versus Voltage Motorola TMOS Power MOSFET Transistor Device Data 3 MTE125N20E POWER MOSFET SWITCHING Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (∆t) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because drain–gate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG – VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turn–on and turn–off delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG – VGSP)] td(off) = RG Ciss In (VGG/VGSP) The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the off–state condition when calculating td(on) and is read at a voltage corresponding to the on–state when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses. 60000 VDS = 0 V Ciss C, CAPACITANCE (pF) 40000 Crss 20000 Coss Crss 0 10 5 VGS 0 VDS 5 10 15 Ciss VGS = 0 V TJ = 25°C 20 25 GATE–TO–SOURCE OR DRAIN–TO–SOURCE VOLTAGE (VOLTS) Figure 7. Capacitance Variation 4 Motorola TMOS Power MOSFET Transistor Device Data MTE125N20E VGS, GATE–TO–SOURCE VOLTAGE (VOLTS) 12 QT 10 8 6 4 2 0 Q3 60 120 VDS 300 180 240 360 420 Qg, TOTAL GATE CHARGE (nC) 480 Q1 Q2 ID = 62.5 A TJ = 25°C VGS 100 80 60 40 20 0 540 120 1000 VDD = 250 V tr ID = 125 A tf VGS = 10 V td(off) TJ = 25°C t, TIME (ns) VDS , DRAIN–TO–SOURCE VOLTAGE (VOLTS) 100 td(on) 10 1 10 RG, GATE RESISTANCE (OHMS) 100 0 Figure 8. Gate–To–Source and Drain–To–Source Voltage versus Total Charge Figure 9. Resistive Switching Time Variation versus Gate Resistance SAFE OPERATING AREA The Forward Biased Safe Operating Area curves define the maximum simultaneous drain–to–source voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25°C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, “Transient Thermal Resistance–General Data and Its Use.” Switching between the off–state and the on–state may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded and the transition time (tr,tf) do not exceed 10 µs. In addition the total power averaged over a complete switching cycle must not exceed (TJ(MAX) – TC)/(RθJC). A Power MOSFET designated E–FET can be safely used in switching circuits with unclamped inductive loads. For reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases non–linearly with an increase of peak current in avalanche and peak junction temperature. 125 100 VGS = 0 V TJ = 25°C I S , SOURCE CURRENT (AMPS) 75 50 25 0 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 1.2 VSD, SOURCE–TO–DRAIN VOLTAGE (VOLTS) Figure 10. Diode Forward Voltage versus Current Motorola TMOS Power MOSFET Transistor Device Data 5 MTE125N20E SAFE OPERATING AREA EAS, SINGLE PULSE DRAIN–TO–SOURCE AVALANCHE ENERGY (mJ) 1000 I D , DRAIN CURRENT (AMPS) VGS = 20 V SINGLE PULSE TC = 25°C 100 1 ms 400 350 300 250 200 150 100 50 0 25 50 75 100 125 TJ, STARTING JUNCTION TEMPERATURE (°C) 150 ID = 125 A 100 µs 10 RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 1 0.1 10 ms dc 1000 10 100 1 VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS) Figure 11. Maximum Rated Forward Biased Safe Operating Area Figure 12. Maximum Avalanche Energy versus Starting Junction Temperature 1 r(t), EFFECTIVE TRANSIENT THERMAL RESISTANCE (NORMALIZED) D = 0.5 0.2 0.1 0.1 0.05 0.02 0.01 0.01 CHIP JUNCTION 0.0174 Ω 0.0 F 0.1409 Ω 0.0994 F 0.1217 Ω 0.5750 F AMBIENT SINGLE PULSE 0.001 1.0E–05 1.0E–04 1.0E–03 1.0E–02 t, TIME (s) 1.0E–01 1.0E+00 1.0E+01 Figure 13. Thermal Response di/dt IS trr ta tb TIME tp IS 0.25 IS Figure 14. Diode Reverse Recovery Waveform 6 Motorola TMOS Power MOSFET Transistor Device Data MTE125N20E PACKAGE DIMENSIONS A B C H L R NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETERS. MILLIMETERS MIN MAX 31.50 31.70 7.80 8.20 4.10 4.30 14.90 15.10 30.10 30.30 38.00 38.20 4.00 11.80 12.20 8.90 9.10 12.60 12.80 25.20 25.40 1.95 2.05 4.10 0.75 0.85 5.50 INCHES MIN MAX 1.240 1.248 0.307 0.322 0.161 0.169 0.586 0.590 1.185 1.193 1.496 1.503 0.157 0.464 0.480 0.350 0.358 0.496 0.503 0.992 1.000 0.076 0.080 0.157 0.030 0.033 0.217 Q G 4 1 3 2 MN D E F Recommended screw torque: 1.3 Maximum screw torque: 1.5 Nm P S DIM A B C D E F G H L M N P Q R S " 0.2 Nm STYLE 1: PIN 1. 2. 3. 4. SOURCE GATE DRAIN SOURCE 2 SOT–227B Motorola TMOS Power MOSFET Transistor Device Data 7 MTE125N20E Motorola reserves the right to make changes without further notice to any products herein. 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