MTP20N06

MOTOROLA Designer's SEMICONDUCTOR TECHNICAL DATA Order this document by MTP20N06V/D TMOS Power Field Effect Transistor TMOS V is a new technology designed to achieve an on–resistance area product about one–half that of standard MOSFETs. This new technology more than doubles the present cell density of our 50 and 60 volt TMOS devices. Just as with our TMOS E–FET designs, TMOS V is designed to withstand high energy in the avalanche and commutation modes. Designed for low voltage, high speed switching applications in power supplies, converters and power motor controls, these devices are particularly well suited for bridge circuits where diode speed and commutating safe operating areas are critical and offer additional safety margin against unexpected voltage transients. New Features of TMOS V • On–resistance Area Product about One–half that of Standard MOSFETs with New Low Voltage, Low RDS(on) Technology • Faster Switching than E–FET Predecessors ™ Data Sheet V™ MTP20N06V TMOS POWER FET 20 AMPERES 60 VOLTS RDS(on) = 0.080 OHM N–Channel Enhancement–Mode Silicon Gate TM D G S CASE 221A–06, Style 5 TO–220AB Features Common to TMOS V and TMOS E–FETS • Avalanche Energy Specified • IDSS and VDS(on) Specified at Elevated Temperature • Static Parameters are the Same for both TMOS V and TMOS E–FET MAXIMUM RATINGS (TC = 25°C unless otherwise noted) Rating Drain–to–Source Voltage Drain–to–Gate Voltage (RGS = 1.0 MΩ) Gate–to–Source Voltage — Continuous Gate–to–Source Voltage — Non–Repetitive (tp ≤ 10 ms) Drain Current — Continuous Drain Current — Continuous @ 100°C Drain Current — Single Pulse (tp ≤ 10 µs) Total Power Dissipation Derate above 25°C Operating and Storage Temperature Range Single Pulse Drain–to–Source Avalanche Energy — Starting TJ = 25°C (VDD = 25 Vdc, VGS = 10 Vdc, Peak IL = 20 Apk, L = 1.0 mH, RG = 25 Ω) Thermal Resistance — Junction to Case Thermal Resistance — Junction to Ambient Maximum Lead Temperature for Soldering Purposes, 1/8″ from case for 10 seconds Symbol VDSS VDGR VGS VGSM ID ID IDM PD TJ, Tstg EAS RθJC RθJA TL Value 60 60 ± 20 ± 25 20 13 70 60 0.40 – 55 to 175 200 2.5 62.5 260 Unit Vdc Vdc Vdc Vpk Adc Apk Watts W/°C °C mJ °C/W °C Designer’s Data for “Worst Case” Conditions — The Designer’s Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit curves — representing boundaries on device characteristics — are given to facilitate “worst case” design. E–FET, Designer’s, and TMOS V are trademarks of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc. REV 1 © Motorola TMOS Motorola, Inc. 1996 Power MOSFET Transistor Device Data 1 MTP20N06V ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted) Characteristic OFF CHARACTERISTICS Drain–to–Source Breakdown Voltage (VGS = 0 Vdc, ID = 0.25 mAdc) Temperature Coefficient (Positive) Zero Gate Voltage Drain Current (VDS = 60 Vdc, VGS = 0 Vdc) (VDS = 60 Vdc, VGS = 0 Vdc, TJ = 150°C) Gate–Body Leakage Current (VGS = ± 20 Vdc, VDS = 0 Vdc) ON CHARACTERISTICS (1) Gate Threshold Voltage (VDS = VGS, ID = 250 µAdc) Threshold Temperature Coefficient (Negative) Static Drain–to–Source On–Resistance (VGS = 10 Vdc, ID = 10 Adc) Drain–to–Source On–Voltage (VGS = 10 Vdc, ID = 20 Adc) (VGS = 10 Vdc, ID = 10 Adc, TJ = 150°C) Forward Transconductance (VDS = 6.0 Vdc, ID = 10 Adc) DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance Reverse Transfer Capacitance SWITCHING CHARACTERISTICS (2) Turn–On Delay Time Rise Time Turn–Off Delay Time Fall Time Gate Charge (VDS = 48 Vdc, ID = 20 Adc, VGS = 10 Vdc) (VDD = 30 Vdc, ID = 20 Adc, VGS = 10 Vdc, RG = 9.1 Ω) td(on) tr td(off) tf QT Q1 Q2 Q3 SOURCE–DRAIN DIODE CHARACTERISTICS Forward On–Voltage (1) (IS = 20 Adc, VGS = 0 Vdc) (IS = 20 Adc, VGS = 0 Vdc, TJ = 150°C) VSD — — trr (IS = 20 Adc, VGS = 0 Vdc, dIS/dt = 100 A/µs) Reverse Recovery Stored Charge INTERNAL PACKAGE INDUCTANCE Internal Drain Inductance (Measured from contact screw on tab to center of die) (Measured from the drain lead 0.25″ from package to center of die) Internal Source Inductance (Measured from the source lead 0.25″ from package to source bond pad) (1) Pulse Test: Pulse Width ≤ 300 µs, Duty Cycle ≤ 2%. (2) Switching characteristics are independent of operating junction temperature. (3) Reflects typical values. Max limit – Typ Cpk = 3 x SIGMA LD — — LS — 7.5 — 3.5 4.5 — — nH nH ta tb QRR — — — — 1.05 0.96 60 52 8.0 0.172 1.6 — — — — — µC ns Vdc — — — — — — — — 8.7 77 26 46 28 4.0 9.0 8.0 20 150 50 90 40 — — — nC ns (VDS = 25 Vdc, VGS = 0 Vdc, f = 1.0 MHz) Ciss Coss Crss — — — 590 180 40 830 250 80 pF (Cpk ≥ 2.0) (3) VGS(th) 2.0 — (Cpk ≥ 2.0) (3) RDS(on) — VDS(on) — — gFS 6.0 — — 8.0 2.0 1.9 — mhos 0.065 0.080 Vdc 2.8 5.0 4.0 — Vdc mV/°C Ohm (Cpk ≥ 2.0) (3) V(BR)DSS 60 — IDSS — — IGSS — — — — 10 100 100 nAdc — 69 — — Vdc mV/°C µAdc Symbol Min Typ Max Unit Reverse Recovery Time 2 Motorola TMOS Power MOSFET Transistor Device Data MTP20N06V TYPICAL ELECTRICAL CHARACTERISTICS 40 I D , DRAIN CURRENT (AMPS) 35 30 25 20 15 10 5 0 0 1 2 3 4 5 6 7 8 9 5V 4V 10 6V VGS = 10V TJ = 25°C 7V 9V 8V I D , DRAIN CURRENT (AMPS) 40 35 30 25 20 15 10 5 0 2 3 4 5 6 7 8 9 100°C VDS ≥ 10 V TJ = –55°C 25°C VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS) VGS, GATE–TO–SOURCE VOLTAGE (VOLTS) Figure 1. On–Region Characteristics R DS(on) , DRAIN–TO–SOURCE RESISTANCE (OHMS) RDS(on) , DRAIN–TO–SOURCE RESISTANCE (OHMS) Figure 2. Transfer Characteristics 0.18 0.16 0.14 0.12 0.1 0.08 0.06 0.04 0.02 0 0 5 10 15 25 20 30 ID, DRAIN CURRENT (AMPS) 35 40 25°C – 55°C TJ = 100°C VGS = 10 V 0.11 0.1 0.09 0.08 0.07 0.06 0.05 0.04 TJ = 25°C VGS = 10 V 15 V 0 5 10 20 30 15 25 ID, DRAIN CURRENT (AMPS) 35 40 Figure 3. On–Resistance versus Drain Current and Temperature Figure 4. On–Resistance versus Drain Current and Gate Voltage RDS(on) , DRAIN–TO–SOURCE RESISTANCE (NORMALIZED) 2.0 1.75 1.5 1.25 1 0.75 0.5 0.25 0 –50 –25 0 25 50 75 100 125 TJ, JUNCTION TEMPERATURE (°C) 150 175 I DSS , LEAKAGE (nA) VGS = 10 V ID = 10 A 35 VGS = 0 V 30 25 20 15 10 5 0 100°C TJ = 125°C 0 50 10 20 30 40 VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS) 60 Figure 5. On–Resistance Variation with Temperature Figure 6. Drain–To–Source Leakage Current versus Voltage Motorola TMOS Power MOSFET Transistor Device Data 3 MTP20N06V POWER MOSFET SWITCHING Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (∆t) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because drain–gate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG – VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turn–on and turn–off delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG – VGSP)] td(off) = RG Ciss In (VGG/VGSP) 1600 1400 Ciss C, CAPACITANCE (pF) 1200 1000 800 600 400 200 0 Crss 10 5 VGS 0 VDS 5 10 15 20 25 Coss Ciss Crss The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the off–state condition when calculating td(on) and is read at a voltage corresponding to the on–state when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses. VDS = 0 V VGS = 0 V TJ = 25°C GATE–TO–SOURCE OR DRAIN–TO–SOURCE VOLTAGE (VOLTS) Figure 7. Capacitance Variation 4 Motorola TMOS Power MOSFET Transistor Device Data MTP20N06V VGS, GATE–TO–SOURCE VOLTAGE (VOLTS) 10 9 8 7 6 5 4 3 2 1 0 0 5 10 Q3 VDS 15 20 TJ = 25°C ID = 20 A 25 Q1 Q2 QT VGS 30 27 24 21 18 15 12 9 6 3 0 30 1000 VDS , DRAIN–TO–SOURCE VOLTAGE (VOLTS) TJ = 25°C ID = 20 A VDD = 30 V VGS = 10 V tr tf td(off) 10 td(on) t, TIME (ns) 100 1 1 10 RG, GATE RESISTANCE (OHMS) 100 Qg, TOTAL GATE CHARGE (nC) Figure 8. Gate–To–Source and Drain–To–Source Voltage versus Total Charge Figure 9. Resistive Switching Time Variation versus Gate Resistance DRAIN–TO–SOURCE DIODE CHARACTERISTICS 20 18 I S , SOURCE CURRENT (AMPS) 16 14 12 10 8 6 4 2 0 0.5 0.55 0.6 0.65 0.7 0.75 0.8 0.85 0.9 0.95 1 1.05 1.1 TJ = 25°C VGS = 0 V VSD, SOURCE–TO–DRAIN VOLTAGE (VOLTS) Figure 10. Diode Forward Voltage versus Current SAFE OPERATING AREA The Forward Biased Safe Operating Area curves define the maximum simultaneous drain–to–source voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25°C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, “Transient Thermal Resistance–General Data and Its Use.” Switching between the off–state and the on–state may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded and the transition time (tr,tf) do not exceed 10 µs. In addition the total power averaged over a complete switching cycle must not exceed (TJ(MAX) – TC)/(RθJC). A Power MOSFET designated E–FET can be safely used in switching circuits with unclamped inductive loads. For reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases non–linearly with an increase of peak current in avalanche and peak junction temperature. Although many E–FETs can withstand the stress of drain– to–source avalanche at currents up to rated pulsed current (IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the accompanying graph (Figure 12). Maximum energy at currents below rated continuous ID can safely be assumed to equal the values indicated. Motorola TMOS Power MOSFET Transistor Device Data 5 MTP20N06V SAFE OPERATING AREA 100 I D , DRAIN CURRENT (AMPS) 200 E , SINGLE PULSE DRAIN–TO–SOURCE AS AVALANCHE ENERGY (mJ) VGS = 20 V SINGLE PULSE TC = 25°C 180 160 140 120 100 80 60 40 20 0 0.1 1 10 VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS) 100 25 50 75 100 125 150 175 TJ, STARTING JUNCTION TEMPERATURE (°C) ID = 20 A 10 µs 100 µs 10 1 ms 10 ms 1 RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 0.1 dc Figure 11. Maximum Rated Forward Biased Safe Operating Area 1.00 D = 0.5 r(t), NORMALIZED EFFECTIVE TRANSIENT THERMAL RESISTANCE 0.2 0.1 0.10 0.02 0.01 SINGLE PULSE 0.05 P(pk) Figure 12. Maximum Avalanche Energy versus Starting Junction Temperature t2 DUTY CYCLE, D = t1/t2 1.0E–04 1.0E–03 1.0E–02 t, TIME (s) 1.0E–01 t1 RθJC(t) = r(t) RθJC D CURVES APPLY FOR POWER PULSE TRAIN SHOWN READ TIME AT t1 TJ(pk) – TC = P(pk) RθJC(t) 0.01 1.0E–05 1.0E+00 1.0E+01 Figure 13. Thermal Response di/dt IS trr ta tb TIME tp IS 0.25 IS Figure 14. Diode Reverse Recovery Waveform 6 Motorola TMOS Power MOSFET Transistor Device Data MTP20N06V PACKAGE DIMENSIONS –T– B 4 SEATING PLANE F T S C NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION Z DEFINES A ZONE WHERE ALL BODY AND LEAD IRREGULARITIES ARE ALLOWED. DIM A B C D F G H J K L N Q R S T U V Z INCHES MIN MAX 0.570 0.620 0.380 0.405 0.160 0.190 0.025 0.035 0.142 0.147 0.095 0.105 0.110 0.155 0.018 0.025 0.500 0.562 0.045 0.060 0.190 0.210 0.100 0.120 0.080 0.110 0.045 0.055 0.235 0.255 0.000 0.050 0.045 ––– ––– 0.080 MILLIMETERS MIN MAX 14.48 15.75 9.66 10.28 4.07 4.82 0.64 0.88 3.61 3.73 2.42 2.66 2.80 3.93 0.46 0.64 12.70 14.27 1.15 1.52 4.83 5.33 2.54 3.04 2.04 2.79 1.15 1.39 5.97 6.47 0.00 1.27 1.15 ––– ––– 2.04 Q 123 A U K STYLE 5: PIN 1. 2. 3. 4. GATE DRAIN SOURCE DRAIN H Z L V G D N R J CASE 221A–06 ISSUE Y Motorola TMOS Power MOSFET Transistor Device Data 7 MTP20N06V Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of others. 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