MTP8N06

MOTOROLA SEMICONDUCTOR TECHNICAL DATA Order this document by MTP8N06E/D ™ Data Sheet TMOS E-FET.™ Power Field Effect Transistor Designer's MTP8N06E Motorola Preferred Device N–Channel Enhancement–Mode Silicon Gate This advanced TMOS E–FET is designed to withstand high energy in the avalanche and commutation modes. The new energy efficient design also offers a drain–to–source diode with a fast recovery time. Designed for low voltage, high speed switching applications in power supplies, converters and PWM motor controls, these devices are particularly well suited for bridge circuits where diode speed and commutating safe operating areas are critical and offer additional safety margin against unexpected voltage transients. • Avalanche Energy Specified • Source–to–Drain Diode Recovery Time Comparable to a Discrete Fast Recovery Diode • Diode is Characterized for Use in Bridge Circuits • IDSS and VDS(on) Specified at Elevated Temperature TMOS POWER FET 8.0 AMPERES 60 VOLTS RDS(on) = 0.12 OHM ® D G S Symbol VDSS VDGR VGS VGSM ID ID IDM PD TJ, Tstg EAS RθJC RθJA TL CASE 221A–06, Style 5 TO–220AB MAXIMUM RATINGS (TC = 25°C unless otherwise noted) Rating Drain–Source Voltage Drain–Gate Voltage (RGS = 1.0 MΩ) Gate–Source Voltage — Continuous Gate–Source Voltage — Non–Repetitive (tp ≤ 10 ms) Drain Current — Continuous — Continuous @ 100°C — Single Pulse (tp ≤ 10 µs) Total Power Dissipation Derate above 25°C Operating and Storage Temperature Range Single Pulse Drain–to–Source Avalanche Energy — Starting TJ = 25°C (VDD = 25 Vdc, VGS = 10 Vdc, IL = 8.0 Apk, L = 3.0 mH, RG = 25 Ω) Thermal Resistance — Junction to Case — Junction to Ambient Maximum Lead Temperature for Soldering Purposes, 1/8″ from case for 10 seconds Value 60 60 ± 20 ± 30 8.0 6.4 24 40 0.32 – 55 to 150 96 3.13 62.5 260 Unit Vdc Vdc Vdc Vpk Adc Apk Watts W/°C °C mJ °C/W °C Designer’s Data for “Worst Case” Conditions — The Designer’s Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit curves — representing boundaries on device characteristics — are given to facilitate “worst case” design. E–FET and Designer’s are trademarks of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc. Preferred devices are Motorola recommended choices for future use and best overall value. REV 1 © Motorola TMOS Motorola, Inc. 1995 Power MOSFET Transistor Device Data 1 MTP8N06E ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted) Characteristic OFF CHARACTERISTICS Drain–Source Breakdown Voltage (VGS = 0 Vdc, ID = 250 µAdc) Temperature Coefficient (Positive) Zero Gate Voltage Drain Current (VDS = 60 Vdc, VGS = 0 Vdc) (VDS = 60 Vdc, VGS = 0 Vdc, TJ = 125°C) Gate–Body Leakage Current (VGS = ± 20 Vdc, VDS = 0) ON CHARACTERISTICS (1) Gate Threshold Voltage (VDS = VGS, ID = 250 µAdc) Temperature Coefficient (Negative) Static Drain–Source On–Resistance (VGS = 10 Vdc, ID = 4.0 Adc) Drain–Source On–Voltage (VGS = 10 Vdc) (ID = 8.0 Adc) (ID = 4.0 Adc, TJ = 125°C) Forward Transconductance (VDS = 10 Vdc, ID = 4.0 Adc) DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance Reverse Transfer Capacitance SWITCHING CHARACTERISTICS (2) Turn–On Delay Time Rise Time Turn–Off Delay Time Fall Time Gate Charge (See Figure 8) (VDS = 48 Vdc, ID = 8.0 Adc, VGS = 10 Vdc) (VDD = 30 Vdc, ID = 8.0 Adc, VGS = 10 Vdc, RG = 9.1 Ω) td(on) tr td(off) tf QT Q1 Q2 Q3 SOURCE–DRAIN DIODE CHARACTERISTICS Forward On–Voltage (1) (IS = 8.0 Adc, VGS = 0 Vdc) (IS = 8.0 Adc, VGS = 0 Vdc, TJ = 125°C) VSD — — trr (IS = 8.0 Adc, VGS = 0 Vdc, dIS/dt = 100 A/µs) Reverse Recovery Stored Charge INTERNAL PACKAGE INDUCTANCE Internal Drain Inductance (Measured from contact screw on tab to center of die) (Measured from the drain lead 0.25″ from package to center of die) Internal Source Inductance (Measured from the source lead 0.25″ from package to source bond pad) (1) Pulse Test: Pulse Width ≤ 300 µs, Duty Cycle ≤ 2%. (2) Switching characteristics are independent of operating junction temperature. LD — — LS — 3.5 4.5 7.5 — — — nH nH ta tb QRR — — — — 0.96 0.85 59.7 41 18.7 0.142 2.0 — — — — — µC ns Vdc — — — — — — — — 8.0 31 21 25 13.9 2.6 6.6 6.1 20 60 40 50 20 — — — nC ns (VDS = 25 Vdc, VGS = 0 Vdc, f = 1.0 MHz) Ciss Coss Crss — — — 424 180 45 570 250 90 pF VGS(th) 2.0 — RDS(on) VDS(on) — — gFS 3.0 0.7 — 4.8 1.2 1.0 — mhos — 3.0 5.0 0.087 4.0 — 0.12 Vdc mV/°C Ohm Vdc V(BR)DSS 60 — IDSS — — IGSS — — — — 10 100 100 nAdc — 63 — — Vdc mV/°C µAdc Symbol Min Typ Max Unit Reverse Recovery Time (See Figure 14) 2 Motorola TMOS Power MOSFET Transistor Device Data MTP8N06E TYPICAL ELECTRICAL CHARACTERISTICS 16 I D , DRAIN CURRENT (AMPS) TJ = 25°C VGS = 10 V 9V 8V 6V 16 7V I D , DRAIN CURRENT (AMPS) VDS ≥ 10 V TJ = – 55°C 12 100°C 8 25°C 12 8 4 5V 4 4V 0 0 1 2 3 4 0 2 3 4 5 6 7 8 VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS) VGS, GATE–TO–SOURCE VOLTAGE (VOLTS) Figure 1. On–Region Characteristics RDS(on) , DRAIN–TO–SOURCE RESISTANCE (OHMS) RDS(on) , DRAIN–TO–SOURCE RESISTANCE (OHMS) Figure 2. Transfer Characteristics 0.14 VGS = 10 V 0.12 TJ = 100°C 0.092 TJ = 25°C 0.088 VGS = 10 V 0.1 25°C 0.08 – 55°C 0.06 0.084 0.08 15 V 0.076 0.04 0 2 4 6 10 8 12 ID, DRAIN CURRENT (AMPS) 14 16 0.072 0 2 4 8 12 6 10 ID, DRAIN CURRENT (AMPS) 14 16 Figure 3. On–Resistance versus Drain Current and Temperature Figure 4. On–Resistance versus Drain Current and Gate Voltage RDS(on) , DRAIN–TO–SOURCE RESISTANCE (NORMALIZED) 1.6 VGS = 10 V ID = 4 A 10000 VGS = 0 V 1000 I DSS , LEAKAGE (nA) TJ = 125°C 1.4 1.2 100 1 0.8 10 25°C 1 0.6 – 50 – 25 0 25 50 75 100 125 150 0 10 20 30 40 50 60 TJ, JUNCTION TEMPERATURE (°C) VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS) Figure 5. On–Resistance Variation with Temperature Figure 6. Drain–To–Source Leakage Current versus Voltage Motorola TMOS Power MOSFET Transistor Device Data 3 MTP8N06E POWER MOSFET SWITCHING Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (∆t) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because drain–gate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG – VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turn–on and turn–off delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG – VGSP)] td(off) = RG Ciss In (VGG/VGSP) The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the off–state condition when calculating td(on) and is read at a voltage corresponding to the on–state when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses. 1200 VDS = 0 V 1000 C, CAPACITANCE (pF) Ciss 800 600 400 Coss 200 Crss 0 10 5 VGS 0 VDS 5 10 15 20 25 Crss Ciss VGS = 0 V TJ = 25°C GATE–TO–SOURCE OR DRAIN–TO–SOURCE VOLTAGE (VOLTS) Figure 7. Capacitance Variation 4 Motorola TMOS Power MOSFET Transistor Device Data MTP8N06E VGS, GATE–TO–SOURCE VOLTAGE (VOLTS) 12 QT 10 8 Q1 6 4 2 Q3 0 0 2 4 6 8 10 QT, TOTAL CHARGE (nC) VDS 12 ID = 8 A TJ = 25°C Q2 30 20 10 0 14 VGS 50 40 60 1000 VDD = 30 V ID = 8 A VGS = 10 V TJ = 25°C VDS , DRAIN–TO–SOURCE VOLTAGE (VOLTS) t, TIME (ns) 100 tr tf 10 td(off) td(on) 1 1 10 RG, GATE RESISTANCE (OHMS) 100 Figure 8. Gate–To–Source and Drain–To–Source Voltage versus Total Charge Figure 9. Resistive Switching Time Variation versus Gate Resistance DRAIN–TO–SOURCE DIODE CHARACTERISTICS 8 VGS = 0 V TJ = 25°C I S , SOURCE CURRENT (AMPS) 6 4 2 0 0.5 0.55 0.6 0.65 0.7 0.75 0.8 0.85 0.9 0.95 1 VSD, SOURCE–TO–DRAIN VOLTAGE (VOLTS) Figure 10. Diode Forward Voltage versus Current SAFE OPERATING AREA The Forward Biased Safe Operating Area curves define the maximum simultaneous drain–to–source voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25°C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, “Transient Thermal Resistance–General Data and Its Use.” Switching between the off–state and the on–state may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded and the transition time (tr,tf) do not exceed 10 µs. In addition the total power averaged over a complete switching cycle must not exceed (TJ(MAX) – TC)/(RθJC). A Power MOSFET designated E–FET can be safely used in switching circuits with unclamped inductive loads. For reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases non–linearly with an increase of peak current in avalanche and peak junction temperature. Although many E–FETs can withstand the stress of drain– to–source avalanche at currents up to rated pulsed current (IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the accompanying graph (Figure 12). Maximum energy at currents below rated continuous ID can safely be assumed to equal the values indicated. Motorola TMOS Power MOSFET Transistor Device Data 5 MTP8N06E SAFE OPERATING AREA 100 I D , DRAIN CURRENT (AMPS) VGS = 20 V SINGLE PULSE TC = 25°C 10 100 µs 1 ms 1 RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 0.1 0.1 1 10 100 VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS) 10 ms dc 100 E , SINGLE PULSE DRAIN–TO–SOURCE AS AVALANCHE ENERGY (mJ) ID = 8 A 80 10 µs 60 40 20 0 25 50 75 100 125 150 TJ, STARTING JUNCTION TEMPERATURE (°C) Figure 11. Maximum Rated Forward Biased Safe Operating Area Figure 12. Maximum Avalanche Energy versus Starting Junction Temperature 1 r(t), NORMALIZED EFFECTIVE TRANSIENT THERMAL RESISTANCE D = 0.5 0.2 0.1 0.1 0.02 0.01 SINGLE PULSE 0.01 1.0E–05 t2 DUTY CYCLE, D = t1/t2 1.0E–03 1.0E–02 t, TIME (s) 1.0E–01 t1 P(pk) 0.05 RθJC(t) = r(t) RθJC D CURVES APPLY FOR POWER PULSE TRAIN SHOWN READ TIME AT t1 TJ(pk) – TC = P(pk) RθJC(t) 1.0E–04 1.0E+00 1.0E+01 Figure 13. Thermal Response di/dt IS trr ta tb TIME tp IS 0.25 IS Figure 14. Diode Reverse Recovery Waveform 6 Motorola TMOS Power MOSFET Transistor Device Data MTP8N06E PACKAGE DIMENSIONS –T– B 4 SEATING PLANE F T S C NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION Z DEFINES A ZONE WHERE ALL BODY AND LEAD IRREGULARITIES ARE ALLOWED. DIM A B C D F G H J K L N Q R S T U V Z INCHES MIN MAX 0.570 0.620 0.380 0.405 0.160 0.190 0.025 0.035 0.142 0.147 0.095 0.105 0.110 0.155 0.018 0.025 0.500 0.562 0.045 0.060 0.190 0.210 0.100 0.120 0.080 0.110 0.045 0.055 0.235 0.255 0.000 0.050 0.045 ––– ––– 0.080 MILLIMETERS MIN MAX 14.48 15.75 9.66 10.28 4.07 4.82 0.64 0.88 3.61 3.73 2.42 2.66 2.80 3.93 0.46 0.64 12.70 14.27 1.15 1.52 4.83 5.33 2.54 3.04 2.04 2.79 1.15 1.39 5.97 6.47 0.00 1.27 1.15 ––– ––– 2.04 Q 123 A U K STYLE 5: PIN 1. 2. 3. 4. GATE DRAIN SOURCE DRAIN H Z L V G D N R J CASE 221A–06 ISSUE Y Motorola TMOS Power MOSFET Transistor Device Data 7 MTP8N06E Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters can and do vary in different applications. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of others. 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