SN54LS375J

SN54/74LS375 4-BIT D LATCH The SN54/ 74LS375 is a 4-Bit D-Type Latch for use as temporary storage for binary information between processing limits and input /output or indicator units. When the Enable (E) is HIGH, information present at the D input will be transferred to the Q output and, if E is HIGH, the Q output will follow the input. When E goes LOW, the information present at the D input prior to its setup time will be retained at the Q outputs. 4-BIT D LATCH LOW POWER SCHOTTKY CONNECTION DIAGRAM DIP (TOP VIEW) V CC 16 D 3 15 Q 3 14 Q 3 13 E 2,3 12 Q 2 11 Q 2 10 D 2 9 NOTE: The Flatpak version has the same pinouts (Connection Diagram) as the Dual In-Line Package. J SUFFIX CERAMIC CASE 620-09 16 1 1 D 0 2 Q 0 3 Q 0 4 E 0,1 5 Q 1 6 Q 1 7 D 1 8 GND 16 N SUFFIX PLASTIC CASE 648-08 1 TRUTH TABLE (Each latch) tn D H L PIN NAMES tn+1 Q H L NOTES: tn = bit time before enable negative-going transition. tn+1 = bit time after enable negative-going transition. 16 1 D SUFFIX SOIC CASE 751B-03 LOADING (Note a) HIGH LOW 0.25 U.L. 1.0 U.L. 1.0 U.L. 5 (2.5) U.L. 5 (2.5) U.L. ORDERING INFORMATION SN54LSXXXJ SN74LSXXXN SN74LSXXXD Ceramic Plastic SOIC D1 – D4 E0 – 1 E2 – 3 Q1 – Q4 Q1 – Q4 Data Inputs Enable Input Latches 0, 1 Enable Input Latches 2, 3 Latch Outputs (Note b) Complimentary Latch Outputs (Note b) 0.5 U.L. 2.0 U.L. 2.0 U.L. 10 U.L. 10 U.L. NOTES: a) 1 TTL Unit Load (U.L.) = 40 µA HIGH/1.6 mA LOW. b) The Output LOW drive factor is 25 U.L. for Military (54) and 5 U.L. for Commercial (74) Temperature Ranges. LOGIC SYMBOL 1 7 9 15 LOGIC DIAGRAM DATA Q 4 E 0,1 D 0 D 1 D 2 D 3 12 E 2,3 Q 0 Q 1 Q 2 Q 3 Q ENABLE 2 3 6 5 10 11 14 13 TO OTHER LATCH V = PIN 16 CC GND = PIN 8 FAST AND LS TTL DATA 5-528 SN54/74LS375 DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol VIH VIL VIK VOH Parameter Input HIGH Voltage 54 Input LOW Voltage 74 Input Clamp Diode Voltage 54 Output HIGH Voltage 74 54, 74 VOL Output LOW Voltage 74 D Input E Input IIH Input HIGH Current D Input E Input Input LOW Current D Input E Input – 20 0.1 0.4 – 0.4 – 1.6 – 100 12 mA mA mA mA VCC = MAX, VIN = 7.0 V VCC = MAX, VIN = 0.4 V VCC = MAX VCC = MAX 0.35 0.5 20 80 V µA 2.7 3.5 0.25 0.4 V V 2.5 – 0.65 3.5 0.8 – 1.5 V V Min 2.0 0.7 V Typ Max Unit V Test Conditions Guaranteed Input HIGH Voltage for All Inputs Guaranteed Input LOW Voltage for All Inputs VCC = MIN, IIN = – 18 mA VCC = MIN, IOH = MAX, VIN = VIH or VIL per Truth Table IOL = 4.0 mA IOL = 8.0 mA VCC = VCC MIN, VIN = VIL or VIH per Truth Table VCC = MAX, VIN = 2.7 V IIL IOS ICC Short Circuit Current (Note 1) Power Supply Current Note 1: Not more than one output should be shorted at a time, nor for more than 1 second. AC CHARACTERISTICS (TA = 25°C, VCC = 5.0 V) Limits Symbol tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL Parameter Propagation Delay, Data to Q Propagation Delay, Data to Q Propagation Delay, Enable to Q Propagation Delay, Enable to Q Min Typ 15 9.0 12 7.0 15 14 16 7.0 Max 27 17 20 15 27 25 30 15 Unit ns ns ns ns Test Conditions VCC = 5.0 V CL = 15 pF FAST AND LS TTL DATA 5-529 SN54/74LS375 LOGIC DIAGRAM DATA Q (SN54LS/74LS375 ONLY) Q ENABLE TO OTHER LATCH GUARANTEED OPERATING RANGES Symbol VCC TA IOH IOL Supply Voltage Operating Ambient Temperature Range Output Current — High Output Current — Low Parameter 54 74 54 74 54, 74 54 74 Min 4.5 4.75 – 55 0 Typ 5.0 5.0 25 25 Max 5.5 5.25 125 70 – 0.4 4.0 8.0 Unit V °C mA mA AC SETUP REQUIREMENTS (TA = 25°C, VCC = 5.0 V) Limits Symbol tW ts th Parameter Enable Pulse Width Setup Time Hold Time Min 20 20 0 Typ Max Unit ns ns ns VCC = 5.0 V Test Conditions AC WAVEFORMS D 1.3 V 1.3 V ts E 1.3 V tPLH Q tPLH 1.3 V 1.3 V th 1.3 V tPHL tPHL 1.3 V Q tPHL 1.3 V tPLH tPLH 1.3 V tPHL DEFINITION OF TERMS SETUP TIME (ts) — is defined as the minimum time required for the correct logic level to be present at the logic input prior to the clock transition from LOW-to-HIGH in order to be recognized and transferred to the outputs. HOLD TIME (th) — is defined as the minimum time following the clock transition from LOW-to-HIGH that the logic level must be maintained at the input in order to ensure continued recognition. A negative HOLD TIME indicates that the correct logic level may be released prior to the clock transition from LOW-to-HIGH and still be recognized. FAST AND LS TTL DATA 5-530 -A- Case 751B-03 D Suffix 16-Pin Plastic SO-16 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. 3. CONTROLLING DIMENSION: MILLIMETER. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. 751B 01 IS OBSOLETE, NEW STANDARD 751B 03. 16 9 -B1 8 P 8 PL 0.25 (0.010) M B M R X 45° G -TD 16 PL 0.25 (0.010) M C SEATING PLANE K T B S M F J A S DIM A B C D F G J K M P R MILLIMETERS MIN MAX 9.80 3.80 1.35 0.35 0.40 10.00 4.00 1.75 0.49 1.25 INCHES MIN MAX 0.386 0.150 0.054 0.014 0.016 0.393 0.157 0.068 0.019 0.049 1.27 BSC 0.19 0.10 0 0.25 0.25 7 0.050 BSC 0.008 0.004 0 0.009 0.009 7 ° ° ° ° 5.80 0.25 6.20 0.50 0.229 0.010 0.244 0.019 Case 648-08 N Suffix 16-Pin Plastic -A16 9 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. 3. CONTROLLING DIMENSION: INCH. DIMENSION L" TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B" DOES NOT INCLUDE MOLD FLASH. 5. 6. ROUNDED CORNERS OPTIONAL. 648 01 THRU 07 OBSOLETE, NEW STANDARD 648 08. B 1 8 F S C -TK SEATING PLANE L H G D 16 PL 0.25 (0.010) M J M T A M DIM A B C D F G H J K L M S MILLIMETERS MIN MAX 18.80 6.35 3.69 0.39 1.02 19.55 6.85 4.44 0.53 1.77 INCHES MIN MAX 0.740 0.250 0.145 0.015 0.040 0.770 0.270 0.175 0.021 0.070 2.54 BSC 1.27 BSC 0.21 2.80 7.50 0 0.38 3.30 7.74 10 0.100 BSC 0.050 BSC 0.008 0.110 0.295 0 0.015 0.130 0.305 10 ° ° ° ° 0.51 1.01 0.020 0.040 -A16 9 Case 620-09 J Suffix 16-Pin Ceramic Dual In-Line NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. -B1 8 3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 4. DIM F MAY NARROW TO 0.76 (0.030) WHERE THE LEAD ENTERS THE CERAMIC BODY. C L 5. 620 01 THRU 08 OBSOLETE, NEW STANDARD 620 09. -TSEATING PLANE K E F D 16 PL 0.25 (0.010) M N G T A S M J 16 PL 0.25 (0.010) M T B S DIM A B C D E F G J K L M N MILLIMETERS MIN MAX 19.05 6.10 19.55 7.36 4.19 0.39 0.53 INCHES MIN MAX 0.750 0.240 0.770 0.290 0.165 0.015 0.021 1.27 BSC 1.40 1.77 0.050 BSC 0.055 0.070 2.54 BSC 0.23 0.27 5.08 7.62 BSC 0 0.100 BSC 0.009 0.011 0.200 0.300 BSC 0 ° 15 ° ° 15 ° 0.39 0.88 0.015 0.035 FAST AND LS TTL DATA 5-531 Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters can and do vary in different applications. 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ASIA PACIFIC: Motorola Semiconductors H.K. Ltd.; Silicon Harbour Center, No. 2 Dai King Street, Tai Po Industrial Estate, Tai Po, N.T., Hong Kong. ◊ FAST AND LS TTL DATA 5-532