MP2499DS-LF

MP2499 The Future of Analog IC Technology Integrated 100V Load Dump Protection 2A, 100kHz Step Down Regulator with Programmable Output Current DESCRIPTION FEATURES The MP2499 is a monolithic step-down switch mode converter with a programmable output current limit and an integrated input overvoltage protection switch. It achieves 2.0A continuous output current over a wide input supply range with excellent load and line regulation. • • • • • • • • The maximum output current can be programmed by sensing current through the inductor DC resistance (DCR) or an accurate sense resistor. Fault condition protection includes cycle-by-cycle current limiting and thermal shutdown. The MP2499 can survive high-voltage transients such as those found in automotive and industrial applications. The MP2499 requires a minimum number of readily available standard external components. The MP2499 is available in a 16-pin SOIC package. • • • • Replaces External Transorb Supports 12V/24V Systems Input Surge Protection Up to 100V Programmable Output Current up to 2.0A Output Adjustable Fixed 100kHz Frequency 0.25Ω Internal Power MOSFET Switch Stable with Low ESR Output Ceramic Capacitors 92% Efficiency @ 500mA (Vo=5V) Thermal Shutdown Cycle-by-Cycle Over Current Protection Available in a 16-Pin SOIC Package APPLICATIONS • • • • • 12V/24V Systems with High Input Surge Automotive Cigarette Lighter Adapters Power Supply for Linear Chargers Industrial Power Supplies Avionics “MPS” and “The Future of Analog IC Technology” are Registered Trademarks of Monolithic Power Systems, Inc. TYPICAL APPLICATION MP2499 Rev. 0.91 11/24/2010 www.MonolithicPower.com MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited. © 2010 MPS. All Rights Reserved. 1 MP2499– INTEGRATED 100V LOAD DUMP PROTECTION, 2A STEP DOWN REGULATOR ORDERING INFORMATION Part Number* MP2499DS Package SOIC16 Top Marking MP2499DS Free Air Temperature (TA) –40°C to +85°C * For Tape & Reel, add suffix –Z (e.g. MP2499DS–Z). For RoHS compliant packaging, add suffix –LF (e.g. MP2499DS–LF–Z) PACKAGE REFERENCE TOP VIEW FB 1 16 EN SS 2 15 GND ISP 3 14 VDD ISN 4 13 SW CTR 5 12 BST N/C 6 11 N/C IN 7 10 OUT IN 8 9 OUT ABSOLUTE MAXIMUM RATINGS (1) Supply Voltage IN ...................................... 100V IN to CTR ...................................... -0.3V to 100V OUT to CTR .................................... -0.3V to 45V VDD ............................................................... 58V VSW ...................................... –0.3V to VDD + 0.3V VBST ................................................... VSW + 6.5V VISN, vISP ................................................ 0V to15V All Other Pins .............................. –0.3V to +6.5V (2) Continuous Power Dissipation (TA = +25°C) ............................................................ .1.6W Junction Temperature ...............................150°C Lead Temperature ....................................260°C Storage Temperature .............. –65°C to +150°C MP2499 Rev. 0.91 11/24/2010 Recommended Operating Conditions (3) Car Battery Input Voltage .................. 12V to 24V Surge Voltage VIN............... 90V/200ms duration VDD ............................................................... 55V Output Voltage VOUT ........................... 3.3V to 5V Operating Junct. Temp (TJ) ..... –40°C to +125°C Thermal Resistance (4) θJA θJC SOIC16 ................................... 80 ...... 30 ... °C/W Notes: 1) Exceeding these ratings may damage the device. 2) The maximum allowable power dissipation is a function of the maximum junction temperature TJ (MAX), the junction-toambient thermal resistance θJA, and the ambient temperature TA. The maximum allowable continuous power dissipation at any ambient temperature is calculated by PD (MAX) = (TJ (MAX)-TA)/θJA. Exceeding the maximum allowable power dissipation will cause excessive die temperature, and the regulator will go into thermal shutdown. Internal thermal shutdown circuitry protects the device from permanent damage. 3) The device is not guaranteed to function outside of its operating conditions. 4) Measured on JESD51-7, 4-layer PCB. www.MonolithicPower.com MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited. © 2010 MPS. All Rights Reserved. 2 MP2499– INTEGRATED 100V LOAD DUMP PROTECTION, 2A STEP DOWN REGULATOR ELECTRICAL CHARACTERISTICS VIN = 12V, TA = +25°C, unless otherwise noted. Parameters Symbol Feedback Voltage VFB Feedback Bias Current PWM Switch On Resistance OV Protection Switch On Resistance Switch Leakage Current Limit Oscillator Frequency Boot-Strap Voltage Minimum On Time Under Voltage Lockout Threshold Rising IBIAS(FB) RDS(ON) Condition Min Typ Max Units 4.5V ≤ VIN ≤ 36V VFB = 0.8V 0.78 0.8 0.82 V VOUT = VCTR VEN = 0V, VSW = 0V fSW VFB = 0.6V VBST - VSW tON VFB = 1V 80 3.0 Under Voltage Lockout Threshold Hysteresis EN Input Low 10 120 3.6 200 Voltage (5) En Input High Voltage 1.8 VEN = 0-6V Supply Current (Shutdown) VEN = 0V Supply Current (Quiescent) VEN = 2V, VFB = 1V –10 Shutdown(5) VISP –VISN VISP, VISN IBIAS (ISN,ISP) VISP, VISN 0.4–15V 0.4–15V 90 –1 V V –2 10 µA 4 10 µA 500 800 µA 150 Current Sense Voltage Input Bias Current (ISN, ISP) nA Ω Ω µA A kHz V ns V mV 0.4 (5) EN Input Bias Current (5) Thermal 10 0.25 0.3 0.1 3.0 100 4.3 100 3.3 100 0.5 °C 110 +1 mV µA Note: 5) Guaranteed by design MP2499 Rev. 0.91 11/24/2010 www.MonolithicPower.com MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited. © 2010 MPS. All Rights Reserved. 3 MP2499– INTEGRATED 100V LOAD DUMP PROTECTION, 2A STEP DOWN REGULATOR PIN FUNCTIONS PIN # Name 1 FB 2 SS 3 4 ISP ISN 5 CTR 6 7 8 9 10 11 N/C IN IN OUT OUT N/C 12 BST 13 SW 14 VDD 15 GND 16 EN MP2499 Rev. 0.91 11/24/2010 Description Feedback. An external resistor divider from the output to GND, tapped to the FB pin sets the output voltage. To prevent current limit run away during a short circuit fault condition the frequency-fold-back comparator lowers the oscillator frequency when the FB voltage is below 250mV. Connect to an external capacitor used for Soft-Start and compensation for current limiting loop. Positive Current Sense Negative Current Sense Input for load current limiting. Control pin. Tie a zener diode from CTR to ground. The zener voltage should equal to normal output voltage. No connection Input. Connect input power supply, which may have surge voltage to IN pin. Input. Connect input power supply, which may have surge voltage to IN pin. Output Pin. Connect to VDD pin. Output Pin. Connect to VDD pin. No connection Bootstrap. This capacitor is needed to drive the power switch’s gate above the supply voltage. It is connected between SW and BST pins to form a floating supply across the power switch driver. An on-chip regulator is used to charge up the external bootstrap capacitor. If the on-chip regulator is not strong enough, an optional diode can be connected from IN or OUT to charge the external bootstrap capacitor. Switch Output. It is the source of power device. Supply Voltage Bypass pin. This pin is also the output of the OV protection switch. The MP2499 operates from a +5V to +36V unregulated input. CIN is needed to prevent large voltage spikes from appearing at the input. Put CIN as close to the IC as possible. It is the drain of the internal power device and power supply for the whole chip. Ground. This pin is the voltage reference for the regulated output voltage. For this reason care must be taken in its layout. This node should be placed outside of the D1 to CIN ground path to prevent switching current spikes from inducing voltage noise into the part. On/Off Control Input. www.MonolithicPower.com MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited. © 2010 MPS. All Rights Reserved. 4 MP2499– INTEGRATED 100V LOAD DUMP PROTECTION, 2A STEP DOWN REGULATOR TYPICAL PERFORMANCE CHARACTERISTICS C1=220µF, C2=2.2µF, C3=39µF, C4=22µF, L=39µH, VOUT=5V, TA=25ºC, unless otherwise noted. MP2499 Rev. 0.91 11/24/2010 www.MonolithicPower.com MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited. © 2010 MPS. All Rights Reserved. 5 MP2499– INTEGRATED 100V LOAD DUMP PROTECTION, 2A STEP DOWN REGULATOR TYPICAL PERFORMANCE CHARACTERISTICS (continued) C1=220µF, C2=2.2µF, C3=39µF, C4=22µF, L=39µH, VOUT=5V, TA=25ºC, unless otherwise noted. MP2499 Rev. 0.91 11/24/2010 www.MonolithicPower.com MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited. © 2010 MPS. All Rights Reserved. 6 MP2499– INTEGRATED 100V LOAD DUMP PROTECTION, 2A STEP DOWN REGULATOR TYPICAL PERFORMANCE CHARACTERISTICS (continued) C1=220µF, C2=2.2µF, C3=39µF, C4=22µF, L=39µH, VOUT=5V, TA=25ºC, unless otherwise noted. MP2499 Rev. 0.91 11/24/2010 www.MonolithicPower.com MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited. © 2010 MPS. All Rights Reserved. 7 MP2499– INTEGRATED 100V LOAD DUMP PROTECTION, 2A STEP DOWN REGULATOR OPERATION Main Control Loop The MP2499 is a current mode buck regulator. That is, the error amplifier (EA) output voltage is proportional to the peak inductor current. At the beginning of a cycle, the integrated high side power switch M1 (Fig.1) is off; the EA output voltage is higher than the current sense amplifier output; and the current comparator’s output is low. The rising edge of the 100kHz clock signal sets the RS Flip-Flop. Its output turns on M1 thus connecting the SW pin and inductor to the input supply. The increasing inductor current is sensed and amplified by the Current Sense Amplifier. Ramp compensation is added to Current Sense Amplifier output and compared to the Error Amplifier output by the PWM Comparator. When the Current Sense Amplifier plus Slope Compensation signal exceeds the EA output voltage, the RS Flip-Flop is reset and the MP2499 reverts to its initial M1 off state. If the Current Sense Amplifier plus Slope Compensation signal does not exceed the COMP voltage, then the falling edge of the CLK resets the Flip-Flop. Load Current Limiting Loop The output current information is sensed via the ISP and ISN pins. The regulation threshold is set at 100mV. If VSENSE, the difference of VISP and VISN, is less than 100mV, the output voltage of the power supply will be set by the FB pin. If VSENSE reaches 100mV, the current limit loop will pull down SS and regulate the output at a constant current determined by the external sense resistor. The external capacitor on SS pin is the dominant compensation capacitor for load current regulation loop. The capacitor has normal value of 100nF, which will put the bandwidth of load current regulation loop to be less than 1kHz. When VSENSE is higher than 100mV, SS will not drop down to the final regulation level immediately. It will cause the load current to be higher than the programmed level for a short period. A fast comparator is added to shut down power switch when the average load current is higher than 120% of the programmed current limit level. An inductor DC resistance (DCR) or accurate sense resistor can be used for load current sensing. The output of the Error Amplifier integrates the voltage difference between the feedback and the 0.8V bandgap reference. The polarity is such that a FB pin voltage lower than 0.8V increases the EA output voltage. Since the EA output voltage is proportional to the peak inductor current, an increase in its voltage increases current delivered to the output. An external Schottky Diode (D1) carries the inductor current when M1 is off. MP2499 Rev. 0.91 11/24/2010 www.MonolithicPower.com MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited. © 2010 MPS. All Rights Reserved. 8 MP2499– INTEGRATED 100V LOAD DUMP PROTECTION, 2A STEP DOWN REGULATOR Figure 1—Function Block Diagram MP2499 Rev. 0.91 11/24/2010 www.MonolithicPower.com MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited. © 2010 MPS. All Rights Reserved. 9 MP2499– INTEGRATED 100V LOAD DUMP PROTECTION, 2A STEP DOWN REGULATOR APPLICATION INFORMATION Setting the Output Voltage The external resistor divider is used to set the output voltage (see the schematic on front page). The feedback resistor R1 also sets the feedback loop bandwidth with the internal compensation capacitor (see Figure 1). Choose R1 to be around 300kΩ for optimal transient response. R2 is then given by: R2 = R1 VOUT −1 0 .8 V Table 1—Resistor Selection for Common Output Voltages VOUT (V) R1 (kΩ) R2 (kΩ) 1.8 2.5 3.3 5 300 (1%) 300 (1%) 300 (1%) 300 (1%) 240 (1%) 141.1(1%) 96 (1%) 57.1 (1%) Selecting the Inductor A 33µH to 47µH inductor with a DC current rating of at least 25% percent higher than the maximum load current is recommended for most applications. For highest efficiency, the inductor DC resistance should be less than 200mΩ. For most designs, the inductance value can be derived from the following equation. L= VOUT × ( VIN − VOUT ) VIN × ∆IL × f SW Where ∆IL is the inductor ripple current. Choose inductor current ripple to be approximately 30% of the maximum load current,. The maximum inductor peak current is: IL(MAX ) = ILOAD + ∆I L 2 Selecting the Input Capacitor The input capacitor reduces the surge current drawn from the input and also the switching noise from the device. The input capacitor impedance at the switching frequency should be less than the input source impedance to prevent high frequency switching current from pass to the input. Ceramic capacitors with X5R or X7R dielectrics are highly recommended because of their low ESR and small temperature coefficients. For most applications, a 220µF electrolytic capacitor is sufficient. Selecting the Output Capacitor The output capacitor keeps output voltage small and ensures regulation loop stability. The output capacitor impedance should be low at the switching frequency. Ceramic capacitors with X5R or X7R dielectrics are recommended. Selecting D2 Diode The D2 Zener diode voltage is a reference voltage to control the clamp voltage of the OVP protection during a surge condition to choose the Zener voltage to be the same as the input voltage to reduce any OVP protection losses. Refer to the typical operation curve on page 6 titled “Clamp Voltage vs. VDD-VCTR” to make sure the VDD voltage doesn’t exceed the maximum input voltage, when a surge voltage is applied to the OVP protection. Selecting Soft Start Capacitor MP2499 has external soft start function. This external function reduces the start up current surge into the output capacitor. This allows the gradual built up of output voltage to its final set value. The soft start time is decided by following equation: TSS = 0.7 × CSS 39 × 10 −6 Under light load conditions below 100mA, larger inductance is recommended for improved efficiency. MP2499 Rev. 0.91 11/24/2010 www.MonolithicPower.com MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited. © 2010 MPS. All Rights Reserved. 10 MP2499– INTEGRATED 100V LOAD DUMP PROTECTION, 2A STEP DOWN REGULATOR Output Current Sensing The output current can be sensed through the DC resistance (DCR) of the inductor, as shown in Figure 2a. In Figure 2a, the output current limit is set as: IOUT = 100mV Ra + Rb × DCR Rb Where DCR is the DC resistance of the inductor winding. DCR L1 SW Ra Cs VOUT COUT ISP Rb ISN In Figure 2a, it is desirable to keep (a) R a ⋅ Rb L1 × CS = R a + Rb DCR For more accurate sensing, use a more accurate (1% or less) sense resistor, as in Figure 2b, where the output current limit is set as: IOUT = 100mV RSENSE RSENSE L1 SW VOUT COUT ISP ISN (b) Figure 2—Current Sensing Methods MP2499 Rev. 0.91 11/24/2010 www.MonolithicPower.com MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited. © 2010 MPS. All Rights Reserved. 11 MP2499– INTEGRATED 100V LOAD DUMP PROTECTION, 2A STEP DOWN REGULATOR PACKAGE INFORMATION SOIC16 0.386( 9.80) 0.394(10.00) 0.024(0.61) 9 16 0.063 (1.60) 0.150 (3.80) 0.157 (4.00) PIN 1 ID 0.050(1.27) 0.228 (5.80) 0.244 (6.20) 0.213 (5.40) 8 1 TOP VIEW RECOMMENDED LAND PATTERN 0.053(1.35) 0.069(1.75) SEATING PLANE 0.050(1.27) BSC 0.013(0.33) 0.020(0.51) 0.004(0.10) 0.010(0.25) SEE DETAIL "A" SIDE VIEW FRONT VIEW 0.010(0.25) x 45o 0.020(0.50) GAUGE PLANE 0.010(0.25) BSC 0o-8o 0.016(0.41) 0.050(1.27) 0.0075(0.19) 0.0098(0.25) NOTE: 1) CONTROL DIMENSION IS IN INCHES. DIMENSION IN BRACKET IS IN MILLIMETERS. 2) PACKAGE LENGTH DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. 3) PACKAGE WIDTH DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. 4) LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.004" INCHES MAX. 5) DRAWING CONFORMS TO JEDEC MS-012, VARIATION AC. 6) DRAWING IS NOT TO SCALE. DETAIL "A" NOTICE: The information in this document is subject to change without notice. Please contact MPS for current specifications. Users should warrant and guarantee that third party Intellectual Property rights are not infringed upon when integrating MPS products into any application. MPS will not assume any legal responsibility for any said applications. MP2499 Rev. 0.91 11/24/2010 www.MonolithicPower.com MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited. © 2010 MPS. All Rights Reserved. 12