MP38115DQ-LF-Z

MP38115 Ultra Low Voltage, 4A, 5.5V Synchronous Step-Down Switching Regulator RE C N O RE E M W FE D ME R E N TO SI DE G D M NS F P2 O R 14 7 The Future of Analog IC Technology DESCRIPTION FEATURES The MP38115 is an internally compensated 1.5MHz fixed frequency PWM synchronous step-down regulator. MP38115 operates from a 1.1V to 5.5V input and generates an output voltage as low as 0.8V. • • • • • • • • • • • • • • The MP38115 integrates a 60mΩ high-side switch and a 60mΩ synchronous rectifier for high efficiency without an external Schottky diode. With peak current mode control and internal compensation, the MP38115 based solution delivers a very compact footprint with a minimum component count. The MP38115 is available in a small 3mm x 3mm 10-lead QFN package. 4A Output Current Input Operation Range: 1.1V to 5.5V 60mΩ Internal Power MOSFET Switches All Ceramic Capacitor Design Up to 95% Efficiency 1.5MHz Fixed Switching Frequency Adjustable Output from 0.8V to 0.9xVIN Internal Soft-Start Frequency Synchronization Input Power Good Output Cycle-by-Cycle Current Limiting Hiccup Short Circuit Protection Thermal Shutdown 3mm x 3mm 10-lead QFN Package APPLICATIONS • • • • µP/ASIC/DSP/FPGA Core and I/O Supplies Printers and LCD TVs Network and Telecom Equipment Point of Load Regulators “MPS” and “The Future of Analog IC Technology” are Registered Trademarks of Monolithic Power Systems, Inc. TYPICAL APPLICATION NO T VIN 1.1V to 5.5V IN VCC 2.7V to 5.5V MP38115 Rev. 0.92 8/11/2009 OFF ON BS VCC SW MP38115 EN/SYNC GND VOUT 1.1V / 4A FB www.MonolithicPower.com MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited. © 2009 MPS. All Rights Reserved. 1 MP38115 – 4A, 5.5V SYNCHRONOUS STEP-DOWN SWITCHING REGULATOR ABSOLUTE MAXIMUM RATINGS (1) RE C N O RE E M W FE D ME R E N TO SI DE G D M NS F P2 O R 14 7 PACKAGE REFERENCE TOP VIEW FB 1 10 EN/SYNC GND 2 9 GND SW 3 8 SW IN 4 7 IN BS 5 6 VCC Recommended Operating Conditions (2) Supply Volts VIN .............................. 1.1V to 5.5V Supply Voltage VCC ......................... 2.7V to 5.5V Output Voltage VOUT ................. 0.8V to 0.9 x VIN Operating Temperature ............. –40°C to +85°C EXPOSED PAD ON BACKSIDE Part Number* Package QFN10 (3mm x 3mm) MP38115DQ * IN to GND ................................... –0.3V to +6.0V VCC to GND .............................. –0.3V to + 6.0V SW to GND .......................... –0.3V to VIN + 0.3V ............................ –2.5V to VIN + 2.5V for < 50ns FB, EN/SYNC to GND .................. –0.3V to +6.5V BS to SW .................................... –0.3V to +6.5V Junction Temperature...............................150°C Lead Temperature ....................................260°C Storage Temperature .............. –65°C to +150°C Temperature Top Marking –40°C to +85°C W2YW For Tape & Reel, add suffix –Z (e.g. MP38115DQ–Z) For RoHS Compliant Packaging, add suffix –LF (e.g. MP38115DQ–LF–Z) Thermal Resistance (3) θJA θJC QFN10 (3mm x 3mm) ............. 50 ...... 12... °C/W Notes: 1) Exceeding these ratings may damage the device. 2) The device is not guaranteed to function outside of its operating conditions. 3) Measured on JESD51-7, 4-layer PCB.. ELECTRICAL CHARACTERISTICS (4) VCC = VEN = 3.6V, TA = +25°C, unless otherwise noted. Parameters Supply Current T Shutdown Current VCC Undervoltage Lockout Threshold VCC Undervoltage Lockout Hysteresis Condition VEN = VCC VFB = 0.85V VEN = 0V, VCC = 5.5V Rising Edge TA = +25°C FB Input Current EN High Threshold EN Low Threshold Internal Soft-Start Time High-Side Switch On-Resistance Low-Side Switch On-Resistance VFB = 0.85V –40°C ≤ TA ≤ +85°C –40°C ≤ TA ≤ +85°C NO Typ ISW = 300mA ISW = –300mA VEN = 0V; VCC = 5.5V, VIN = 5.5V VSW = 0V or 5.5V 0.784 μA 1 μA 0.800 2.69 0.816 ±50 1.6 0.4 120 60 60 –10 www.MonolithicPower.com MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited. © 2009 MPS. All Rights Reserved. Units 750 2.59 BS Under Voltage Lockout Threshold MP38115 Rev. 0.92 8/11/2009 Max 210 Regulated FB Voltage SW Leakage Current Min 10 1.8 V mV V nA V V µs mΩ mΩ μA V 2 MP38115 – 4A, 5.5V SYNCHRONOUS STEP-DOWN SWITCHING REGULATOR ELECTRICAL CHARACTERISTICS (4) (continued) RE C N O RE E M W FE D ME R E N TO SI DE G D M NS F P2 O R 14 7 VIN = VEN = 3.6V, TA = +25°C, unless otherwise noted. Parameters High-Side Switch Current Limit Low-Side Switch Current Limit Oscillator Frequency Maximum Synch Frequency Minimum Synch Frequency Minimum On Time Maximum Duty Cycle Thermal Shutdown Threshold Condition Sourcing Sinking Min 1.2 Hysteresis = 20°C Typ 6.5 3.5 1.5 2 1 50 90 150 Max 1.8 Units A A MHz MHz MHz ns % °C Note: 4) Production test at +25°C. Specifications over the temperature range are guaranteed by design and characterization. PIN FUNCTIONS Pin # 6 4, 7 3, 8 2, 9 5 1 Description Bias Supply. This supplies power to both the internal control circuit and the gate drivers. A VCC decoupling capacitor to ground is required close to this pin. Input Supply. A decoupling capacitor to ground is required close to these pins to reduce IN switching spikes. Switch Node Connection to the Inductor. These pins connect to the internal high and lowSW side power MOSFET switches. All SW pins must be connected together externally. Ground. Connect these pins with larger copper areas to the negative terminals of the input GND and output capacitors. Bootstrap. A capacitor between this pin and SW provides a floating supply for the high-side BS gate driver. Feedback. This is the input to the error amplifier. An external resistive divider connects this FB pin between the output and GND. The voltage on the FB pin compares to the internal 0.8V reference to set the regulation voltage. Enable and Frequency Synchronization Input Pin. Forcing this pin below 0.4V shuts down EN/SYNC the part. Forcing this pin above 1.6V turns on the part. Applying a 1MHz to 2MHz clock signal to this pin synchronizes the internal oscillator frequency to the external clock. NO T 10 Name MP38115 Rev. 0.92 8/11/2009 www.MonolithicPower.com MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited. © 2009 MPS. All Rights Reserved. 3 MP38115 – 4A, 5.5V SYNCHRONOUS STEP-DOWN SWITCHING REGULATOR RE C N O RE E M W FE D ME R E N TO SI DE G D M NS F P2 O R 14 7 FUNCTIONAL BLOCK DIAGRAM VCC UVLO IN EN EN/SYNC LOGIC EN EXCLK LOGIC CLK OSC BS + -- EN/SYNC IN PWM CURRENT COMPARATOR SLOPE SW SW 0.5pF 1.2 MEG 17pF FB 0.8V -+ + COMP SLOPE COMPENSATION AND PEAK CURRENT LIMIT GND Figure 1—Functional Block Diagram (MP38115) NO T SOFT -START GND MP38115 Rev. 0.92 8/11/2009 www.MonolithicPower.com MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited. © 2009 MPS. All Rights Reserved. 4 MP38115 – 4A, 5.5V SYNCHRONOUS STEP-DOWN SWITCHING REGULATOR FUNCTIONAL DESCRIPTION RE C N O RE E M W FE D ME R E N TO SI DE G D M NS F P2 O R 14 7 PWM Control The MP38115 is a constant frequency peakcurrent-mode control PWM switching regulator. Refer to the functional block diagram. The high side N-Channel DMOS power switch turns on at the beginning of each clock cycle. The current in the inductor increases until the PWM current comparator trips to turn off the high side DMOS switch. The peak inductor current at which the current comparator shuts off the high side power switch is controlled by the COMP voltage at the output of feedback error amplifier. The transconductance from the COMP voltage to the output current is set at 11.25A/V. exceeds the reference voltage of 0.8V. At this point the reference voltage takes over at the noninverting error amplifier input. The soft-start time is internally set at 120µs. If the output of the MP38115 is pre-biased to a certain voltage during startup, the IC will disable the switching of both high-side and low-side switches until the voltage on the internal soft-start capacitor exceeds the sensed output voltage at the FB pin. This current-mode control greatly simplifies the feedback compensation design by approximating the switching converter as a single-pole system. Only Type II compensation network is needed, which is integrated into the MP38115. The loop bandwidth is adjusted by changing the upper resistor value of the resistor divider at the FB pin. The internal compensation in the MP38115 simplifies the compensation design, minimizes external component counts, and keeps the flexibility of external compensation for optimal stability and transient response. Bootstrap (BST PIN) The gate driver for the high-side N-channel DMOS power switch is supplied by a bootstrap capacitor connected between the BS and SW pins. When the low-side switch is on, the capacitor is charged through an internal boost diode. When the high-side switch is off and the low-side switch turns on, the voltage on the bootstrap capacitor is boosted above the input voltage and the internal bootstrap diode prevents the capacitor from discharging. NO T Enable and Frequency Synchronization (EN/SYNC PIN) This is a dual function input pin. Forcing this pin below 0.4V for longer than 4us shuts down the part; forcing this pin above 1.6V for longer than 4µs turns on the part. Applying a 1MHz to 2MHz clock signal to this pin also synchronizes the internal oscillator frequency to the external clock. When the external clock is used, the part turns on after detecting the first few clocks regardless of duty cycles. If any ON or OFF period of the clock is longer than 4µs, the signal will be intercepted as an enable input and disables the synchronization. Over Current Protection The MP38115 offers cycle-to-cycle current limiting for both high-side and low-side switches. The highside current limit is relatively constant regardless of duty cycles. When the output is shorted to ground, causing the output voltage to drop below 70% of its nominal output, the IC is shut down momentarily and begins discharging the soft start capacitor. It will restart with a full soft-start when the soft- start capacitor is fully discharged. This hiccup process is repeated until the fault is removed. Soft-Start and Output Pre-Bias Startup When the soft-start period starts, an internal current source begins charging an internal soft-start capacitor. During soft-start, the voltage on the softstart capacitor is connected to the non-inverting input of the error amplifier. The soft-start period lasts until the voltage on the soft-start capacitor MP38115 Rev. 0.92 8/11/2009 www.MonolithicPower.com MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited. © 2009 MPS. All Rights Reserved. 5 MP38115 – 4A, 5.5V SYNCHRONOUS STEP-DOWN SWITCHING REGULATOR APPLICATION INFORMATION where ∆IL is Inductor Ripple Current. Choose inductor ripple current approximately 30% of the maximum load current, 4A. The maximum inductor peak current is: RE C N O RE E M W FE D ME R E N TO SI DE G D M NS F P2 O R 14 7 Output Voltage Setting The external resistor divider sets the output voltage (see Page 1, Schematic Diagram). The feedback resistor R1 also sets the feedback loop bandwidth with the internal compensation (refer to description function). The relation between R1 and feedback loop bandwidth (fC), output capacitance (CO) is as follows: 1.24 × 10 6 R1(KΩ) = fc(KHz ) × C O (μF) The feedback loop bandwidth (fC) is no higher than 1/10th of switching frequency of MP2107. In the case of ceramic capacitor as CO, it is usually set in the range of 50KHz and 150KHz for optimal transient performance and good phase margin. If an electrolytic capacitor is used, the loop bandwidth is no higher than 1/4 of the ESR zero frequency (fESR). fESR is given by: 1 fESR = 2π × RESR × CO For example, choose fC=70KHz with a ceramic capacitor, CO=47μF, R1 is estimated to be 400KΩ. R2 is then given by: R2 = R1 VOUT -1 0.8V Table 1—Resistor Selection vs. Output Voltage Setting R1 R2 L Cout (Ceramic) 1.2V 1.5V 1.8V 2.5V 400kΩ 400kΩ 400kΩ 400kΩ 806kΩ 453kΩ 316kΩ 187kΩ 0.47μH-1μH 0.47μH-1μH 0.47μH-1μH 0.47μH-1μH 47μF 47μF 47μF 47μF 127kΩ 0.47μH-1μH 47μF T Vout 3.3V 400kΩ NO Inductor Selection A 0.47µH to 1µH inductor with DC current rating at least 25% higher than the maximum load current is recommended for most applications. For best efficiency, the inductor DC resistance shall be