MP6539
100V, Three-Phase, BLDC Motor
Pre-Driver with HS & LS Inputs
DESCRIPTION
FEATURES
The MP6539 is a gate driver IC designed for
three-phase, brushless DC motor driver
applications. The MP6539 is capable of driving
three half-bridges consisting of six N-channel
power MOSFETs up to 100V.
The MP6539 uses a bootstrap capacitor to
generate a supply voltage for the high-side
MOSFET driver. An internal charge pump
maintains the high-side gate driver if the output
is held high for an extended period of time.
Full protection features include programmable
over-current protection (OCP), adjustable deadtime control, under-voltage lockout (UVLO), and
thermal shutdown.
The MP6539 is available in TSSOP-28
(9.7mmx6.4mm) and QFN-28 (4mmx5mm)
packages with an exposed thermal pad.
Supports 100V Operation
120V VBST Maximum Voltage
Internal LDO Supports External NPN for
High-Current Drive Requirements
Integrated Current-Sense Amplifier
Low-Power Sleep Mode for BatteryPowered Applications
Programmable Over-Current Protection
(OCP) for External MOSFETs
Adjustable Dead-Time Control to Prevent
Shoot-Through
Thermal Shutdown and Under-Voltage
Lockout (UVLO) Protection
Fault Indication Output
Available in Thermally Enhanced SurfaceMounted TSSOP and QFN Packages
APPLICATIONS
Three-Phase Brushless DC Motors and
Permanent Magnet Synchronous Motors
Power Drills
E-Bikes
All MPS parts are lead-free, halogen-free, and adhere to the RoHS directive. For
MPS green status, please visit the MPS website under Quality Assurance. “MPS”
and “The Future of Analog IC Technology” are registered trademarks of
Monolithic Power Systems, Inc.
TYPICAL APPLICATION
VIN
LDO
VIN
VDD
BSTA
nFAULT
HSA
MP6539
HSB
HSC
LSA
LSB
GHA
SHA
Exposed GND
PAD
GLA
LSC
nSLEEP
LSS
OCREF
CSO
DT
MP6539 Rev. 1.01
4/20/2018
GND
Phase A
(repeat for B and C)
To Phase B
To Phase C
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2018 MPS. All Rights Reserved.
1
MP6539 – 100V, THREE-PHASE, BLDC MOTOR PRE-DRIVER WITH HS & LS INPUTS
ORDERING INFORMATION
Part Number
MP6539GV*
MP6539GF**
Package
QFN-28 (4mm x 5mm)
TSSOP-28 EP
Top Marking
See Below
See Below
* For Tape & Reel, add suffix –Z (e.g.: MP6539GV–Z)
** For Tape & Reel, add suffix –Z (e.g.: MP6539GF–Z)
TOP MARKING (MP6539GV)
MPS: MPS prefix
Y: Year code
WW: Week code
MP6539: Part number
LLLLLL: Lot number
TOP MARKING (MP6539GF)
MPS: MPS prefix
YY: Year code
WW: Week code
MP6539: Part number
LLLLLLLLL: Lot number
MP6539 Rev. 1.01
4/20/2018
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2018 MPS. All Rights Reserved.
2
MP6539 – 100V, THREE-PHASE, BLDC MOTOR PRE-DRIVER WITH HS & LS INPUTS
PACKAGE REFERENCE
23 HSB
TOP VIEW
24 HSA
25 nFAULT
nSLEEP
26
OCREF
27
28
DT
TOP VIEW
LSC
1
28
LSS
LSB
2
27
GLC
LSA
3
26
GHC
GND
1
22
HSC
HSC
4
25
SHC
VIN
2
21
LSA
HSB
5
24
BSTC
HSA
6
23
GLB
nFAULT
7
22
GHB
nSLEEP
8
21
SHB
OCREF
9
20
BSTB
CSO
LDO
3
20
4
19
MP6539
LSB
LSC
MP6539
SHA
7
16
GHC
GHA
GHA
8
15
SHC
EXPOSED PAD ON
BACKSIDE
CONNECTED TO GND
14
GLA
18
BSTC
19
11
13
10
GLB
DT
GND
12
GLC
GHB
17
11
6
SHB
BSTA
10
LSS
BSTB
18
9
5
GLA
VREG
VIN
12
17
SHA
CSO
13
16
BSTA
LDO
14
15
VREG
EXPOSED PAD ON
BACKSIDE
CONNECTED TO GND
QFN-28 (4mmx5mm)
TSSOP-28 EP
ABSOLUTE MAXIMUM RATINGS (1)
Thermal Resistance
Input voltage (VIN) ........................ -0.3V to 110V
Input voltage VREG, GLA/B/C .... -0.3V to 14.5V
LDO ............................................ -0.3V to 14.5V
BSTA/B/C .................................... -0.3V to 120V
GHA/B/C .................... -0.3V to (BST-SH) + 0.3V
GHA/B/C (transient, 2µs) ..................................
..................................... -8V to (BST-SH) + 0.3V
LSS.................................................. -0.3V to 4V
LSS (transient, 2µs) ............................ -1V to 4V
SHA/B/C ......................................... -5V to 110V
SHA/B/C (transient, 2µs)................. -8V to 110V
All other pins to GND .................... -0.3V to 6.5V
(2)
Continuous power dissipation (TA = +25°C)
QFN-28 (4mmx5mm) .................................3.1W
TSSOP-28 EP (9.7mmx6.4mm) .................3.9W
Storage temperature ................ -55°C to +150°C
Junction temperature ............................. +150°C
Lead temperature (solder) ..................... +260°C
QFN-28 (4mmx5mm) ............ 40 ........ 9 .... °C/W
TSSOP-28 EP ....................... 32 ........ 6 .... °C/W
Recommended Operating Conditions
(4)
θJA
θJC
NOTES:
1) Exceeding these ratings may damage the device.
2) The maximum allowable power dissipation is a function of the
maximum junction temperature TJ (MAX), the junction-toambient thermal resistance θJA, and the ambient temperature
TA. The maximum allowable continuous power dissipation at
any ambient temperature is calculated by PD (MAX) = (TJ
(MAX)-TA)/θJA. Exceeding the maximum allowable power
dissipation produces an excessive die temperature, causing
the regulator to go into thermal shutdown. Internal thermal
shutdown circuitry protects the device from permanent
damage.
3) The device is not guaranteed to function outside of its
operating conditions.
4) Measured on JESD51-7, 4-layer PCB.
(3)
Input voltage (VIN) .......................... +8V to 100V
Input voltage (VREG) ...................... +8.5V to 14V
OCREF voltage (VOC) ................ 0.125V to 2.4V
Operating junction temp. (TJ) ... -40°C to +125°C
MP6539 Rev. 1.01
4/20/2018
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2018 MPS. All Rights Reserved.
3
MP6539 – 100V, THREE PHASE BLDC MOTOR PRE-DRIVER WITH HS & LS INPUTS
ELECTRICAL CHARACTERISTICS
VIN = 48V, VREG = 12V, TA = 25°C, unless otherwise noted.
Parameter
Power Supply
Input supply voltage
LDO output voltage
Gate driver supply voltage
Quiescent current
Control Logic
Input logic low threshold
Input logic high threshold
Logic input current
Symbol
VIN
VLDO
VREG
IQ
ISLEEP
OCP deglitch time
Sleep wake-up time
Thermal shutdown
Thermal shutdown hysteresis
Gate Drive
Bootstrap diode forward
voltage
Maximum source current
Maximum sink current
Gate drive pull-up resistance
HS gate drive pull-down
resistance
LS gate drive pull-down
resistance
LS automatic turn-on time
Dead time
Min
ILDO ≤ 5mA, VIN > 15V
8
10.8
8.5
nSLEEP = 1, not switching
nSLEEP = 0
VIL
VIH
IIN(H)
IIN(L)
VIH = 0.8V
VIL = 5V
VOC
VFBOOT
Max
Units
12
100
13.2
14
V
V
V
mA
µA
0.7
1
2
-2.4
-14
2.4
14
V
V
µA
µA
kΩ
kΩ
0.1
1
V
µA
8.5
7.6
V
V
mV
V
V
mV
V
V
V
µs
ms
°C
°C
450
450
IO = 5mA
VO = 3.3V
6.5
6
3.6
3.4
Voltage between SHx and BSTx
VOC = 1V
VOC = 2.4V
0.8
2.18
tOC
tSLEEP
(5)
TTSD
TTSD_HYS
Typ
0.8
RSLEEP-PD
nSLEEP pull-down resistance
RPD
Internal pull down resistance
Fault Output (Open-Drain Output)
VOL
Output low voltage
IOH
Output high leakage current
Protection Circuit
VREG_RUVLO
VREG UVLO rising threshold
VREG_FUVLO
VREG UVLO falling threshold
VREG_HYS
VREG UVLO hysteresis
VVIN_RUVLO
VIN UVLO rising threshold
VVIN_FUVLO
VIN UVLO falling threshold
VVIN_HYS
VIN UVLO hysteresis
V
VBST UVLO threshold
BST_UVLO
OCREF threshold
Condition
(5)
7.5
6.8
610
4
3.8
100
4
1
2.4
2.7
2
175
20
ID = 10mA
ID = 50mA
(5)
4.4
4.3
1.2
2.62
1.2
2.3
V
V
A
A
Ω
DSO
(5)
DSI
RUP
VDS = 1V
RHS-DN
VDS = 1V
0.6
4.5
Ω
RLS-DN
VDS = 1V
0.6
4.5
Ω
tLS
tDEAD
RDT = 10kΩ
RDT = 100kΩ
DT tied to GND
0.8
1
7
4.6
560
4.5
77
µs
ns
µs
ns
NOTE:
5) Guaranteed by design.
MP6539 Rev. 1.01
4/20/2018
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2018 MPS. All Rights Reserved.
4
MP6539 – 100V, THREE PHASE BLDC MOTOR PRE-DRIVER WITH HS & LS INPUTS
TYPICAL CHARACTERISTICS
VIN = 48V, unless otherwise noted.
0.8
0.78
0.76
0.74
0.72
0.7
0.68
0.66
0.64
0.62
0.6
VIN UVLO Falling Threshold vs.
Temperature
4.4
4.3
VIN UVLO FALLING
THRESHOLD (V)
IQ (mA)
Quiescent Current vs. Temperature
4.2
4.1
4
3.9
3.8
3.7
3.6
-50
-20
10
40
70
100
TEMPERATURE (°C )
-50
130
VREG Falling Threshold vs.
Temperature
VBST UVLO THRESHOLD (V)
VREG FALLING THRESHOLD
(V)
-20
10
40
70
100
TEMPERATURE(°C )
130
130
4
3.8
3.6
3.4
3.2
3
2.8
2.6
2.4
2.2
2
1.8
-50
OCREF Threshold vs. Temperature
3.52
2.425
3.51
OCP CSO RISING
THRESHOLD (V)
2.43
2.42
2.415
2.41
2.405
2.4
-20
10
40
70
100
TEMPERATURE(°C )
130
OCP CSO Rising Threshold vs.
Temperature
OCREF = 2.4V
OC_REF THRESHOLD (V)
10
40
70
100
TEMPERATURE(°C )
VBST UVLO Threshold vs. Temperature
6.9
6.88
6.86
6.84
6.82
6.8
6.78
6.76
6.74
6.72
6.7
-50
-20
3.5
3.49
3.48
3.47
3.46
2.395
2.39
3.45
-50
MP6539 Rev. 1.01
4/20/2018
-20
10
40
70
100
TEMPERATURE(°C )
130
-50
-20
10
40
70
100
130
TEMPERATURE°C )
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2018 MPS. All Rights Reserved.
5
MP6539 – 100V, THREE PHASE BLDC MOTOR PRE-DRIVER WITH HS & LS INPUTS
TYPICAL CHARACTERISTICS (continued)
VIN = 48V, unless otherwise noted.
OCP CSO Falling Threshold vs.
Temperature
3.05
OCP CSO FALLING
THRESHOLD (V)
3.045
3.04
3.035
3.03
3.025
3.02
3.015
3.01
-50
MP6539 Rev. 1.01
4/20/2018
-20
10
40
70
TEMPERATURE(°C )
100
130
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2018 MPS. All Rights Reserved.
6
MP6539 – 100V, THREE PHASE BLDC MOTOR PRE-DRIVER WITH HS & LS INPUTS
TYPICAL PERFORMANCE CHARACTERISTICS
VIN = 48V, OCREF = 0.5V, RDT = 1kΩ, A phase switching, B phase LS on, fPWMA = 30kHz, TA = 25°C,
resistor + inductor load: 5Ω + 1mH/phase with star connection, unless otherwise noted.
Steady State
Steady State
Duty = 10%
Duty = 50%
CH1: SHA
50V/div.
CH1: SHA
50V/div.
CH2: GHA
50V/div.
CH2: GHA
50V/div.
CH3: GLA
10V/div.
CH3: GLA
10V/div.
CH4: IOUTA
200mA/div.
CH4: IOUTA
1A/div.
10µs/div.
10µs/div.
Steady State
Power Ramp-Up
Duty = 90%
Duty = 10%
CH1: SHA
50V/div.
CH1: SHA
50V/div.
CH2: GHA
50V/div.
CH2: GHA
50V/div.
CH3: GLA
10V/div.
CH3: VIN
20V/div.
CH4: IOUTA
2A/div.
CH4: IOUTA
200mA/div.
10µs/div.
400µs/div.
Power Ramp-Up
Power Ramp-Up
Duty = 50%
Duty = 90%
CH1: SHA
50V/div.
CH1: SHA
50V/div.
CH2: GHA
50V/div.
CH2: GHA
50V/div.
CH3: VIN
20V/div.
CH3: VIN
20V/div.
CH4: IOUTA
2A/div.
CH4: IOUTA
1A/div.
400µs/div.
MP6539 Rev. 1.01
4/20/2018
400µs/div.
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2018 MPS. All Rights Reserved.
7
MP6539 – 100V, THREE PHASE BLDC MOTOR PRE-DRIVER WITH HS & LS INPUTS
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
VIN = 48V, OCREF = 0.5V, RDT = 1kΩ, A phase switching, B phase LS on, fPWMA = 30kHz, TA = 25°C,
resistor + inductor load: 5Ω + 1mH/phase with star connection, unless otherwise noted.
Sleep Recovery
Sleep Recovery
Duty = 10%
Duty = 50%
CH1: SHA
50V/div.
CH1: SHA
50V/div.
CH2: GHA
50V/div.
CH2: GHA
50V/div.
CH3:
CH3:
nSLEEP
2V/div.
nSLEEP
2V/div.
CH4: IOUTA
1A/div.
CH4: IOUTA
200mA/div.
1ms/div.
1ms/div.
Sleep Recovery
Sleep Entry
Duty = 90%
Duty = 10%
CH1: SHA
50V/div.
CH1: SHA
50V/div.
CH2: GHA
50V/div.
CH2: GHA
50V/div.
CH3:
CH3:
nSLEEP
2V/div.
nSLEEP
2V/div.
CH4: IOUTA
200mA/div.
CH4: IOUTA
2A/div.
1ms/div.
200µs/div.
Sleep Entry
Sleep Entry
Duty = 50%
Duty = 90%
CH1: SHA
50V/div.
CH1: SHA
50V/div.
CH2: GHA
50V/div.
CH2: GHA
50V/div.
CH3:
CH3:
nSLEEP
2V/div.
nSLEEP
2V/div.
CH4: IOUTA
1A/div.
CH4: IOUTA
2A/div.
200µs/div.
MP6539 Rev. 1.01
4/20/2018
200µs/div.
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2018 MPS. All Rights Reserved.
8
MP6539 – 100V, THREE PHASE BLDC MOTOR PRE-DRIVER WITH HS & LS INPUTS
PIN FUNCTIONS
QFN-28
Pin #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
TSSOP
Pin #
Name
Description
25
26
27
28
1
2
3
4
5
6
GND
VIN
CSO
LDO
VREG
BSTA
SHA
GHA
GLA
BSTB
SHB
GHB
GLB
BSTC
SHC
GHC
GLC
LSS
LSC
LSB
LSA
HSC
HSB
HSA
25
7
nFAULT
26
8
nSLEEP
27
28
9
OCREF
DT
Ground.
Input supply voltage.
Current sense output and OCP off time adjust.
Gate drive LDO output/base drive for external NPN transistor.
Gate driver supply voltage.
Bootstrap output phase A.
High-side source connection phase A.
High-side gate drive phase A.
Low-side gate drive phase A.
Bootstrap output phase B.
High-side source connection phase B.
High-side gate drive phase B.
Low-side gate drive phase B.
Bootstrap output phase C.
High-side source connection phase C.
High-side gate drive phase C.
Low-side gate drive phase C.
Low-side source connection.
Phase C low-side input pin.
Phase B low-side input pin.
Phase A low-side input pin.
Phase C high-side input pin.
Phase B high-side input pin.
Phase A high-side input pin.
Fault indication. nFAULT is an open-drain output type. nFAULT is logic
low when in a fault condition.
Sleep mode input. Drive nSLEEP to logic low to operate the device in a
low-power sleep mode. Float nSLEEP to enable the device.
Over-current protection reference input.
Dead time setting.
MP6539 Rev. 1.01
4/20/2018
11
12
13
14
15
16
17
18
19
20
21
22
23
24
10
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2018 MPS. All Rights Reserved.
9
MP6539 – 100V, THREE PHASE BLDC MOTOR PRE-DRIVER WITH HS & LS INPUTS
BLOCK DIAGRAM
VDD
Charge
Pump
nSLEEP
BSTA
HSA
HSB
HSC
LSA
LSB
LSC
HS Gate
Drive
Timing and
Control
Logic
GHA
VREG
GLA
LS Gate
Drive
6V
VDS
Comparator
LSS
VDS
Sense
RDT
OCREF
RSENSE
CSO
RCSO
GND
3.5V
nFAULT
VIN
SHA
DT
CCSO
Phase A,
repeat for
B&C
Fault
Handling
TSD
R
19R
UVLO
Comparator
VDD
VREG
REF
VIN
VIN
VIN
LDO
Regulator
LDO
Figure 1: Functional Block Diagram
MP6539 Rev. 1.01
4/20/2018
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2018 MPS. All Rights Reserved.
10
MP6539 – 100V, THREE PHASE BLDC MOTOR PRE-DRIVER WITH HS & LS INPUTS
OPERATION
The MP6539 is a three-phase, BLDC motor
pre-driver that can drive three half-bridges with
a 0.8A source and 1A sink current capability.
The MP6539 supports operation up to 100V.
The MP6539 features a low-power sleep mode,
which disables the device and draws very low
supply current.
The MP6539 provides several flexible functions,
such as adjustable dead-time control and overcurrent protection (OCP), which allow the
device to cover a wide range of applications.
Power-Up Sequence
The power-up sequence is initiated by the
application of voltage to VIN and the voltage
present on VREG. Usually, VREG is supplied
by an internal LDO regulator connected to VIN,
but it is also possible to drive VREG from
another power source.
To initiate a power-up, VIN must be above
~4.5V, and VREG must be above the VREG
under-voltage lockout (UVLO) threshold of 7.4V.
If VREG is supplied by the internal LDO
regulator, this means that VIN must be at about
8V before the part starts to power up. After
VREG exceeds the VREG UVLO threshold, the
MP6539 sequentially turns on each low-side
MOSFET (LS-FET) in succession to charge the
bootstrap capacitors.
The power-up process takes between 1ms and
2ms, after which the MP6539 responds to logic
inputs and drives the outputs.
Input Logic
Driving nSLEEP low puts the device into a lowpower sleep state. In this state, all internal
circuits are disabled. All inputs are ignored
when nSLEEP is active low. When waking up
from sleep mode, approximately 1ms of time
must pass before issuing a pulse-width
modulation (PWM) command to allow the
internal circuitry time to stabilize.
HSx is used to control the gate driver for the
high-side MOSFET (HS-FET) of each phase.
LSx is used to control the gate driver for the LSFET. A positive dead time is enforced by the
device. If both HSx and LSx are driven high,
neither MOSFET is driven (see Table 1).
MP6539 Rev. 1.01
4/20/2018
Table 1: Input Logic Truth Table
LSx
H
H
L
L
HSx
H
L
H
L
SHx
High impedance
GND
VIN
High impedance
nFAULT
nFAULT reports to the system when a fault
condition occurs, such as over-current
protection
(OCP)
or
over-temperature
protection (OTP). nFAULT is an open-drain
output type and is driven low when a fault
condition occurs. If the fault condition is
released, nFAULT is pulled up to a high level by
an external pull-up resistor.
Current-Sense Amplifier
An integrated current-sense amplifier amplifies
the voltage on LSS (relative to GND) by a factor
of 20. This voltage is the output to CSO.
The current-sense amplifier only sources
current. An external capacitor of 1nF (minimum)
must be connected from CSO to ground for
stability.
During the PWM on time, current flowing
through the output MOSFETs also flows
through the shared low-side current sense
resistor, generating a voltage that is amplified
by the current-sense amplifier, which charges
the external capacitor on CSO. During the
PWM off time, current recirculates through the
LS-FETs and does not pass through the sense
resistor, so there is zero voltage across it.
During this time, the capacitor discharges
through the internal feedback resistor
(approximately 450kΩ) and also through any
external resistor to ground. Select an external
resistor and capacitor to provide a filter to hold
the value of the current through the PWM off
time. Any external resistor used should be 1kΩ
or larger.
Over-Current Protection (OCP) / Current
Regulation
The voltage across each LS-FET is monitored
by a comparator in the MP6539 to turn the
device off in the event of an over-current
condition. The over-current shutdown voltage
threshold level is programmable through
OCREF by applying an external reference
voltage with a DAC or resistor divider. When
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2018 MPS. All Rights Reserved.
11
MP6539 – 100V, THREE PHASE BLDC MOTOR PRE-DRIVER WITH HS & LS INPUTS
the VDS of the MOSFET exceeds OCREF,
CSO is pulled to ~6V internally. Whenever CSO
exceeds 3.5V, an OCP event is detected, and
all output MOSFETs are turned off. nFAULT is
driven active low.
Once the current through the LS-FETs and the
sense resistor stops, the CSO voltage is no
longer driven and starts to fall at a rate
determined by the external capacitor and
resistor. When the voltage falls below 2.9V, the
output MOSFETs are re-enabled, and nFAULT
is inactive.
The resulting off time is set by the value of the
external capacitor and the internal feedback
resistor in parallel with the external resistor (if
used).
The off time generated when CSO reaches
3.5V can be approximated with Equation (1):
tOFF (µs) = 0.2*R(kΩ)*C(nF)
(1)
The off time generated when VDS exceeds
OCREF is longer since CSO is pulled to 6V and
must decay to 2.9V for the outputs to be reenabled. This off time can be approximated with
Equation (2):
tOFF (µs) = 0.6*R(kΩ)*C(nF)
(2)
Where C is the capacitance from CSO to
ground, and R is the total resistance from CSO
to ground, comprised of the internal feedback
resistor (~450kΩ) in parallel with any external
resistor to ground.
This feature can be used for current regulation
to limit the stall/start-up current of a motor,
either by using an external current sense
resistor or (with lower accuracy) the RDS(ON) of
the LS-FET.
In addition to low-side current monitoring, a
circuit monitors the output and triggers a fault
condition of the output, driving it high, but it will
not rise above ~4.5V. This provides protection
against a short to ground, which would not be
detected by low-side current sensing. If this
occurs, the MP6539 enters a latched fault state
and disables all outputs. The MP6539 remains
latched off until it is reset by nSLEEP or UVLO.
Gate-Drive Voltage Regulator
To generate a voltage to drive the external
MOSFET gates, a linear regulator is integrated
into the MP6539.
If current over about 5mA is needed (to drive
the high gate charge MOSFETs at a high
switching frequency), an external NPN
transistor (and optionally also a resistor) must
be used to remove power dissipation from the
IC.
For low-current applications, LDO is connected
to VREG directly. For higher current
requirements, an NPN transistor is used (see
Figure 2).
VIN
optional
VIN
VIN
LDO
Regulator
LDO
VREG
Figure 2: High-Current Configuration of the LDO
If desired, an appropriate gate-drive supply
voltage can be supplied directly to VREG from
an external supply. In this case, connect only
the capacitor to LDO. VIN must still be
connected to the motor supply voltage.
OCP Deglitch Time
There is usually a current spike during the
switching transition due to the body diode’s
reverse-recovery current or the distributed
inductance or capacitance. This current spike
requires filtering to prevent it from erroneously
triggering OCP and shutting down the external
MOSFET. An internal, fixed, deglitch time (tOC)
(which is also the minimum on time for the
MOSFET) blanks the output of the VDS monitor
when the outputs are switched.
Charge Pump and Bootstrap
Normally, the high-side gate-drive
generated from bootstrap capacitors
between SHx and BSTx. The
capacitor is charged whenever the
turned on.
voltage is
connected
bootstrap
LS-FET is
If the output is held at a high state for a long
period of time, the bootstrap capacitor
MP6539 Rev. 1.01
4/20/2018
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2018 MPS. All Rights Reserved.
12
MP6539 – 100V, THREE PHASE BLDC MOTOR PRE-DRIVER WITH HS & LS INPUTS
discharges slowly. This eventually results in
gate driver loss for the HS-FET.
To prevent this, an internal charge pump
generates a voltage to maintain the bootstrap
capacitor charge.
The bootstrap voltage is monitored by an
under-voltage detection circuit. If any bootstrap
voltage falls below the VBST UVLO voltage, the
part initiates a new power-up sequence.
Dead-Time Adjustment
To prevent shoot-through in any phase of the
bridge, it is necessary to insert a dead time
(tDEAD) between a high- or low-side turn-off and
the next complementary turn-on event. The
dead time for all three phases is set by a single
dead-time resistor (RDT) between DT and
ground using Equation (3):
tDEAD(µs) = 0.044*R(kΩ) + 0.1
(3)
VREG and VIN UVLO Protection
If at any time the voltage on VREG falls below
the VREG UVLO threshold voltage, the outputs
are disabled, and the nFAULT signal is
asserted. Operation resumes with a bootstrap
refresh when VREG rises above the UVLO
threshold.
If the voltage on VIN falls below the VIN UVLO
threshold voltage, all circuitry in the device is
disabled, and the internal logic is reset.
nFAULT is not asserted. Operation resumes
when VREG rises above the UVLO threshold.
Thermal Shutdown
If the die temperature exceeds safe limits, the
MP6539 enters a latched fault state similar to
an OCP event, and nFAULT is driven low. Only
nSLEEP or UVLO can unlatch the device from
an OTP fault lockout.
If DT is tied to GND directly, an internal
minimum dead time of 30ns is applied. Leave
DT open to generate a 6µs dead time.
MP6539 Rev. 1.01
4/20/2018
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2018 MPS. All Rights Reserved.
13
MP6539 – 100V, THREE PHASE BLDC MOTOR PRE-DRIVER WITH HS & LS INPUTS
PACKAGE INFORMATION
QFN-28 (4mmx5mm)
MP6539 Rev. 1.01
4/20/2018
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2018 MPS. All Rights Reserved.
14
MP6539 – 100V, THREE PHASE BLDC MOTOR PRE-DRIVER WITH HS & LS INPUTS
PACKAGE INFORMATION (continued)
TSSOP-28 EP
NOTICE: The information in this document is subject to change without notice. Users should warrant and guarantee that third
party Intellectual Property rights are not infringed upon when integrating MPS products into any application. MPS will not
assume any legal responsibility for any said applications.
MP6539 Rev. 1.01
4/20/2018
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2018 MPS. All Rights Reserved.
15
工商网监
湘ICP备2023018690号
