MP8719
The Future of Analog IC Technology
26V, 12A, Low IQ, High-Current,
Synchronous Buck Converter
with ±1A LDO and Buffered Reference
DESCRIPTION
FEATURES
The MP8719 provides a complete power supply
with the highest power density for DDR3,
DDR3L, LPDDR3, and DDR4 memory. The
MP8719
integrates
a
high-frequency,
synchronous, rectified, step-down, switch-mode
converter (VDDQ) with a 1A sink/source LDO
(VTT) and buffered low-noise reference
(VTTREF).
The MP8719 operates at high efficiency over a
wide output current load range based on MPS’s
proprietary switching loss reduction technology
and internal low RDS(ON) power MOSFETs.
Adaptive constant-on-time (COT) control mode
provides fast transient response and eases loop
stabilization. The DC auto-tune loop provides
good load and line regulation.
The VTT LDO provides 1A of sink/source
current capability and requires only a 22μF
ceramic capacitor. The VTTREF tracks VDDQ/2
with excellent 1% accuracy.
Full protection features include over-current
(OC) limit, over-voltage protection (OVP),
under-voltage
protection
(UVP),
overtemperature warning (OTW), and thermal
shutdown.
The MP8719 requires a minimal number of
external components and is available in a QFN16 (3mmx3mm) package.
Wide 4.5V to 26V Operating Input Range
135μA Low Quiescent Current
12A Continous Output Current
13A Peak Output Current
Selectable Ultrasonic Mode (USM)
Selectable
500kHz/700kHz
Switching
Frequency
Built-In ±1A VTTLDO
1% Buffered VTTREF Output
Adaptive COT for Fast Transient
DC Auto-Tune Loop
Stable with POSCAP and Ceramic Output
Capacitors
Over-Temperature Warning (OTW)
Internal Soft Start (SS)
Output Discharge
OCL, OVP, UVP, and Thermal Shutdown
Latch-Off Reset via EN or Power Cycle
Available in a QFN-16 (3mmx3mm)
Package
APPLICATIONS
Televisions
Networking Systems
Distributed Power Systems
Set-Top-Box
All MPS parts are lead-free, halogen-free, and adhere to the RoHS
directive. For MPS green status, please visit the MPS website under
Quality Assurance. “MPS” and “The Future of Analog IC Technology” are
registered trademarks of Monolithic Power Systems, Inc.
TYPICAL APPLICATION
MP8719 Rev1.01
8/3/2017
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1
MP8719 – 26V, 12A, HIGH-CURRENT, SYNC BUCK CONVERTER WITH ±1A LDO
ORDERING INFORMATION
Part Number*
MP8719GQ
Package
QFN-16 (3mmx3mm)
Top Marking
See Below
* For Tape & Reel, add suffix –Z (e.g. MP8719GQ–Z)
TOP MARKING
AZF: Product code of MP8719GQ
Y: Year code
LLL: Lot number
PACKAGE REFERENCE
TOP VIEW
QFN-16 (3mmx3mm)
MP8719 Rev1.01
8/3/2017
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2
MP8719 – 26V, 12A, HIGH-CURRENT, SYNC BUCK CONVERTER WITH ±1A LDO
ABSOLUTE MAXIMUM RATINGS (1)
Thermal Resistance
Supply voltage (VIN) .................................... 26V
VSW (DC) .................................-1V to VIN + 0.3V
VSW (25ns)...............................-3.6V to VIN + 4V
VBST ................................................... VSW + 4.5V
IEN1, IEN2 .................................................... 100µA
All other pins ................................-0.3V to +4.5V
(2)
Continuous power dissipation (TA = +25°C)
QFN-16 (3mmx3mm) ................................. 2.3W
Junction temperature ................................150°C
Lead temperature .....................................260°C
Storage temperature ................ -65°C to +150°C
QFN-16 (3mmx3mm) ............. 55 ....... 13 ... °C/W
Recommended Operating Conditions
(3)
Supply voltage (VIN) ........................ 4.5V to 24V
Supply voltage (VCC) ..................... 3.15V to 3.5V
(4)
Output voltage (VDDQ)................. 0.6V to 3.3V
IEN1, IEN2 ...................................................... 50μA
Operating junction temp. (TJ) ... -40°C to +125°C
MP8719 Rev1.01
8/3/2017
(5)
θJA
θJC
NOTES:
1) Exceeding these ratings may damage the device.
2) The maximum allowable power dissipation is a function of the
maximum junction temperature TJ(MAX), the junction-toambient thermal resistance θJA, and the ambient temperature
TA. The maximum allowable continuous power dissipation at
any ambient temperature is calculated by PD(MAX)=(TJ(MAX)TA)/θJA. Exceeding the maximum allowable power dissipation
produces an excessive die temperature, causing the regulator
to go into thermal shutdown. Internal thermal shutdown
circuitry protects the device from permanent damage.
3) The device is not guaranteed to function outside of its
operating conditions.
4) For applications that need 3.3V < Vout < 5.5V, special design
requirements are needed. Please refer to the Application
Information section on page 16. VDDQ must be ≤3.3V.
5) Measured on JESD51-7, 4-layer PCB.
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3
MP8719 – 26V, 12A, HIGH-CURRENT, SYNC BUCK CONVERTER WITH ±1A LDO
ELECTRICAL CHARACTERISTICS
VIN = 12V, 3V3 = 3.3V, TJ = 25°C, RMODE = 0Ω, unless otherwise noted.
Parameters
Supply Current
3V3 supply current in normal
mode
Symbol
I3V3
3V3 supply current in S3 mode
I3V3_S3
3V3 shutdown current
I3V3
SDN
Condition
Min
VEN1 = VEN2 = 3V, no load
VEN1 = 0V, VEN2 = 3V,
no load
VEN1 = VEN2 = 0V, no load
Typ
Max
Units
185
µA
135
µA
1
µA
MOSFET
High-side switch on resistance
HSRDS-ON
TJ = 25°C
19.5
mΩ
Low-side switch on resistance
LSRDS-ON
TJ = 25°C
6.6
mΩ
Switch leakage
SWLKG
VEN = 0V, VSW = 0V
Current Limit
Low-side valley current limit
ILIMIT
Switching Frequency and Minimum Off Time
RMODE = 0Ω
Switching frequency
FS
RMODE = 150kΩ
VIN = 6V, VOUT = 3V,
Constant on timer
TON
RMODE = 150kΩ
(6)
Minimum on time
TON MIN
Minimum off time (6)
TOFF MIN
Ultrasonic Mode (USM)
Ultrasonic mode operation period
TUSM
VFB = 0.62V
Protection
OVP threshold
VOVP
UVP-1 threshold
VUVP-1
(6)
UVP-1 foldback timer
TUVP-1
UVP-2 threshold
VUVP-2
Reference and Soft Start, Soft Stop
Reference voltage
VREF
Feedback current
IFB
VFB = 0.62V
Soft-start time
TSStart
EN to PG up
Soft-stop time
TSStop
Enable (EN) and Under-Voltage Lockout (UVLO)
EN1 rising threshold
VEN1 TH
EN1 hysteresis
VEN1-HYS
EN2 rising threshold
VEN2 TH
EN2 hysteresis
VEN2-HYS
VEN1/2 = 2V
Enable input current
IEN1/2
VEN1/2 = 0V
MP8719 Rev1.01
8/3/2017
12
0
1
μA
13
14
A
700
500
1100
125
70%
45%
594
1.8
0.54
1.12
1200
kHz
kHz
1300
ns
70
300
ns
ns
32
µs
130
75%
30
50%
135
80%
600
10
2.2
2
606
50
2.6
mV
nA
ms
ms
0.59
125
1.22
125
0.64
V
mV
V
mV
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55%
1.32
5
1
%VREF
VREF
µs
VREF
μA
4
MP8719 – 26V, 12A, HIGH-CURRENT, SYNC BUCK CONVERTER WITH ±1A LDO
ELECTRICAL CHARACTERISTICS (continued)
VIN = 12V, 3V3 = 3.3V, TJ = 25°C, RMODE = 0Ω, unless otherwise noted.
Parameters
Symbol
VCC UVLO threshold rising
VCC UVLO threshold
hysteresis
VIN UVLO threshold rising
VIN UVLO threshold
hysteresis
Power Good (PG)
PG when FB rising (good)
PG when FB falling (fault)
PG when FB rising (fault)
PG when FB falling (good)
PG low to high delay
EN low to PG low delay
PG sink current capability
VCCVth
Condition
Min
Typ
Max
Units
2.9
3.0
3.1
V
VCCHYS
220
VINVTH
4.2
VINHYS
360
PG Rising(GOOD)
PG Falling(Fault)
PG Rising(Fault)
PG Falling(GOOD)
PGTd
PGTd EN low
VPG
VFB rising, percentage of VFB
VFB falling, percentage of VFB
VFB rising, percentage of VFB
VFB falling, percentage of VFB
mV
4.4
mV
95
90
115
105
3
%
1
0.4
Sink 4mA
V
μs
μs
V
VTTREF Output
VTTREF output voltage
Output voltage tolerance to
VDDQ
Current limit
VTT LDO
VTT output voltage
VTT tolerance to VTTREF
Source current limit
Sink current limit
OTW
Over-temperature warning (6)
OTW hysteresis (6)
OTW sink current capability
OTW leakage current
OTW assertion time (6)
Thermal Protection
Thermal shutdown (6)
Thermal shutdown
hysteresis
VTTREF
VTTREF/ VDDQ
ILIMIT
VDDQ/2
IVTTREF < 0.1mA, 1V < VDDQ <
1.5V
IVTTREF < 10mA, 1V < VDDQ <
1.5V
VTTREF
49.2%
50%
50.8%
49%
50%
51%
13
15
VTT
VTT-VTTREF
mA
VDDQ/2
-10mA < IVTT < 10mA, VDDQ =
[1V - 1.5V]
-0.6A < IVTT < 0.6A, VDDQ = [1V
- 1.5V]
-1A < IVTT < 1A, VDDQ = [1V 1.5V]
ILIMIT SOURCE
ILIMIT SINK
-15
15
mV
-20
20
mV
-25
25
mV
1.2
1.2
1.5
1.5
A
A
130
25
32
°C
°C
V
μA
ms
TSD
145
°C
TSD_HYS
25
°C
TOTW
TOTW HYS
VOTW
IOTW
TOTW
Sink 4mA
VOTW = 3.3V
0.4
1
NOTE:
6) Guaranteed by design.
MP8719 Rev1.01
8/3/2017
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5
MP8719 – 26V, 12A, HIGH-CURRENT, SYNC BUCK CONVERTER WITH ±1A LDO
PIN FUNCTIONS
PIN #
Name
1
VIN
2
PGND
3
3V3
4
AGND
5
VTT
6
VDDQ
7
VTTREF
8
VTTS
9
SW
10
BST
11
OTW
12
PG
13
FB
14
MODE
15
EN2
16
EN1
MP8719 Rev1.01
8/3/2017
Description
Supply voltage. VIN supplies power for the internal MOSFET and regulators. The
MP8719 operates from a +4.5V to +26V input rail. An input capacitor is needed to
decouple the input rail. Use wide PCB traces and multiple vias to make the connection.
Power ground. Use wide PCB traces and multiple vias to make the connection.
External 3V3 VCC input for control and driver. Place a 1µF decoupling capacitor
close to 3V3 and AGND. It is recommended to form an R-C filter.
Analog ground. The internal reference is referred to AGND. Connect GND of the FB
divider resistor to AGND for better load regulation.
VTT LDO output. Decouple with a minimum 22µF ceramic capacitor as close to VTT
as possible. X7R or X5R grade dielectric ceramic capacitors are recommended for
their stable temperature characteristics.
Input of VTTLDO. VDDQ is also used for VOUT sense. Do not float VDDQ at any time.
Connect VDDQ to the output capacitor of the regulator directly with a thick (>100mil)
trace.
Buffered VTT reference output. Decouple VTTREF with a minimum 0.22µF ceramic
capacitor as close to it as possible. X7R or X5R grade dielectric ceramic capacitors are
recommended for their stable temperature characteristics.
VTT output sense. Connect VTTS to the output capacitor of the VTT regulator directly.
Switch output. Connect SW to the inductor and bootstrap capacitor. SW is connected
to VIN when the HS-FET is on. SW is connected to PGND when the LS-FET is on. Use
wide and short PCB traces to make the connection. SW is noisy, so keep sensitive
traces away from SW.
Bootstrap. A capacitor connected between SW and BST is required to form a floating
supply across the high-side switch driver.
Over-temperature status. OTW is used to indicate that the MP8719 is close to OTP.
OTW is pulled low once the junction temperature is higher than the over-temperature
warning threshold. OTW can be left open if not used.
Power good output. PG is an open-drain signal. PG is high if the output voltage is
within a proper range.
Feedback. An external resistor divider from the output to GND (tapped to FB) sets the
output voltage. Place the resistor divider as close to FB as possible. Avoid vias on the
FB traces.
Switching frequency and ultrasonic mode selection. A 1% pull-down resistor is
needed on MODE.
Enable. EN1 and EN2 are digital inputs which are used to enable or disable the
internal regulators. Once EN1 = EN2 = 1, the VDDQ regulator, VTT LDO, and VTTREF
output are turned on. When EN1 = 0 and EN2 = 1, all the regulators are on except VTT
LDO. All regulators are turned off when EN2 = 0 or EN1 = EN2 = 0. Do not float EN1 at
any time. If the VTT LDO function is not used, tie EN1 to GND.
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MP8719 – 26V, 12A, HIGH-CURRENT, SYNC BUCK CONVERTER WITH ±1A LDO
TYPICAL PERFORMANCE CHARACTERISTICS
VIN = 20V, VDDQ = 1.35V, L = 0.68µH/3.1mΩ, FSW = 700kHz, unless otherwise noted.
MP8719 Rev1.01
8/3/2017
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MP8719 – 26V, 12A, HIGH-CURRENT, SYNC BUCK CONVERTER WITH ±1A LDO
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
VIN = 20V, VDDQ = 1.35V, L = 0.68µH/3.1mΩ, FSW = 700kHz, unless otherwise noted.
VDDQ/AC
20mV/div.
VDDQ/AC
20mV/div.
VDDQ
1V/div.
VSW
20V/div.
VSW
20V/div.
VEN2
2V/div.
VPG
2V/div.
IL
2A/div.
IL
10A/div.
IL
2A/div.
VDDQ
1V/div.
VDDQ
1V/div.
VDDQ
1V/div.
VEN2
2V/div.
VPG
2V/div.
VEN2
2V/div.
VEN2
2V/div.
VPG
2V/div.
IL
10A/div.
VPG
2V/div.
IL
5A/div.
VDDQ
1V/div.
VDDQ
1V/div.
VDDQ
1V/div.
VTT
500mV/div.
VTT
500mV/div.
VTT
500mV/div.
VTTREF
500mV/div.
VTTREF
500mV/div.
VTTREF
500mV/div.
VEN2
5V/div.
VEN2
5V/div.
VEN2
5V/div.
MP8719 Rev1.01
8/3/2017
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MP8719 – 26V, 12A, HIGH-CURRENT, SYNC BUCK CONVERTER WITH ±1A LDO
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
VIN = 20V, VDDQ = 1.35V, L = 0.68µH/3.1mΩ, FSW = 700kHz, unless otherwise noted.
VDDQ
1V/div.
VTT
500mV/div.
VDDQ
1V/div.
VTT
500mV/div.
VVREF
500mV/div.
VEN2
5V/div.
VVREF
500mV/div.
VEN1
2V/div.
VVREF
500mV/div.
VEN1
2V/div.
VDDQ
1V/div.
VTT
500mV/div.
VDDQ
1V/div.
VTT
500mV/div.
VDDQ/AC
50mV/div.
VDDQ
1V/div.
VTT
500mV/div.
VSW
20V/div.
VVREF
500mV/div.
VEN1
2V/div.
VVREF
500mV/div.
VEN1
2V/div.
IL
5A/div.
VDDQ
1V/div.
VDDQ
1V/div.
VDDQ
1V/div.
VSW
20V/div.
VSW
20V/div.
VSW
20V/div.
IL
10A/div.
IL
10A/div.
IL
10A/div.
MP8719 Rev1.01
8/3/2017
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MP8719 – 26V, 12A, HIGH-CURRENT, SYNC BUCK CONVERTER WITH ±1A LDO
BLOCK DIAGRAM
AGND
MODE
3V3
OTW
EN2
EN1
VIN
BST
BSTREG
3V3
VIN
POR &
Reference
Soft Start
FB
FB
On Time
One Shot
REF
Min off time
Control
Logic
SW
VDDQ
DC Error
Correction
+
+
Output
Discharge
PGND
Vref
SW
OC Limit
130% Vref
OVP
PG
FB
95% Vref
POK
50% Vref
UVP-2
75% Vref
UVP-1
Fault
Logic
VDDQ
EN1/EN2
Control
VTTREF
VTT
VTTS
Figure 1: Functional Block Diagram
MP8719 Rev1.01
8/3/2017
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10
MP8719 – 26V, 12A, HIGH-CURRENT, SYNC BUCK CONVERTER WITH ±1A LDO
PRELIMINARY SPECIFICATIONS SUBJECT TO CHANGE
OPERATION
Pulse-Width Modulation (PWM) Operation
The MP8719 is a fully integrated, synchronous,
rectified, step-down, switch-mode converter
with ±1A of LDO current. Constant-on-time
(COT) control provides fast transient response
and eases loop stabilization. At the beginning of
each cycle, the high-side MOSFET (HS-FET) is
turned on when the feedback voltage (VFB) is
below the reference voltage (VREF), which
indicates an insufficient output voltage. The on
period is determined by both the output voltage
and the input voltage to make the switching
frequency fairly constant over the input voltage
range.
After the on period elapses, the HS-FET is
turned off or enters an off state. The HS-FET is
turned on again when VFB drops below VREF. By
repeating operation this way, the converter
regulates the output voltage. The integrated
low-side MOSFET (LS-FET) is turned on when
the HS-FET is in its off state to minimize
conduction loss. A dead short occurs between
the input and GND if both the HS-FET and the
LS-FET are turned on at the same time. This is
called shoot-through. To prevent shoot-through,
a dead time (DT) is generated internally
between the HS-FET off and the LS-FET on
period or the LS-FET off and the HS-FET on
period.
Internal compensation is applied for COT
control for stable operation, even when ceramic
capacitors are used as output capacitors. This
internal
compensation
improves
jitter
performance without affecting the line or load
regulation.
Heavy-Load Operation
Continuous conduction mode (CCM) occurs
when the output current is high and the inductor
current is always above zero amps (see Figure
2). When VFB is below VREF, the HS-FET is
turned on for a fixed interval, which is
determined by the one-shot on timer. When the
HS-FET is turned off, the LS-FET is turned on
until the next period.
Figure 2: CCM Operation
In CCM operation, the switching frequency is
fairly constant (PWM mode).
Light-Load Operation
When the load decreases, the inductor current
decreases as well. Once the inductor current
reaches zero, the MP8719 transitions from
CCM to discontinuous conduction mode (DCM).
DCM operation is shown in Figure 3.
When VFB is below VREF, the HS-FET is turned
on for a fixed interval, which is determined by
the one-shot on timer. When the HS-FET is
turned off, the LS-FET is turned on until the
inductor current reaches zero. In DCM
operation, the VFB does not reach VREF when
the inductor current is approaching zero. The
LS-FET driver turns into tri-state (Hi-Z) when
the inductor current reaches zero. A current
modulator takes over the control of the LS-FET
and limits the inductor current to less than -1mA.
Therefore, the output capacitors discharge
slowly to GND through the LS-FET. As a result,
efficiency during light-load condition is improved
greatly. The HS-FET does not turn on as
frequently during light-load condition as it does
during heavy-load condition (skip mode).
At a light-load or no-load condition, the output
drops very slowly, and the MP8719 reduces the
switching frequency naturally, achieving high
efficiency at light load.
Figure 3: DCM Operation
MP8719 Rev. 1.01
8/3/2017
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MP8719 – 26V, 12A, HIGH-CURRENT, SYNC BUCK CONVERTER WITH ±1A LDO
As the output current increases from light-load
condition, the current modulation regulation
time period becomes shorter. The HS-FET is
turned on more frequently, making the
switching frequency increase. The output
current reaches the critical level when the
current modulator time is zero. The critical level
of the output current is determined with
Equation (1):
IOUT _ Critical
( V VOUT ) VOUT
IN
2 L FS VIN
(1)
The MP8719 enters PWM mode once the
output current exceeds the critical level.
Afterward, the switching frequency remains
fairly constant over the output current range.
Jitter and FB Ramp
Jitter occurs in both PWM and skip mode when
noise in the VFB ripple propagates a delay to the
HS-FET driver (see Figure 4 and Figure 5).
Jitter affects system stability, with noise
immunity proportional to the steepness of VFB’s
downward slope, so the jitter in DCM is usually
larger than it is in CCM. However, VFB ripple
does not affect noise immunity directly.
VNOISE
Figure 6 shows a typical output circuit in PWM
mode without an external ramp circuit. Refer to
the Application Information section on page 16
for design steps without external compensation.
Figure 6: Simplified Output Circuit
VREF
HS D river
J itter
Figure 4: Jitter in PWM Mode
VS LOPE 2
V FB
V REF
HS D river
Jitter
Figure 5: Jitter in Skip Mode
MP8719 Rev1.01
8/3/2017
The MP8719 has built-in internal ramp
compensation to ensure that the system is
stable, even without the help of the output
capacitor’s ESR. Use the pure ceramic
capacitor solution, which reduces the output
ripple, total BOM cost, and board area
significantly.
V S L O PE1
VFB
VNOISE
Operating
without
External
Ramp
Compensation
The traditional COT control scheme is
intrinsically unstable if the output capacitor’s
ESR is not large enough to act as an effective
current-sense
resistor.
Usually,
ceramic
capacitors cannot be used directly as output
capacitors.
When using a large capacitor (e.g.: OSCON) on
the output, add a >10µF ceramic capacitor in
parallel to minimize the effect of ESL.
Operating
with
External
Ramp
Compensation
Usually, the MP8719 is able to support ceramic
output capacitors without an external ramp.
However in some cases, the internal ramp may
not be enough to stabilize the system, or there
is too much jitter, which requires external ramp
compensation. Refer to the Application
Information section on page 16 for design steps
with external ramp compensation.
VTT and VTTREF
The MP8719 integrates high performance, low
dropout linear regulators (VTT and VTTREF) to
provide
complete
DDR3/DDR3L
power
solutions. The VTTREF has a 10mA
sink/source current capability and always tracks
half of VDDQ with ±1% accuracy using an on-
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12
MP8719 – 26V, 12A, HIGH-CURRENT, SYNC BUCK CONVERTER WITH ±1A LDO
PRELIMINARY SPECIFICATIONS SUBJECT TO CHANGE
chip divider. A minimum 0.22μF ceramic
can be selected by a different resistor on the
capacitor must be connected close to the
3V3 logic mode pin. There are four modes that
VTTREF terminal for stable operation.
can be selected for normal application with
external resistors (see Table 2). It is
VTT responds quickly to track VTTREF with
recommended to use a 1% accuracy resistor.
±30mV in all conditions. The current capability
Table 2: Mode Selection
of the VTT regulator is up to 1A for both sink
State USM
Fs
Resistor to GND
and source modes. A minimum 22μF ceramic
capacitor must be connected close to the VTT
M1
No
700kHz
0Ω
terminal. VTTS should be connected to the
M2
Yes
700kHz
90kΩ
positive node of the remote VTT output
M3
No
500kHz
150kΩ
capacitor as a separate trace from the highM4
Yes
500kHz
>230kΩ or float
current line to VTT.
Configuring the EN Control
The MP8719 has two enable pins to turn the
internal regulators on or off (EN1, EN2). When
EN1 and EN2 are high, VDDQ, VTTREF and
VTT are turned on. When EN1 is low and EN2
is high, VDDQ and VTTREF remain on while
VTT is turned off and left at a high-impedance
state (Hi-Z). The VTT output floats and does not
sink or source current in this state. When EN1
and EN2 are low, all of the regulators remain off
and discharge to GND through a soft
shutdown(see Table 1).
VDDQ Power Good (PG)
The MP8719 uses a power good (PG) output to
indicate whether the output voltage of the
VDDQ regulator is ready. PG is the open drain
of a MOSFET. It should be connected to VCC or
another voltage source through a resistor (e.g.:
100kΩ). After the input voltage is applied, the
MOSFET is turned on, so PG is pulled to GND
before SS is ready. After VFB reaches 95% of
VREF, PG is pulled high (after a delay time within
10µs). When VFB drops to 90% of VREF, PG is
pulled low.
Table 1: EN1/EN2 Control
Soft Start (SS)
The MP8719 employs a soft-start (SS)
mechanism to ensure a smooth output during
power-up. When EN becomes high, the internal
reference voltage ramps up gradually, and the
output voltage ramps up smoothly as well.
Once the reference voltage reaches the target
value, the soft start finishes, and the MP8719
enters steady-state operation (see Figure 7).
EN1
EN2
VDDQ
VTTREF
VTT
High
High
On
On
On
Low
High
On
On
Off (Hi-Z)
Low
Low
Off
Off
Off
High
Low
Off
Off
Off
Ultrasonic Mode (USM)
Ultrasonic mode (USM) is designed to keep the
switching frequency above an audible
frequency area during light-load or no-load
conditions. Once the part detects that both the
HS-FET and the LS-FET are off for about 32µs),
PWM is forced to initiate TON, so the switching
frequency is out of the audible range. To
prevent VOUT from rising too high, the MP8719
reduces TON to control VOUT. If the MP8719’s FB
is still too high after reducing TON to the
minimum value, the output discharge function is
activated and keeps VOUT within a reasonable
range. USM is selected by MODE.
MODE Selection
The MP8719 implements MODE for multiple
applications for USM and switching frequency
selection. USM and the switching frequency
MP8719 Rev. 1.01
8/3/2017
Figure 7: Start-Up Power Sequence
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MP8719 – 26V, 12A, HIGH-CURRENT, SYNC BUCK CONVERTER WITH ±1A LDO
If the output is pre-biased to a certain voltage
during start-up, the IC disables the switching of
both the high-side and low-side switches until
the voltage on the internal reference exceeds
the sensed output voltage at the FB node.
Soft Shutdown
The MP8719 employs a soft shutdown
mechanism for DDR to ensure that VTTREF
and VTT follow exactly half of the VDDQ. When
EN2 is low, the internal reference then ramps
down gradually, so the output voltage falls
linearly (see Figure 8).
Since the comparison is done during the LSFET on state, the OC trip level sets the valley
level of the inductor current. The maximum load
current at the over-current threshold (IOC) can
be calculated using Equation (2):
IOC I _ limit
Iinductor
2
(2)
The over-current limit (OCL) limits the inductor
current and does not latch off. In an overcurrent condition, the current to the load
exceeds the current to the output capacitor, so
the output voltage tends to fall off. Eventually,
the currents ends up crossing the under-voltage
protection (UVP) threshold and latches off.
Fault latching can be reset by EN going low or
cycling the power of VIN.
VTT/VTTREF Over-Current Protection (OCP)
The VTT LDO has an internal, non-latched,
fixed current limit of 1.5A for both sink and
source operation. Once the current limit is
reached, the gate of the sink/source MOSFET
is adjusted to limit the current. VTTREF also
has an internal non-latch 15mA current limit.
Figure 8: Soft Shutdown Sequence
VDDQ Over-Current Limit (OCL)
The MP8719 has cycle-by-cycle over-current
limiting control. The current-limit circuit employs
a valley current-sensing algorithm. The MP8719
uses the RDS(ON) of the LS-FET as a currentsensing element. If the magnitude of the
current-sense signal is above the current-limit
threshold, the PWM is not allowed to initiate a
new cycle, even if FB is lower than REF (see
Figure 9).
VDDQ Over/Under-Voltage Protection (OVP,
UVP)
The MP8719 monitors a resistor divided
feedback voltage to detect over and under
voltage. When the feedback voltage rises
higher than 130% of the target voltage, the
OVP comparator output goes high, the circuit
latches as the HS-FET turns off, and the LSFET turns on, acting as a -2A current source.
To protect the MP8719 from damage, there is
an absolute 3.6V OVP on VOUT. Once VOUT
reaches this value, it latches off as well. The
LS-FET behaves the same as it does at 130%
OVP.
When the feedback voltage drops below 75% of
VREF, but remains higher than 50% of VREF, the
UVP-1 comparator output goes high, and the
MP8719 latches if VFB remains in this range for
about 30µs (latching the HS-FET off and the
LS-FET on). The LS-FET remains on until the
inductor current reaches zero. During this
period, the valley current limit helps control the
inductor current.
Figure 9: Valley Current-Limit Control
MP8719 Rev1.01
8/3/2017
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MP8719 – 26V, 12A, HIGH-CURRENT, SYNC BUCK CONVERTER WITH ±1A LDO
When the feedback voltage drops below 50% of
VREF, the UVP-2 comparator output goes high,
and the MP8719 latches off directly after the
comparator and logic delay (latching the HSFET off and the LS-FET on). The LS-FET
remains on until the inductor current reaches
zero. Fault latching can be reset by driving EN
low or cycling the power of VIN.
Under-Voltage Lockout (UVLO) Protection
The MP8719 has two under-voltage lockout
(UVLO) protections: a 3V VCC UVLO and a
4.2V VIN UVLO. The MP8719 starts up only
when both VCC and VIN exceed their
respective UVLO thresholds. The MP8719
shuts down when either VCC is lower than the
UVLO falling threshold voltage (typically 2.8V)
or VIN is lower than the 3.9V VIN falling
threshold. Both UVLO protections are non-latch
off.
If an application requires a higher under-voltage
lockout (UVLO), use EN2 to adjust the input
voltage UVLO by using two external resistors
(see Figure 10).
Over-Temperature Warning (OTW)
An over-temperature warning (OTW) status pin
is added on the MP8719 to act as a pre-overtemperature indicator. When the IC detects that
it is close to its over-temperature threshold,
OTW pulls low and remains low for at least
10ms. OTW pulls high again when the device
temperature has cooled below the temperature
hysteresis. OTW does not trigger any protection.
Thermal Shutdown
Thermal shutdown is employed in the MP8719.
The junction temperature of the IC is monitored
internally. If the junction temperature exceeds
the threshold value (typically 145°C), the
converter shuts off. This is a non-latch
protection. There is a hysteresis of about 25°C.
Once the junction temperature drops to about
120°C, soft start is initiated.
Output Discharge
The MP8719 discharges all the outputs
including VDDQ, VTTREF, and VTT when the
controller is turned off by a protection function
(UVP, OCP, OVP, UVLO, or thermal shutdown).
The discharge resistor on VDDQ is 3Ω, typically.
Note that the output discharge is not active
during soft shutdown.
Figure 10: Adjustable UVLO
MP8719 Rev1.01
8/3/2017
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15
MP8719 – 26V, 12A, HIGH-CURRENT, SYNC BUCK CONVERTER WITH ±1A LDO
PRELIMINARY SPECIFICATIONS SUBJECT TO CHANGE
APPLICATION INFORMATION
Setting the Output Voltage with No External
Ramp
The
MP8719
does
not
need
ramp
compensation for applications where POSCAP
or ceramic capacitors are set as output
capacitors (when VIN is over 6V), so external
compensation is not needed. The output
voltage is then set by feedback resistors R1
and R2 (see Figure 11).
L
Vo
SW
C4
FB
R1
R2
CAP
Figure 11: Simplified Circuit without External
Ramp
First, choose a value for R2. R2 should be
chosen reasonably. A small value for R2 leads
to considerable quiescent current loss, but an
R2 value that is too large makes FB noisesensitive. It is recommended to choose a value
within 5 - 50kΩ for R2. Use a comparatively
larger value for R2 when VOUT is low; use a
smaller value for R2 when VOUT is high.
Considering the output ripple, determine R1
with Equation (3):
V
VREF
R1 OUT
R2
VREF
(3)
C4 acts as a feed-forward capacitor to improve
the transient and can be set in the range of
0 - 1000pF. A larger value for C4 leads to better
transient, but it is more noise sensitive.
Reserve room for a noise filter resistor (R9)
(see Figure 12).
Setting the Output Voltage with External
Compensation
If the system is not stable enough or there is
too much jitter when a ceramic capacitor is
used on the output (i.e.: with a ceramic COUT
and VIN is 5V or lower), an external voltage
ramp should be added to FB through resistor
R4 and capacitor C4. Since there is already an
internal ramp added in the system, a 1MΩ (R4)
220pF (C4) ramp should suffice.
MP8719 Rev. 1.01
8/3/2017
Figure 12: Simplified Circuit with External Ramp
Besides the R1 and R2 divider, the output
voltage is influenced by R4 (see Figure 12). R2
should be chosen reasonably. A small value for
R2 leads to considerable quiescent current loss,
but a value for R2 that is too large makes FB
noise sensitive. It is recommended to choose a
value within 5 - 50kΩ for R2. Use a
comparatively larger value for R2 when VOUT is
low; use a smaller value for R2 when VOUT is
high. The value of R1 then is determined with
Equation (4):
R1
1
VREF
R2
VOUT VREF R4
R2
(4)
To get a pole for better noise immunity, set R9
with Equation (5):
R9
1
2 C4 2FSW
(5)
Set R9 in the range of 100Ω to 1kΩ to reduce
its influence on the ramp.
Selecting the Input Capacitor
The input current to the step-down converter is
discontinuous and therefore requires a
capacitor to supply AC current to the step-down
converter while maintaining the DC input
voltage. For the best performance, use ceramic
capacitors placed as close to VIN as possible.
Capacitors with X5R and X7R ceramic
dielectrics are recommended because they are
fairly stable with temperature fluctuations.
The capacitors must have a ripple current rating
greater than the maximum input ripple current
of the converter. The input ripple current can be
estimated with Equation (6):
ICIN IOUT
VOUT
V
(1 OUT )
VIN
VIN
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(6)
16
MP8719 – 26V, 12A, HIGH-CURRENT, SYNC BUCK CONVERTER WITH ±1A LDO
The worst-case condition occurs at VIN = 2VOUT,
shown in Equation (7):
ICIN
IOUT
2
(7)
For simplification, choose an input capacitor
with an RMS current rating greater than half of
the maximum load current.
The input capacitance value determines the
input voltage ripple of the converter. If there is
an input voltage ripple requirement in the
system, choose an input capacitor that meets
the specification.
The input voltage ripple can be estimated with
Equation (8):
VIN
IOUT
V
V
OUT (1 OUT )
FSW CIN VIN
VIN
(8)
The worst-case condition occurs at VIN = 2VOUT,
shown in Equation (9):
VIN
IOUT
1
4 FSW CIN
(9)
Selecting the Output Capacitor
The output capacitor is required to maintain the
DC output voltage. Ceramic or POSCAP
capacitors are recommended. The output
voltage ripple can be estimated using Equation
(10):
VOUT
VOUT
V
1
(1 OUT ) (RESR
) (10)
FSW L
VIN
8 FSW COUT
When using ceramic capacitors, the impedance
at the switching frequency is dominated by the
capacitance, which mainly causes the output
voltage ripple. For simplification, the output
voltage ripple can be estimated with Equation
(11):
VOUT
VOUT
V
(1 OUT )
8 FSW 2 L COUT
VIN
VOUT
(11)
VOUT
V
(1 OUT ) RESR
FSW L
VIN
(12)
The maximum output capacitor limitation should
be considered in the design application. The
MP8719 has a soft-start time period of around
1.6ms. If the output capacitor value is too high,
the output voltage cannot reach the design
value during the soft-start time, causing it to fail
to regulate. The maximum output capacitor
value (Co_max) can be limited approximately with
Equation (13):
CO _ MAX (ILIM _ AVG IOUT ) Tss / VOUT
(13)
Where ILIM_AVG is the average start-up current
during the soft-start period (which can be
equivalent to the current limit), and Tss is the
soft-start time.
Selecting the Inductor
An inductor is necessary for supplying constant
current to the output load while being driven by
the switched input voltage. A larger-value
inductor results in less ripple current, resulting
in lower output ripple voltage, but also has a
larger physical footprint, a higher series
resistance, and a lower saturation current. A
good rule for determining the inductance value
is to design the peak-to-peak ripple current in
the inductor to be in the range of 30% to 50% of
the maximum output current, and the peak
inductor current below the maximum switch
current limit. The inductance value can be
calculated with Equation (14):
L
The output voltage ripple caused by ESR is
very small. Therefore, an external ramp is
needed to stabilize the system. The external
ramp can be generated through resistor R4 and
capacitor C4.
MP8719 Rev1.01
8/3/2017
When using POSCAP capacitors, the ESR
dominates the impedance at the switching
frequency. The ramp voltage generated from
the ESR dominates the output ripple. The
output ripple can be approximated with
Equation (12):
VOUT
V
(1 OUT )
FSW IL
VIN
(14)
Where ∆IL is the peak-to-peak inductor ripple
current.
The inductor should not saturate under the
maximum inductor peak current (including a
short-current), so ISAT is recommended to
be >13A.
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MP8719 – 26V, 12A, HIGH-CURRENT, SYNC BUCK CONVERTER WITH ±1A LDO
4. Place the decoupling capacitor as close to
VCC and GND as possible.
PCB Layout Guidelines
Efficient PCB layout is critical for stable
operation of the IC. A 4-layer layout is strongly
recommended to achieve better thermal
performance. For best results, refer to Figure
13 and follow the guidelines below. For more
information, refer to the application note AN087
“PCB Layout Design Guidelines for NB68X
Families.”
5. Keep the switching node (SW) short and
away from the feedback network.
6. Place the external feedback resistors next
to FB.
7. Ensure that there is no via on the FB trace.
8. Keep the BST voltage path (BST, C3, and
SW) as short as possible.
1. Keep the VDDQ trace width greater than
100mil to avoid a voltage drop at the input
of the VTTLDO.
9. Keep the VIN and GND pads connected
with a large copper plane to achieve better
thermal performance.
2. Place the high-current paths (GND, VIN,
and SW) very close to the device with short,
direct, and wide traces.
A thick PGND trace under the IC should be
top priority.
10. Add several vias with 10mil drill/18mil
copper width close to the VIN and GND
pads to help thermal dissipation.
3. Place the input capacitors as close to VIN
and GND as possible on the same layer as
the IC.
To Vout
To AGND
VCC
0402
PG
EN1
EN2
MODE
FB
PG
OTW
16
15
14
13
12
11
OTW
0603
VIN
SW
VIN
1
10
BST
9
SW
2 PGND
3
4
5
3V3
AGND
VTT
6
7
8
VDDQ VTTREF VTTS
L
7mm*6.6mm
>100Mil
AGND–PGND KELVIN
CONNECTION
PGND
VOUT
0805
VOUT
Figure 13: Recommended PCB Layout
MP8719 Rev1.01
8/3/2017
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MP8719 – 26V, 12A, HIGH-CURRENT, SYNC BUCK CONVERTER WITH ±1A LDO
Design Example
For applications that need currents over 10A, it
is recommended to apply a 500kHz fSW part for
better thermal performance and efficiency (see
Table 3). Otherwise, a 700kHz fSW operation
makes the system more compact with faster
transient (see Table 4).
There is a resistor from an external 3.3V supply
to 3V3 acting as a ripple noise filter of the 3.3V
power supply. It is recommended to have a
resistor value from 0 - 5.1Ω depending on the
noise level. A size 0402 resistor is sufficient if
the 3.3V voltage rises up with SS > 100µs.
Otherwise, a larger resistor (e.g.: 0603/0805) is
needed.
For applications where VIN is 5V or lower, it is
recommended to apply the SCH shown in
Figure 14 with a proper external ramp.
The MP8719 also supports non DDR
applications with very compact external
components (see Figure 15).
Some design examples are provided below
when ceramic capacitors are applied.
MP8719 Rev1.01
8/3/2017
Table 3: Design Example for 500kHz fSW
VOUT
(V)
Cout
(F)
L
(μH)
1.0
22μx4
1.0
1.2
22μx4
1.0
1.35
22μx4
1.0
1.5
22μx4
1.8
22μx4
RMode
(Ω)
C4
(pF)
R1
(kΩ)
R2
(kΩ)
150k
220
13.3
20
150k
220
20
20
150k
220
28
22.1
1.2
150k
220
30.1
20
1.5
150k
220
40.2
20
Table 4: Design Example for 700kHz fSW
VOUT
(V)
Cout
(F)
L
(μH)
RMode
(Ω)
C4
(pF)
R1
(kΩ)
R2
(kΩ)
1
22μx3
0.68
0
220
13.3
20
1.2
22μx3
0.68
0
220
20
20
1.35
22μx3
0.68
0
220
28
22.1
1.5
22μx3
0.68
0
220
30.1
20
1.8
22μx3
0.68
0
220
40.2
20
Additional Design Examples with Higher
VOUT
The MP8719 supports designs that need VOUT
to be in the range of 3.3V to 5.5V. Figure 17
shows an SCH with a 5V VOUT with proper
external settings. Please pay attention to the
red components, and please note that USM is
not allowed for this application.
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MP8719 – 26V, 12A, HIGH-CURRENT, SYNC BUCK CONVERTER WITH ±1A LDO
TYPICAL APPLICATION CIRCUITS
DDR Application for VIN >6V
VIN
OTW
BST
SW
DDR_VTT_CONTROL
EN 1
EN 2
FB
EN 2
PG
VDDQ
3V3
VTT
VTTSEN
AGND
PGND
MODE
VTTREF
Figure 14: Typical DDR Application Circuit, VIN = 6V - 24V, VOUT = 1.35V, IOUT = 10A, with VTT fs = 700kHz
DDR Application Cover 5V VIN Application
Figure 15: Typical DDR Application Circuit, VIN = 4.5V - 24V, VOUT = 1.35V, IOUT = 10A, with VTT fs = 700kHz
MP8719 Rev. 1.01
8/3/2017
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MP8719 – 26V, 12A, HIGH-CURRENT, SYNC BUCK CONVERTER WITH ±1A LDO
TYPICAL APPLICATION CIRCUITS (continued)
Non DDR Application
Figure 16: Normal Single Buck Application Circuit, VIN = 4.5V - 24V, VOUT = 1V, IOUT = 10A,
without VTT fs = 700kHz
Special Application with 3.3V < VOUT < 5.5V
Figure 17: Special Application Circuit, VIN = 7V - 22V, VOUT = 5V, IOUT = 10A, fs = 700kHz
NOTE 1: Ultrasonic mode is not effective if applied in this SCH.
NOTE 2: The maximum load is 10A in this application. Fs is set with a 500kHz mode but is actually 700kHz.
NOTE 3: It is recommended to avoid VDDQ voltages over 3.3V by using the external resistors setting.
MP8719 Rev. 1.01
8/3/2017
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21
MP8719 – 26V, 12A, HIGH-CURRENT, SYNC BUCK CONVERTER WITH ±1A LDO
PACKAGE INFORMATION
QFN-16 (3mmx3mm)
NOTICE: The information in this document is subject to change without notice. Users should warrant and guarantee that third
party Intellectual Property rights are not infringed upon when integrating MPS products into any application. MPS will not
assume any legal responsibility for any said applications.
MP8719 Rev. 1.01
8/3/2017
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