MP024-10
Primary-Side, CC/CV, Flyback Regulator
with High-Voltage Current Source and
Programmable Cable Compensation
DESCRIPTION
FEATURES
The MP024-10 is a low-cost, offline, primaryside, flyback regulator with a simple, external
circuit. It provides accurate constant voltage
(CV) and constant current (CC) regulation
without an optocoupler or secondary feedback
circuit and has an integrated 700V MOSFET
and high-voltage start-up current source.
The MP024-10 operates in discontinuous
conduction mode (DCM) using variable off-time
control. Its power-saving technologies limit the
no-load power consumption to less than 30mW.
Full protection features include VCC undervoltage lockout (VCC UVLO), overload
protection (OLP), over-temperature protection
(OTP), open-loop protection (OCkP), sensingshort protection (SSP), and over-voltage
protection (OVP).
The variable switching frequency method
provides natural spectrum shaping to smooth
the EMI signature, making the MP024-10
suitable for offline, low-power battery chargers
and adapters.
Primary-Side Control without Optocoupler or
Secondary Feedback Circuit
Precise Constant Current and Constant
Voltage Control (CC/CV)
Variable Off-Time Peak-Current Control
700V/4.5Ω Integrated MOSFET
700V High-Voltage Current Source
30mW No-Load Power Consumption
Programmable Cable Compensation
Multiple Protections: OVP, OCkP, SSP,
OLP, OTP, and VCC UVLO
Low Cost and Simple External Circuit
Available in a SOIC8-7B Package
APPLICATIONS
Cell Phone Chargers
Adapters for Handheld Electronics
Standby and Auxiliary Power Supplies
All MPS parts are lead-free, halogen-free, and adhere to the RoHS directive.
For MPS green status, please visit MPS website under Quality Assurance.
“MPS” and “The Future of Analog IC Technology” are registered trademarks of
Monolithic Power Systems, Inc.
The MP024-10 is available in a SOIC8-7B
package.
Maximum Output Power (1) (4)
230Vac ±15%
Open
Adapter
(3)
Frame (2)
POUT
(W)
13
10
85Vac~265Vac
Open
Adapter
(3)
Frame (2)
10
7.5
NOTES:
1) The maximum output power is limited by thermal shutdown.
2) Maximum continuous power in an open frame design at
50°C ambient temperature.
3) Maximum continuous power in a non-ventilated enclosed
adapter measured at 50°C ambient temperature.
4) Single output, VOUT = 5V.
MP024-10 Rev.1.0
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1
MP024-10 – PRIMARY-SIDE CC/CV REGULATOR
TYPICAL APPLICATION
Output
Input
CP
DRAIN
VCC
FB
GND
SOURCE
SS
MP024-10
MP024-10 Rev.1.0
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MP024-10 – PRIMARY-SIDE CC/CV REGULATOR
ORDERING INFORMATION
Part Number*
MP024GS-10
Package
SOIC8-7B
Top Marking
See Below
* For Tape & Reel, add suffix –Z (e.g. MP024GS-10–Z)
TOP MARKING
MP024-10: First five digits of the part number
LLLLLLLL: Lot number
MPS: MPS prefix
Y: Year code
WW: Week code
PACKAGE REFERENCE
TOP VIEW
FB
1
8
2
7
GND
CP
6
DRAIN
4
VCC
5
SS
SOURCE
SOIC8-7B
MP024-10 Rev.1.0
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MP024-10 – PRIMARY-SIDE CC/CV REGULATOR
ABSOLUTE MAXIMUM RATINGS (5)
Thermal Resistance (4)
DRAIN to SOURCE, GND ........... -0.3V to 700V
VCC to GND .................................. -0.3V to 28V
CP, SS, SOURCE to GND ............... -0.3V to 7V
FB to GND ....................................... -0.7V to 7V
Continuous power dissipation (TA = +25°C) (6)
................................................................ 1.66W
Junction temperature ............................... 150°C
Lead temperature .................................... 260°C
Storage temperature ................ -60°C to +150°C
ESD capability human body model ........... 2.0kV
ESD capability machine model ..................200V
SOIC8-7B.............................. 75 ....... 45 ... °C/W
Recommended Operating Conditions (7)
θJA
θJC
NOTES:
5) Exceeding these ratings may damage the device.
6) The maximum allowable power dissipation is a function of
the maximum junction temperature TJ (MAX), the junction-toambient thermal resistance θJA, and the ambient temperature
TA. The maximum allowable continuous power dissipation at
any ambient temperature is calculated by PD (MAX) = (TJ
(MAX)-TA)/θJA. Exceeding the maximum allowable power
dissipation produces an excessive die temperature, causing
the regulator to go into thermal shutdown. Internal thermal
shutdown circuitry protects the device from permanent
damage.
7) The device is not guaranteed to function outside of its
operating conditions.
8) Measured on JESD51-7, 4-layer PCB.
Junction temperature (TJ) .......... -40°C to +125°C
Ambient temperature (TA) .......... -40°C to +110°C
Operating VCC range ...................... 10V to 25V
MP024-10 Rev.1.0
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MP024-10 – PRIMARY-SIDE CC/CV REGULATOR
ELECTRICAL CHARACTERISTICS
VCC = 15V, TJ = -40°C~125°C, min and max values are guaranteed by characterization, typical
values are tested under 25°C, unless otherwise noted.
Parameter
Symbol Condition
Min
Typ
Max
Units
18.8
8.2
19.4
8.7
235
0.55
20.0
9.2
300
0.85
V
V
μA
mA
Supply Voltage Management (VCC)
VCC on threshold
VCC off threshold
VCCH
VCCL
Operating current
IOP
fS = fS-min
fS = 40kHz
Internal MOSFET (DRAIN)
Breakdown voltage
On state resistance
High-voltage current source
supply current
Leakage current
Internal MOSFET (SOURCE)
Maximum on time
Minimum switching frequency
Current limit
fS to start the current foldback
fS to end the current foldback
Leading edge blanking
Feedback Input (FB)
FB input current
FB reference voltage
OLP threshold at sampled FB
OLP counter
FB sampling duration
VBRDSS
RDSon
IHV
Ileak
tONmax
fS-min
VLimit-Max
VLimit-Min
700
VCC = 10V, IDS = 0.1A,
TJ = 25°C
VCC = 18V, VD = 80V,
TJ = 25°C
VD = 400V, TJ = 25°C
VSOURCE = 0V
25
fS ≥ fS-H
fS ≤ fS-L
464
220
fS-H
fS-L
tLEB
IFB
1.8
26
190
V
4.5
6.5
Ω
2.2
2.6
mA
11
µA
40
75
480
250
55
110
496
280
μs
Hz
mV
mV
40
20
300
54
kHz
kHz
ns
410
VFB = 4V, VCP = 2V
VFB = 4V, VCP = 1.5V
12
9
μA
μA
VFB = 4V, VCP = 0.8V
VFB = 4V, VCP = 0.2V
μA
μA
V
V
VFB
VFBolp
3.90
tFB-SD
180
4.6
1.2
3.96
1.4
768
260
RSS = 0Ω, VLimit = 0.5V
RSS = 1kΩ, VLimit = 0.5V
RSS = 2kΩ, VLimit = 0.5V
RSS = 4kΩ, VLimit = 0.5V
RSS = 0Ω, VLimit = 0.25V
RSS = 1kΩ, VLimit = 0.25V
RSS = 2kΩ, VLimit = 0.25V
2.60
1.85
3.8
5.3
1.1
0.75
1.85
3.62
2.72
5.5
7.2
1.82
1.35
2.72
4.9
3.65
7.2
9.3
2.6
1.95
3.65
RSS = 4kΩ, VLimit = 0.25V
2.6
3.62
4.9
FB maximum sampling time
tFBS-Max
FB minimum sampling time
tFBS-Min
MP024-10 Rev.1.0
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4.02
360
ns
μs
μs
5
MP024-10 – PRIMARY-SIDE CC/CV REGULATOR
ELECTRICAL CHARACTERISTICS (continued)
VCC = 15V, TJ = -40°C~125°C, min and max values are guaranteed by characterization, typical
values are tested under 25°C, unless otherwise noted.
Parameter
ZCD threshold
FB open-circuit threshold
Symbol Condition
VDCM
VFBopen
OVP threshold at FB
VFBovp
FB OVP blanking time
tOVP-B
Output Cable Compensation (CP)
Supply voltage on CP
Thermal Shutdown
VCP-Max
Min
Typ
Max
Units
55
-190
100
-110
145
-45
mV
mV
5.7
1
5.96
1.35
6.3
1.7
V
μs
4
V
Thermal shutdown threshold (9)
140
°C
Thermal shutdown recovery
hysteresis (9)
40
°C
NOTE:
9) The parameters are guaranteed by characterization.
MP024-10 Rev.1.0
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MP024-10 – PRIMARY-SIDE CC/CV REGULATOR
PIN FUNCTIONS
SOIC8-7B
Pin #
Name
1
FB
2
GND
4
DRAIN
5
SOURCE
6
SS
7
CP
8
VCC
Description
Feedback. The FB voltage determines the operation mode (CV mode or CC
mode).
Ground.
Drain of the internal MOSFET. DRAIN is integrated with an internal highvoltage current source, which charges up VCC for start-up.
Source of the internal MOSFET. Connect a current sense resistor to detect the
MOSFET current for peak-current-mode control in CV and CC mode.
Select sampling time by different external resistor configurations.
Output cable compensation. Connect a 1µF ceramic capacitor to CP as a lowpass filter. The compensation voltage can be adjusted by the resistor divider. CP
can also be used to select the secondary duty limitation by different external
resistor configurations.
Supply voltage. When VCC is lower than a certain level, the internal high
voltage current source is turned on to charge up VCC. When VCC is charged to
a certain level by the internal high-voltage current source, the IC begins working.
In addition to the bulk capacitor, a 0.1µF ceramic capacitor can be connected as
close to VCC as possible to decouple the noise disturbance.
MP024-10 Rev.1.0
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MP024-10 – PRIMARY-SIDE CC/CV REGULATOR
TYPICAL CHARACTERISTICS
VCC Off Threshold vs. Temperature
20.0
9
19.8
8.9
19.6
8.8
VCCL (V)
VCCH (V)
VCC On Threshold vs. Temperature
19.4
19.2
8.7
8.6
19.0
8.5
-50
0
50
100
TEMPERATURE (°C)
150
-50
3.0
10
2.5
8
2.0
6
1.5
1.0
150
4
2
0.5
0
-50
0
50
100
TEMPERATURE (°C)
150
-50
Breakdown Voltage vs. Temperature
800
250
780
240
760
230
740
210
700
200
0
50
100
TEMPERATURE (°C)
150
50
100
TEMPERATURE (°C)
150
220
720
-50
0
Operating Current @ Fs_min vs.
Temperature
IOP (uA)
VBRDSS (V)
50
100
TEMPERATURE (°C)
Leakage Current @ VD = 400V vs.
Temperature
Ileak (uA)
IHV (mA)
High-Voltage Current Source Supply
Current @ VD = 80V vs. Temperature
0
-50
0
50
100
TEMPERATURE (°C)
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150
8
MP024-10 – PRIMARY-SIDE CC/CV REGULATOR
TYPICAL CHARACTERISTICS (continued)
Operating Current @ fS = 40kHz vs.
Temperature
10
600
8
580
6
560
IOP (uA)
RDSon (Ω)
On-State Resistance vs. Temperature
4
2
540
520
0
500
-50
0
50
100
TEMPERATURE (°C)
150
-50
FB Reference Voltage vs. Temperature
3.98
490
VLimit_Max (V)
500
VFB (V)
3.94
3.92
150
480
470
460
3.90
-50
0
50
100
TEMPERATURE (°C)
450
150
-50
ZCD Threshold vs. Temperature
0
50
TEMPERATURE (°C)
100
150
FB Open-Circuit Threshold vs.
Temperature
110
-90
106
-100
102
-110
VFBopen (mV)
VDCM (mV)
100
Current Limit vs. Temperature
4.00
3.96
0
50
TEMPERATURE (°C)
98
94
90
-120
-130
-140
-50
0
50
TEMPERATURE (°C)
100
150
-50
0
50
TEMPERATURE (°C)
100
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150
9
MP024-10 – PRIMARY-SIDE CC/CV REGULATOR
TYPICAL CHARACTERISTICS (continued)
FB Maximum Sampling Time @ RSS = 0Ω
vs. Temperature
100
4.3
90
4.1
80
3.9
tFBS-Max (μs)
fS-min (Hz)
Minimum Switching Frequency vs.
Temperature
70
60
3.7
3.5
50
3.3
-50
0
50
100
TEMPERATURE (°C)
150
-50
0
50
100
TEMPERATURE (°C)
150
FB Minimum Sampling Time @ RSS = 0Ω
vs. Temperature
2.4
tFBS-Max (μs)
2.2
2.0
1.8
1.6
1.4
-50
0
50
100
TEMPERATURE (°C)
150
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MP024-10 – PRIMARY-SIDE CC/CV REGULATOR
TYPICAL PERFORMANCE CHARACTERISTICS
Performance waveforms are tested on the evaluation board in the Design Example section.
VIN = 230VAC, VOUT = 5V, IOUT = 2A, unless otherwise noted.
No-Load Consumption
Efficiency
81%
30
80%
25
79%
EFFICIENCY
PIN (mW)
20
15
10
5
77%
76%
75%
Vin=115VAC
Vin=230VAC
74%
0
73%
85
115
145
175
VIN (VAC)
Conducted EMI
VIN = 115VAC, L Line
Att 10 dB
dBµV
78%
RBW
9 kHz
MT
20 ms
235
265
0
0.5
1
IOUT (A)
Conducted EMI
VIN = 115VAC, N Line
Att 10 dB
PREAMP OFF
1 MHz
120
205
dBµV
10 MHz
1.5
RBW
9 kHz
MT
20 ms
PREAMP OFF
1 MHz
120
2
10 MHz
110
110
SGL
SGL
1 PK
1 PK
100
2 AV
90
2 AV
TDS
CLRWR
90
TDS
CLRWR
80
80
70
70
EN55022Q
EN55022Q
60
60
EN55022A
EN55022A
6DB
50
6DB
50
40
40
30
30
20
20
10
10
0
0
150 kHz
30 MHz
Conducted
EMI
16:29:11
VIN = 230VAC, L Line
Date: 28.DEC.2016
Att 10 dB
dBµV
100
CLRWR
CLRWR
120
1 MHz
RBW
9 kHz
MT
20 ms
150 kHz
30 MHz
Conducted EMI
16:32:01
VIN = 230VAC, N Line
Date: 28.DEC.2016
Att 10 dB
PREAMP OFF
dBµV
10 MHz
120
1 MHz
RBW
9 kHz
MT
20 ms
PREAMP OFF
10 MHz
110
110
SGL
SGL
1 PK
1 PK
100
2 AV
100
CLRWR
CLRWR
90
2 AV
TDS
CLRWR
90
TDS
CLRWR
80
80
70
70
EN55022Q
EN55022Q
60
60
EN55022A
EN55022A
6DB
50
40
30
30
20
20
10
10
0
0
150 kHz
Date: 28.DEC.2016
6DB
50
40
30 MHz
16:38:43
150 kHz
Date: 28.DEC.2016
30 MHz
16:35:45
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MP024-10 – PRIMARY-SIDE CC/CV REGULATOR
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
Performance waveforms are tested on the evaluation board in the Design Example section.
VIN = 230VAC, VOUT = 5V, IOUT=2A, unless otherwise noted.
Steady State
VIN = 265VAC
Power On
VIN = 265VAC
CH1: VDS-PRI
CH1:VDS-PRI
200V/div.
200V/div.
CH2: VD-SEC
CH2: VD-SEC
20V/div.
20V/div.
4μs/div.
10ms/div.
OLP Entry
OLP Recovery
CH1:VDS-PRI
CH1: VDS-PRI
200V/div.
200V/div.
CH2: VCC
CH2: VCC
10V/div.
10V/div.
CH3: VOUT
CH3: VOUT
5V/div.
5V/div.
400ms/div.
400ms/div.
OLP Power On
Short-Circuit Entry
CH1: VDS-PRI
CH1:VDS-PRI
200V/div.
200V/div.
CH2: VCC
CH2: VCC
10V/div.
10V/div.
CH3: VOUT
CH3: VOUT
5V/div.
5V/div.
400ms/div.
400ms/div.
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MP024-10 – PRIMARY-SIDE CC/CV REGULATOR
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
Performance waveforms are tested on the evaluation board in the Design Example section.
VIN = 230VAC, VOUT = 5V, IOUT = 2A, unless otherwise noted.
Short-Circuit Recovery
Short-Circuit Power On
CH1: VDS-PRI
CH1:VDS-PRI
200V/div.
200V/div.
CH2: VCC
CH2: VCC
10V/div.
10V/div.
CH3: VOUT
CH3: VOUT
5V/div.
5V/div.
400ms/div.
400ms/div.
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MP024-10 – PRIMARY-SIDE CC/CV REGULATOR
BLOCK DIAGRAM
Vcc
Start-Up Unit
Power
Management
DRAIN
OCkP, OVP, OLP
Driving Signal
Management
FB
Constant Voltage
Control
Constant Current
Control
CS
CP
Comparator
Cable
Compensation
SOURCE
GND
Figure 1: Functional Block Diagram
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MP024-10 – PRIMARY-SIDE CC/CV REGULATOR
Ipk
OPERATION
The MP024-10 is a primary-side flyback
regulator that provides accurate constant
voltage and constant current regulation without
an optocoupler or secondary feedback circuit.
The regulator is designed to operate with a
minimal number of external components.
Start-Up
Initially, the IC is self-supplied by the internal
high-voltage current source, which is drawn
from DRAIN. The internal high-voltage current
source turns off for better efficiency once VCC
reaches the VCC on threshold (VCCH). Afterward,
the power supply is taken over by the auxiliary
winding of the transformer. When VCC falls
below the VCC off threshold (VCCL), the IC stops
switching, and the internal high-voltage current
source turns on again (see Figure 2).
Vcc
Regulation Occurs Here
Auxiliary Winding Takes Charge
Ip
0
Figure 3: Primary Current Waveform
When the current Ip(t) rises up to Ipk, the
MOSFET turns off. Calculate Ipk with Equation
(2):
Ipk
VIPK
RS
(2)
The energy stored in the inductor (Lm) within
each cycle can be calculated with Equation (3):
E
1
2
Lm Ipk
2
(3)
The power transferred from the input to the
output can be calculated with Equation (4):
VCCH
VCCL
P
1
2
Lm Ipk
fs
2
(4)
Where fs is the switching frequency.
Drain
In constant current operation, the reference for
Ipk is fixed at VLimit-Max. In constant voltage
operation, Ipk is modulated by the switching
frequency (see Figure 4).
Switching Pluses
High voltage
current source
VIPK
ON
VLimit-Max
OFF
VLimit-Min
Figure 2: VCC Under-Voltage Lockout
Peak-Current Control on the Primary Side
A current sense resistor (RS) is used to sense
the primary current Ip(t) (see Figure 3). The
current rises linearly at a rate shown in
Equation (1):
dIp (t)
dt
Vin
Lm
(1)
fS-min
fS_L
fS_H
fS
Figure 4: Peak Current Modulation
The turn-on time is limited at tONmax in case the
current sensing resistor is shorted and the
primary current runs away. If this maximum
limitation is reached, IC protection is triggered.
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MP024-10 – PRIMARY-SIDE CC/CV REGULATOR
Constant Voltage (CV) Operation
In constant voltage (CV) mode, the MP024-10
detects the output voltage from FB and
generates the switching frequency to regulate
the output voltage.
To regulate the output voltage on the primary
side, FB uses a resistor divider to sample the
auxiliary winding voltage (Vaux). The relationship
between Vaux and the output voltage (Vo) can be
calculated with Equation (5):
Vaux
Naux
(VO VD )
Ns
Constant Current (CC) Operation
Figure 7 shows the secondary
waveforms.
During the conduction time of the secondary
diode, the difference between the output
voltage and the voltage on the secondary
winding is not constant, since VD varies with the
current flowing through the diode. To
compensate for the voltage drop difference, the
sampling time decreases gradually from tFBS-Max
to tFBS-Min as the current limitation folds back
from VLimit-Max to VLimit-Min (see Figure 5).
Sampling Point
Iout
0
tons
T
Figure 7: Secondary Current Waveform
In constant current (CC) operation, Ipk is fixed,
and the CC loop control function maintains a
fixed ratio between the secondary diode on time
(tons) and the switching cycle. The fixed ratio
limits the maximum duty of the secondary side
diode on time as shown in Equation (6):
t ons
DS Max
T
tFBS-max for VLimit-Max
tFBS-min for
VLimit-Min
tons
Figure 5: Auxiliary Winding Voltage
The FB sampling time is able to be customized
with different resistor values connected to SS
(see
Figure
6).
See
the
Electrical
Characteristics table on page 5 for all available
choices for the sampling time. The entire
customization process is completed before
start-up and stored in a register, so it does not
have any influence on the normal operation.
SS
RSS
(6)
The relationship between the output constantcurrent and the secondary peak current (Ipks) is
shown in Equation (7):
Iout
0V
current
Is
(5)
Where VD is the forward drop voltage of the
secondary diode.
Sampling Point
The sampling should be chosen almost at the
end of the secondary diode conduction period
for accurate CV regulation.
t ons
1
1
Ipks
IpksDS Max
2
t ons t offs 2
(7)
When the secondary diode is turned on, the
peak current on the secondary side can be
calculated with Equation (8):
Ipks
Np
NS
IPK
(8)
The output current regulation is shown in
Equation (9):
Iout
1 Np
IPKDS Max
2 NS
(9)
For different applications with different kinds of
output voltages, DS-Max can be customized from
CP. If CP is connected with a capacitor directly
or shorted to GND, DS-Max remains at a default
value of 0.4.
Figure 6: External Resistor for Sampling Time
Customization
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MP024-10 – PRIMARY-SIDE CC/CV REGULATOR
If CP is connected with a resistor, then there
are several options for the CP and DS-Max
combination (see Figure 8).
RCP
CP
Figure 8: External Configuration of CP
Table 1 shows all available choices for DS-Max.
The entire customization process is completed
before start-up and latched in a register, so it
does not have any influence on the normal
operation.
Table 1: DS-Max vs. CP Configuration
RCP/CCP
0Ω/NC
10kΩ/NC
20kΩ/NC
40kΩ/NC
NC/1μF
DS-Max
0.4
0.3
0.35
0.5
0.4
To enable the overload protection (OLP)
function in CC mode, the sampling on the FB
voltage should be running, and the sampling
time should be fixed at tFBS-Max.
Leading-Edge Blanking
The MP024-10 uses a leading-edge blanking
period when the MOSFET turns on. Leadingedge blanking is used to prevent a false
termination of the switching pulse caused by
the turn-on current spike. During this blanking
period, the current sense comparator is
disabled, and the MOSFET cannot be turned
off.
Discontinuous Conduction Mode (DCM)
Detection
The MP024-10 is designed to operate in
discontinuous conduction mode (DCM) in both
CV and CC modes. To avoid operating in
continuous conduction mode (CCM), the
MP024-10 implements a zero-current detection
function internally with a threshold of VDCM. The
IC does not begin the next cycle until ZCD is
detected.
During normal operation, the blanking time for
ZCD is synchronized with the FB sampling time
(i.e.: ZCD always starts after the sampling
phase is done). There is also a soft-start (SS)
function on the ZCD blanking time that prevents
ZCD from being falsely triggered when the
output capacitor is not charged up. During the
start-up period, the blanking time for ZCD
gradually shrinks from tB_STP (10μs) to the FB
sampling time in three cycles.
Protection Features (OVP, OCkP, SSP, and
OLP)
The MP024-10 includes over-voltage protection
(OVP), open-circuit protection (OCkP), sensingshort protection (SSP), and overload protection
(OLP). If the voltage at FB exceeds VFBovp, OVP
is triggered. If VFBopen cannot be monitored for
each cycle, OCkP is triggered. If the maximum
turn on time is reached, SSP is triggered. If the
sampled FB voltage is lower than VFBolp for 128
consecutive cycles, OLP is triggered. The
MP024-10 immediately shuts down the driving
signals and enters hiccup mode when any of
these protection features are triggered and
resumes normal operation when the fault has
been removed.
OLP is not enabled until the soft-start period of
the ZCD blanking time is finished.
Over-Temperature Protection (OTP)
When the junction temperature of the IC
exceeds the thermal shutdown threshold, overtemperature protection (OTP) is triggered, and
the IC stops switching. The MP024-10 resumes
normal operation when the junction temperature
drop exceeds the thermal shutdown hysteresis.
Output Cable Compensation
The MP024-10 has an internal output cable
compensation circuit (see Figure 9). A switching
signal (VLimit*tONS) is generated internally and is
synchronized with the switching frequency. The
duty on time of this signal is tONS, and the
amplitude of this signal is proportional to the
current limit threshold. The switching signal is
output to CP through a 1MΩ resistor. A lowpass filter can be implemented by placing an
external capacitor on CP, and a DC voltage
(VCP) that is proportional to the output current
can be derived on CP.
An internal current sinking into FB is
proportional to VCP, so the voltage drop on the
upper resistor of the divider implements the
output cable compensation function.
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MP024-10 – PRIMARY-SIDE CC/CV REGULATOR
VLimit*tons
CP
CCP
- +
FB
Figure 9: Output Cable Compensation
Determine the compensation
Equation (10):
VFCP
voltage
8 VLimit DS
N
2 RUP S
3
300 10
NP _ AU
with
(10)
Where
VFCP
is
the
secondary-side
compensation voltage drop, DS is the
secondary-diode duty cycle, RUP is the upper
resistor of the resistor divider, NS is the number
of turns for the secondary-side transformer
windings, NP_AU is the number of transformer
auxiliary winding turns, and VLimit is the current
limit.
For example, to calculate the maximum output
cable compensation in CC condition, use DS =
DS-Max (when CP function is used, DS-Max is 0.4)
and VLimit = VLimit-Max (typically 480mV) in the
formula. The compensation voltage drops as
VLimit or DS decrease along with the load current.
The CP voltage is 8*VLimit*DS.
Connect a 1µF capacitor to CP for cable
compensation. Since CP is also used for DS-Max
customization, the cable compensation function
is only available when CP is connected to the
capacitors directly. If there is any non-zero
resistor connected to CP, all of the internal
blocks related to the cable compensation
function are disabled and there is no current
sinking into FB.
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MP024-10 – PRIMARY-SIDE CC/CV REGULATOR
APPLICATION INFORMATION
Input Filter
The input filter helps to maintain the bus voltage
when the AC input voltage is low.
Figure 10 shows the typical input filter of an
application with a low power range. The bulk
capacitors (C1 and C2) filter the rectified AC
input. Usually, C1 and C2 are set at 2µF/W to
3µF/W for a universal input condition. For
230VAC single-range applications, cut the
capacitor values in half. The inductor (L) forms
a pi (π) filter with C1 and C2 to restrain the
differential mode EMI noise. The resistor (R) in
parallel with L dampens the mid-frequency
band EMI noise, if necessary. Normally, R is
1kΩ to 10kΩ.
Figure 11 shows the typical DC bus voltage
waveform after the rectifier.
L
+
R
C2
C1 +
AC Input
+
DC Input
Output Capacitor
Low or very low ESR output capacitors are
recommended to meet the output voltage ripple
requirements. Low ESR capacitors improve the
output voltage regulation accuracy at high or
low temperatures and can provide better
efficiency than high ESR output capacitors.
Output Diode Or Synchronous Rectifier
Schottky diodes are recommended for their fast
switching speed and low forward voltage drop
for better high or low temperature CV regulation
and efficiency.
If lower average efficiency (3% to 4%) is
acceptable, replace the output diode with a fast
or ultra-fast diode to reduce cost. Re-adjust the
resistor divider values for an accurate output
voltage since the forward voltage drop is higher
than the Schottky diode.
If the circuit has a high efficiency requirement, it
is recommended to use a synchronous rectifier
(SR) instead. The MP6906 is a suitable SR
controller where the output voltage is low and
there is no need for a secondary auxiliary
winding (see Figure 12). The MP6906 is
available in a SOT23-6 package, which only
requires few extra PCB dimensions and
external components.
Figure 10: Input Filter
V in
T1
Np
Vout
Ns
VDC(max)
DC input voltage
M
AGND
VG
Naux
V DC(min)
AGND
MP6906
RD
AC input voltage
VAC
4
t
VDD
R LL
CL L
6
LL
PGND
VSS
VG
Figure 11: DC Input Voltage Waveform
A low DC input voltage causes insufficient
output current due to the maximum on-duty
limitation of the secondary side. To prevent this,
calculate the minimum input DC voltage with
Equation (11):
VDC(min)
Np
Ns
(VO VD )
DS Max
1 DS Max
3
2
1
VG
0
VD
V CC
5
(11)
If VDC(min) cannot satisfy this expression, use
larger input capacitors to increase VDC(min).
AGND
AGND
Figure 12: Synchronous Rectifier
Leakage Inductance
The
transformer’s
leakage
inductance
decreases system efficiency and affects either
the output current or voltage constant precision.
The transformer structure can be optimized to
minimize the leakage inductance. The leakage
inductance should be less than 5% of the
primary inductance.
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MP024-10 – PRIMARY-SIDE CC/CV REGULATOR
RCD Snubber
The transformer’s leakage inductance causes
MOSFET drain voltage spikes and excessive
ringing on the drain voltage waveform, which
affects the output voltage sampling after the
primary MOSFET turns off.
The damping resistor in series with the RCD
has a relatively large value to prevent any
excessive voltage ringing that can affect the CV
sampling and increase the output ripple. Use a
damping resistor value in the range of 100Ω to
500Ω to restrain the drain voltage ringing.
The RCD snubber circuit limits the drain voltage
spike (see Figure 13).
Resistor Divider
For better application performance, select the
resistor divider’s total value with in the range of
10kΩ to 100kΩ. Smaller resistors will draw
larger current from the auxiliary winding, which
increases the no-load consumption, and larger
resistors may pick up noise from adjacent
components.
-
CSN
RSN
VSN
*
+
+
LM
DSN
*
R
LK
Figure 13: RCD Snubber
Select an appropriate RSN and CSN value to
meet voltage spike requirements and improve
system operation.
If there is oscillation or noise disturbing the FB
sampling, an R-C filter can be inserted between
the resistor divider and FB to achieve a stable
voltage. The CFB value is recommended to be
several pF, and RFB is recommended to be
between 1kΩ and 2kΩ. RFB can also limit
substrate injection current effects (see Figure
14).
The power dissipated in the snubber circuit can
be approximated with Equation (12):
PSN
VSN
1
LKIPK 2
fS
2
VSN NPS VO
RUP
(12)
RFB
FB
Where LK is the leakage inductance, VSN is the
clamp voltage, and NPS is the turn ratio of the
primary-to-secondary side.
CFB
RDOWN
Since RSN consumes the majority of the power,
calculate RSN with Equation (13):
RSN
VSN2
PSN
(13)
The maximum ripple of the snubber capacitor
voltage is then calculated with Equation (14):
VSN
VSN
CSNRSN fS
(14)
Generally, a 15% ripple is reasonable.
Select a time constant (t = RSN ·CSN) below
0.1ms for better CV sampling. Calculate CSN
using Equation (14).
The RCD resistor is a trade-off between the
power loss and the acceptable clamp voltage in
practical applications.
Figure 14: Feedback Resistor Divider Circuit
For accurate CV regulation, the accuracy of
these feedback resistors should be at least 1%.
Dummy Load
When the system operates without any load,
the output voltage rises above the normal
operation because of the minimum switching
frequency limitation. Use a dummy load for
good load regulation. The dummy load is a
trade-off between efficiency and load regulation.
For example, a large dummy load can
deteriorate efficiency and no-load consumption.
For most applications, a dummy load of several
mW is reasonable.
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MP024-10 – PRIMARY-SIDE CC/CV REGULATOR
Maximum Switching Frequency
The maximum switching frequency should be
limited by the sampling point. The relationship
between RSS and the sampling time point is
shown in the Electrical Characteristics table on
page 5. The secondary on time must be longer
than the maximum TFBS-Max. Calculate TS_ON with
Equation (15):
TS _ ON IPK
NS LM
tFBS _ Max tFB _ SD
NP (VO VD )
9. Use a single-point connection at the
negative terminal of the input filter capacitor
for the IC GND and bias winding return.
(15)
Where TFBS-Max is the FB maximum sampling
time, and tFB_SD is the FB sampling duration.
Top Layer
Combine Equation (14) and the relationship of
RCP and DS-Max shown in Table 1 to fix the
maximum switching frequency.
PCB Layout Guidelines
Efficient PCB layout is critical for stable
operation, good EMI, and good thermal
performance. For best results, refer to Figure
15 and follow the guidelines below.
1. Minimize the loop area formed by the input
capacitor, the transformer’s primary winding,
the MOSFET drain and source of the
MP024-10, and the sensing resistor to
reduce EMI noise.
2. Minimize the voltage jumping area, such as
the MOSFET drain, the anode of the
secondary diode, etc. for better EMI.
3. Minimize the clamp circuit loop to reduce
EMI.
4. Minimize the secondary loop area of the
output diode and output filter to reduce EMI
noise.
5. Provide sufficient copper areas at the
cathode terminal of the output diode to act
as a heat sink.
Bottom Layer
Figure 15: Recommended Layout
Design Example
Table 2 shows a design example following the
application guidelines.
Table 2: Design Example
VIN
VOUT
IOUT
85Vac~265Vac, 47Hz/63Hz
5V
2A
Figure 16 shows the detailed application
schematic. For more device applications, please
refer to the related evaluation board datasheets.
6. Place the AC input away from the switching
nodes to minimize any noise coupling that
may bypass the input filter.
7. Place the bypass capacitor as close to the
IC as possible.
8. Place the feedback resistors next to FB and
minimize the feedback sampling loop to
minimize noise coupling.
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MP024-10 – PRIMARY-SIDE CC/CV REGULATOR
TYPICAL APPLICATION CIRCUIT
1mH
R3
100kΩ/1206
10kΩ/0805
C3
1nF/1206
CR1
4.7
90VAC~265VAC
C1
10µF/400V
C8
560µF
B
C13
560µF
C11
1µF/10V
R9
5.1kΩ
5V/2A
1
D1
FR107
1000V/1A
C2
10µF/400V
600V/0.5A
Vout
45V/10A
Nsec
Np
4
FR1
C7
1nF
D3
A
5
R1
L
R7
10Ω/1206
EPC17
Lp=1.2mH
Np:Np_au:Nsec=115:15:6
T1
L1
AGND
Np_au
N
2
R2
100Ω/1206
AGND
PGND
PGND
D2
R5
30.9kΩ/1%
PGND
1nF
CY1
AGND
R4
0Ω
1
2
U1
FB
GND
VCC
CP
SS
PGND
8
7
C9
6
100nF
C6
22µF
R6
13kΩ/1%
4
DRAIN
SOURCE
C10
10pF
5
MP024-10/SO8-7
R10
1.8Ω/1206
1%
PGND
R11
0Ω
C5
1µF
R12
NC
R13
1.2Ω/1206
1%
PGND
Figure 16: Universal Input, 5V/2A Output
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MP024-10 – PRIMARY-SIDE CC/CV REGULATOR
FLOW CHART
Start
HV Supply On
Y
N
VCC > VCCH?
Y
VCC < VCCL?
N
HV Supply Off
Normal Operation
Monitor VFB
CC Loop
Operation
N
CV Loop
Operation?
N
VFB > VFBovp?
VFB > VFBopen
(entire cycle)?
Y
Y
OVP,
Stop Switching
OCkP,
Stop Switching
Y
CV Loop
Operation
N
Y
End
Figure 17: Flow Chart
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MP024-10 – PRIMARY-SIDE CC/CV REGULATOR
SIGNAL TIMING SEQUENCE WAVEFORM
Vout
Rated
Value
CC_Charge
VDD
3.75V
CC_ON
CV_Charge
Vcomp
CV_ON
Current
Sense
VLimit
CC Mode Operation
CV Mode Operation
Figure 18: Start-Up Sequence
VCCH
VCC
VCCL
High IHV
Voltage
Current
Source
Driver
VFBovp
FB VFB
Over Voltage
Occurs
VFBopen
Over Temperature
Occurs
Open Circuit
Occurs
Fault
Flag
OVP
OCkP
OTP
Figure 19: Protection Sequence
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MP024-10 – PRIMARY-SIDE CC/CV REGULATOR
PACKAGE INFORMATION
SOIC8-7B
0.189(4.80)
0.197(5.00)
8
0.050(1.27)
0.024(0.61)
5
0.063(1.60)
0.150(3.80)
0.157(4.00)
PIN 1 ID
1
0.228(5.80)
0.244(6.20)
0.213(5.40)
4
TOP VIEW
RECOMMENDED LAND PATTERN
0.053(1.35)
0.069(1.75)
SEATING PLANE
0.004(0.10)
0.010(0.25)
0.013(0.33)
0.020(0.51)
0.050(1.27)
BSC
0.0075(0.19)
0.0098(0.25)
SEE DETAIL "A"
SIDE VIEW
FRONT VIEW
0.010(0.25)
x 45o
0.020(0.50)
GAUGE PLANE
0.010(0.25) BSC
0o-8o
0.016(0.41)
0.050(1.27)
DETAIL "A"
NOTE:
1) CONTROL DIMENSION IS IN INCHES. DIMENSION IN
BRACKET IS IN MILLIMETERS.
2) PACKAGE LENGTH DOES NOT INCLUDE MOLD FLASH
,
PROTRUSIONS, OR GATE BURRS.
3) PACKAGE WIDTH DOES NOT INCLUDE INTERLEAD FLASH
OR PROTRUSIONS.
4) LEAD COPLANARITY(BOTTOM OF LEADS AFTER FORMING)
SHALL BE0.004" INCHES MAX.
5) JEDEC REFERENCE IS MS-012.
6) DRAWING IS NOT TO SCALE.
NOTICE: The information in this document is subject to change without notice. Users should warrant and guarantee that third
party Intellectual Property rights are not infringed upon when integrating MPS products into any application. MPS will not
assume any legal responsibility for any said applications.
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