NB669
24V, High Current
Synchronous Buck Converter With LDO
END OF LIFE
DESCRIPTION
FEATURES
The NB669 is a fully integrated high frequency
synchronous rectified step-down switch mode
converter with 5V fixed output voltage. It offers
very compact solution to achieve 6A continuous
output current and 9A peak output current over
a wide input supply range with excellent load
and line regulation. The NB669 operates at high
efficiency over a wide output current load
range.
Constant-On-Time
(COT)
control
mode
provides fast transient response and eases loop
stabilization.
Under voltage lockout is internally set as 4.15
V. An open drain power good signal indicates
the output is within its nominal voltage range.
Wide 6.5V to 24V Operating Input Range
5V Fixed Output Voltage
Built-in 5V, 100mA LDO with Switches
6A Continuous Output Current
9A Peak Output Current
300kHZ CLK for External Charge Pump
Low RDS(ON) Internal Power MOSFETs
Proprietary Switching Loss Reduction
Technique
Internal Soft Start
Output Discharge
500kHZ Switching Frequency
OCP, OVP, UVP Protection and Thermal
Shutdown
Latch off Reset via EN or Power Cycle.
NB669 also provides a 5V LDO, which can be
used to power the external peripheries, such as
the keyboard controller in the laptop computer.
A 300kHz CLK is also available; its output can
be used to drive an external charge pump,
generating gate drive voltage for the load
switches without reducing the main converter’s
efficiency.
APPLICATIONS
Full protection features include OCP, OVP,
UVP and thermal shut down.
All MPS parts are lead-free and adhere to the RoHS directive. For MPS green
status, please visit MPS website under Products, Quality Assurance page.
The converter requires minimum number of
external components and is available in QFN16
(3mmx3mm) package.
Laptop Computer
Tablet PC
Networking Systems
Personal Video Recorders
Flat Panel Television and Monitors
Distributed Power Systems
“MPS” and “The Future of Analog IC Technology” are registered trademarks of
Monolithic Power Systems, Inc.
TYPICAL APPLICATION
NB669 Rev. 1.03
8/27/2014
www.MonolithicPower.com
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© 2014 MPS. All Rights Reserved.
1
NB669, 24V, HIGH CURRENT SYNCHRONOUS BUCK CONVERTER WITH LDO
END OF LIFE
ORDERING INFORMATION
Part Number*
Package
Top Marking
NB669GQ
QFN16 (3mmx3mm)
AEV
* For Tape & Reel, add suffix –Z (e.g. NB669GQ–Z)
PACKAGE REFERENCE
TOP VIEW
VIN
AGND
EN
14
13
ENLDO VCC
12
11
BST
10
1
15 SW
PGND
9
SW
8
SW
2
16 SW
3
4
5
6
7
NC
PG
CLK
LDO
VOUT
EXPOSED PAD
ON BACKSIDE
ABSOLUTE MAXIMUM RATINGS (1)
Supply Voltage VIN .......................................24V
VSW ....................................... -0.3V to VIN + 0.3V
VSW (30ns) ..................................-3V to VIN + 4V
VSW (5ns) ..................................... -6V to VIN+4V
VBST .................................................. VSW + 5.5V
VEN ..............................................................12V
Enable Current IEN(2)................................ 2.5mA
All Other Pins .............................. -0.3V to +5.5V
Continuous Power Dissipation (T A=+25°C) (3)
QFN16……………………..….…..…………1.8W
Junction Temperature .............................. 150C
Lead Temperature ................................... 260C
Storage Temperature ............... -65C to +150C
NB669 Rev. 1.03
8/27/2014
Recommended Operating Conditions
(4)
Supply Voltage VIN .......................... 6.5V to 22V
Output Voltage VOUT ...................................... 5V
Enable Current IEN...................................... 1mA
Operating Junction Temp. (TJ)..-40°C to +125°C
Thermal Resistance
(5)
θJA
θJC
QFN16 (3mmx3mm)............... 70 ...... 15 ... C/W
Notes:
1) Exceeding these ratings may damage the device.
2) Refer to Page 11 of Configuring the EN Control.
3) The maximum allowable power dissipation is a function of the
maximum junction temperature TJ(MAX), the junction-toambient thermal resistance θJA, and the ambient temperature
TA. The maximum allowable continuous power dissipation at
any ambient temperature is calculated by PD(MAX)=(TJ(MAX)TA)/θJA. Exceeding the maximum allowable power dissipation
will cause excessive die temperature, and the regulator will go
into thermal shutdown. Internal thermal shutdown circuitry
protects the device from permanent damage.
4) The device is not guaranteed to function outside of its
operating conditions.
5) Measured on JESD51-7, 4-layer PCB.
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NB669, 24V, HIGH CURRENT SYNCHRONOUS BUCK CONVERTER WITH LDO
END OF LIFE
ELECTRICAL CHARACTERISTICS
VIN = 12V, TJ = 25C, unless otherwise noted.
Parameters
Symbol
Condition
Min
Typ
Max
Units
1
2
μA
220
300
μA
Supply Current
Supply Current (Shutdown)
IIN_Shtdn
Supply Current (Quiescent)
IIN
Supply Current (No Load)
IIN
Supply Current (Standby)
IIN_Stby
VEN = 0V
VEN = 2V, VENLDO = 2V ,
VOUT = 5.2V
VEN = 2V, VENLDO = 2V ,
VOUT = 5.05V, Io=0A
VEN = 0V, VENLDO = 2V ,
ILDO = 0A
140
240
40
80
μA
120
μA
MOSFET
High-side Switch On Resistance
HSRDS-ON
30
mΩ
Low-side Switch On Resistance
LSRDS-ON
15
mΩ
Switch Leakage
SW LKG
VEN = 0V, VSW = 0V
0
1
μA
8
8.5
9.5
A
400
500
600
kHz
Current Limit
Low-side Valley Current Limit
ILIMIT
Switching frequency and minimum off timer
Switching Frequency
Minimum Off
Time(6)
FSW
TOFF
350
ns
Over-voltage and Under-voltage Protection
OVP Threshold
VOVP
OVP Delay(6)
125
TOVPDEL
UVP Threshold
135
2.5
VUVP
UVP Delay(6)
130
55
TUVPDEL
60
65
8
%
VOUT_Ref
μs
%
VOUT_Ref
μs
VOUT_Ref And Soft Start
VOUT Ref Voltage
Soft Start Time
VOUT_Ref
TSS
4.95
1.5
5.05
1.8
5.15
1.95
V
ms
VILEN
VEN-HYS
1.15
1.25
100
5
0
1.25
1.35
V
mV
Enable And UVLO
Enable Input Low Voltage
Enable Hysteresis
Enable Input Current
Enable LDO Input Low Voltage
Enable LDO Hysteresis
NB669 Rev. 1.03
8/27/2014
IEN
VENLDO
VENLDO-HYS
VEN = 2V
VEN = 0V
1.15
100
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© 2014 MPS. All Rights Reserved.
μA
1.35
V
mV
3
NB669, 24V, HIGH CURRENT SYNCHRONOUS BUCK CONVERTER WITH LDO
END OF LIFE
ELECTRICAL CHARACTERISTICS
(continued)
VIN = 12V, TJ = 25C, unless otherwise noted.
Parameters
Symbol
VCC Under Voltage Lockout
Threshold Rising
VCC Under Voltage Lockout
Threshold Hysteresis
Condition
Min
Typ
Max
Units
VCCVth
4.65
4.85
V
VCCHYS
500
mV
CLK Output
CLK Output High Level Voltage
CLK Output Low Level Voltage
VCLKH
VCLKL
IVclk= -5mA
IVclk= 5mA
CLK Frequency
FCLK
TJ = 25C
4.75
0
4.95
0.05
5.15
0.1
300
V
V
kHz
LDO Regulator
LDO Regulator
LDO Load Regulation
VLDO
ILDO =50mA
Before switch-over
LDO Load capability
Switch Rdson
4.95
RSwitch
After switch-over
ILDO =50mA
70
5.1
5
90
5.25
120
V
%
mA
1.3
2
mA
Ω
5.2
5.4
V
100
VCC Regulator
VCC Regulator
VCC
VCC Load Regulation
5
Icc=5mA
5
%
Power Good
PG Rising (Good)
PG Falling (Fault)
PG Rising (Fault)
PG Falling (Good)
Power Good Lower to High Delay
Power Good Sink Current
Capability
Power Good Leakage Current
Thermal Protection
Thermal Shutdown (6)
Thermal Shutdown Hysteresis
PGVth-Hi
PGVth-Lo
PGVth-Hi
PGVth-Lo
PGTd
95
85
115
105
0.5
%
VOUT_Ref
ms
VPG
Sink 4mA
0.4
V
IPG_LEAK
VPG = 3.3V
100
nA
TSD
150
25
°C
°C
Note:
6) Guaranteed by design.
NB669 Rev. 1.03
8/27/2014
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© 2014 MPS. All Rights Reserved.
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NB669, 24V, HIGH CURRENT SYNCHRONOUS BUCK CONVERTER WITH LDO
END OF LIFE
PIN FUNCTIONS
PIN #
Name
1
VIN
2
3
PGND
NC
4
PG
5
CLK
6
LDO
7
VOUT
8, 9
Exposed Pad
15, 16
SW
10
BST
11
VCC
12
ENLDO
13
EN
14
AGND
NB669 Rev. 1.03
8/27/2014
Description
Supply Voltage. The VIN pin supplies power for internal MOSFET and regulator. The
NB669 operates from a +6.5V to +24V input rail. An input capacitor is needed to
decouple the input rail. Use wide PCB traces and multiple vias to make the
connection.
Power Ground. Use wide PCB traces and multiple vias to make the connection.
Not connected.
Power good output. The output of this pin is an open drain signal and is high if the
output voltage is higher than 95% of the nominal voltage. There is a delay from Vout
≥ 95% to PGOOD goes high.
300kHZ CLK output to drive the external charge pump
Internal 5V LDO output. Decouple with a minimum 4.7µF ceramic capacitor as close
to the pin as possible. X7R or X5R grade dielectric ceramic capacitors are
recommended for their stable temperature characteristics.
Once the output voltage of the Buck regulator is ready, it will switch over the LDO
output to save the power loss.
Output voltage sense. For the NB669, the output of the Buck regulator is fixed to 5V.
VOUT pin is used to sense the output voltage of the Buck regulator, connect this pin
to the output capacitor of the regulator directly. This pin also acts as the input of the
5V LDO switch over power input.
Keep the VOUT sensing trace far away from the SW node. Vias should also be
avoided on the VOUT sensing trace.
Switch Output. Connect this pin to the inductor and bootstrap capacitor. This pin is
driven up to the VIN voltage by the high-side switch during the on-time of the PWM
duty cycle. The inductor current drives the SW pin negative during the off-time. The
on-resistance of the low-side switch and the internal diode fixes the negative
voltage. Use wide and short PCB traces to make the connection. Try to minimize the
area of the SW pattern.
Bootstrap. A capacitor connected between SW and BST pins is required to form a
floating supply across the high-side switch driver.
Internal 5V LDO output. The driver and control circuits are powered from this
voltage. Decouple with a minimum 1µF ceramic capacitor as close to the pin as
possible. X7R or X5R grade dielectric ceramic capacitors are recommended for their
stable temperature characteristics.
100mA LDO and VCC enable pin. ENLDO is internally pulled up to high. Leave this
pin open to enable the LDO. Drive it low to turn off all the regulators.
Buck regulator and charge pump clock enable pin. EN is a digital input that turns the
Buck regulator and CLK on or off. When the power supply of the control circuit is
ready, drive EN high to turn on the Buck regulator and charge pump clock, drive it
low to turn them off.
Analog ground. The internal reference is referred to AGND.
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NB669, 24V, HIGH CURRENT SYNCHRONOUS BUCK CONVERTER WITH LDO
END OF LIFE
TYPICAL PERFORMANCE CHARACTERISTICS
Performance waveforms are tested on the evaluation board of the Design Example section.
VIN=12V, VOUT =5V, L=2µH, TJ=+25°C, unless otherwise noted.
NB669 Rev. 1.03
8/27/2014
www.MonolithicPower.com
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© 2014 MPS. All Rights Reserved.
6
NB669, 24V, HIGH CURRENT SYNCHRONOUS BUCK CONVERTER WITH LDO
END OF LIFE
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
Performance waveforms are tested on the evaluation board of the Design Example section.
VIN=12V, VOUT =5V, L=2µH, TJ=+25°C, unless otherwise noted.
NB669 Rev. 1.03
8/27/2014
www.MonolithicPower.com
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© 2014 MPS. All Rights Reserved.
7
NB669, 24V, HIGH CURRENT SYNCHRONOUS BUCK CONVERTER WITH LDO
END OF LIFE
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
Performance waveforms are tested on the evaluation board of the Design Example section.
VIN=12V, VOUT =5V, L=2µH, TJ=+25°C, unless otherwise noted.
NB669 Rev. 1.03
8/27/2014
www.MonolithicPower.com
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© 2014 MPS. All Rights Reserved.
8
NB669, 24V, HIGH CURRENT SYNCHRONOUS BUCK CONVERTER WITH LDO
END OF LIFE
BLOCK DIAGRAM
VCC
VIN
BST
BSTREG
Softstart
POR &
Reference
VIN
VOUT
0.6V V REF
On Time
One Shot
VFB
Gate
control
Logic
Min off time
EN
SW
VOUT
1V
PGND
SW
OCP
PG
OVP
130% VREF
Fault
logic
POK
95% VREF
CLK
CLK
generator
AGND
UVP
60% VREF
Vcc
VOUT
Vcc
Regulator
LDO
Switch-over
LDO
Control
VIN
ENLDO
LDO
Figure 1—Functional Block Diagram
NB669 Rev. 1.03
8/27/2014
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NB669, 24V, HIGH CURRENT SYNCHRONOUS BUCK CONVERTER WITH LDO
END OF LIFE
OPERATION
PWM Operation
The NB669 is fully integrated synchronous
rectified step-down switch mode converter.
Constant-on-time (COT) control is employed to
provide fast transient response and easy loop
stabilization. At the beginning of each cycle, the
high-side MOSFET (HS-FET) is turned ON when
the feedback voltage (VFB) is below the reference
voltage (VREF), which indicates insufficient output
voltage. The ON period is determined by the
output voltage and input voltage to make the
switching frequency fairy constant over input
voltage range.
After the ON period elapses, the HS-FET is
turned off, or becomes OFF state. It is turned ON
again when VFB drops below VREF. By repeating
operation this way, the converter regulates the
output voltage. The integrated low-side MOSFET
(LS-FET) is turned on when the HS-FET is in its
OFF state to minimize the conduction loss. There
will be a dead short between input and GND if
both HS-FET and LS-FET are turned on at the
same time. It’s called shoot-through. In order to
avoid shoot-through, a dead-time (DT) is
internally generated between HS-FET off and LSFET on, or LS-FET off and HS-FET on.
An internal compensation is applied for COT
control to make a more stable operation even
when ceramic capacitors are used as output
capacitors, this internal compensation will then
improve the jitter performance without affect the
line or load regulation.
Heavy-Load Operation
When the output current is high and the inductor
current is always above zero amps, it is called
continuous-conduction-mode (CCM). The CCM
mode operation is shown in Figure 2 shown.
When VFB is below VREF, HS-FET is turned on for
a fixed interval. When the HS-FET is turned off,
the LS-FET is turned on until next period.
In CCM mode operation, the switching frequency
is fairly constant and it is called PWM mode.
Light-Load Operation
With the load decrease, the inductor current
decrease too. Once the inductor current touch
zero, the operation is transition from continuousconduction-mode (CCM) to discontinuousconduction-mode (DCM).
The light load operation is shown in Figure 3.
When VFB is below VREF, HS-FET is turned on for
a fixed interval which is determined by one- shot
on-timer as equation 1 shown. When the HS-FET
is turned off, the LS-FET is turned on until the
inductor current reaches zero. In DCM operation,
the VFB does not reach VREF when the inductor
current is approaching zero. The LS-FET driver
turns into tri-state (high Z) whenever the inductor
current reaches zero. A current modulator takes
over the control of LS-FET and limits the inductor
current to less than -1mA. Hence, the output
capacitors discharge slowly to GND through LSFET. As a result, the efficiency at light load
condition is greatly improved. At light load
condition, the HS-FET is not turned ON as
frequently as at heavy load condition. This is
called skip mode.
At light load or no load condition, the output
drops very slowly and the NB669 reduces the
switching frequency naturally and then high
efficiency is achieved at light load.
Figure 2—Heavy Load Operation
NB669 Rev. 1.03
8/27/2014
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NB669, 24V, HIGH CURRENT SYNCHRONOUS BUCK CONVERTER WITH LDO
END OF LIFE
Figure 5—Jitter in Skip Mode
Selecting the Output Capacitors
The traditional constant-on-time control scheme
is intrinsically unstable if output capacitor’s ESR
is not large enough as an effective current-sense
resistor. Ceramic capacitors usually can not be
used as output capacitor.
Figure 3—Light Load Operation
As the output current increases from the light
load condition, the time period within which the
current modulator regulates becomes shorter.
The HS-FET is turned ON more frequently.
Hence, the switching frequency increases
correspondingly. The output current reaches the
critical level when the current modulator time is
zero. The critical level of the output current is
determined as follows:
IOUT
(VIN VOUT ) VOUT
2 L FSW VIN
Figure 6 shows an equivalent circuit in PWM
mode with the HS-FET off. To realize the stability,
the ESR value should be chosen as follow:
RESR
TSW
T
ON
2
0.7
COUT
(2)
TSW is the switching period.
SW
L
(1)
It turns into PWM mode once the output current
exceeds the critical level. After that, the switching
frequency stays fairly constant over the output
current range.
Jitter and FB Ramp Slope
Jitter occurs in both PWM and skip modes when
noise in the VFB ripple propagates a delay to the
HS-FET driver, as shown in Figures 4 and 5.
Jitter can affect system stability, with noise
immunity proportional to the steepness of VFB’s
downward slope. However, VFB ripple does not
directly affect noise immunity.
VOUT
VOUT
R
ESR
FB
R
CAP
Figure 6—Simplified Circuit in PWM Mode
The NB669 has built in internal ramp
compensation to make sure the system is stable
even without the help of output capacitor’s ESR;
and thus the pure ceramic capacitor solution can
be applicant. The pure ceramic capacitor solution
can significantly reduce the output ripple, total
BOM cost and the board area.
Configuring the EN Control
The NB669 has two enable pins to control the
on/off of the internal regulators.
ENLDO is used to enable or disable the whole
Figure 4—Jitter in PWM Mode
NB669 Rev. 1.03
8/27/2014
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NB669, 24V, HIGH CURRENT SYNCHRONOUS BUCK CONVERTER WITH LDO
chip. Once ENLDO is off, all the regulators
include Vcc will be off. ENLDO is internally pulled
high so it can be floated in the normal operation.
When ENLDO is pulled high, Pull En high to turn
on the Buck regulator also the charge pump clk,
and pull EN low to turn them off. Do not float the
EN pin.
See Table1 for the logics to control the regulators
Table 1—ENLDO/EN Control
State ENLDO
S0
1
S3
1
S4/S5
0
Others
0
EN
1
0
0
1
VCC VOUT/CLK
ON
ON
ON
OFF
OFF
OFF
OFF
OFF
RUP RDOWN
(V)
RDOWN
(3)
For example, for RUP=150kΩ and RDOWN=51kΩ,
the VINSTART is set at 4.92V.
To avoid noise, a 10nF ceramic capacitor from
EN to GND is recommended.
There is an internal Zener diode on the EN pin,
which clamps the EN pin voltage to prevent it
from running away. The maximum pull up current
assuming a worst case 12V internal Zener clamp
should be less than 1mA.
Therefore, when EN is driven by an external logic
signal, the EN voltage should be lower than 12V;
when EN is connected with VIN through a pull-up
resistor or a resistive voltage divider, the
resistance selection should ensure the maximum
pull up current less than 1mA.
If using a resistive voltage divider and VIN higher
than 12V, the allowed minimum pull-up resistor
RUP should meet the following equation:
VIN (V) 12
12
1(mA)
RUP (k )
RDOWN (k )
NB669 Rev. 1.03
8/27/2014
RUP (k)
VIN (V) 12
1(mA)
(5)
A typical pull-up resistor is 499kΩ.
Soft Start
LDO
ON
ON
OFF
OFF
For automatic start-up the EN pin can be pulled
up to input voltage through a resistive voltage
divider. Choose the values of the pull-up resistor
(RUP from Vin pin to EN pin) and the pull-down
resistor (RDOWN from EN pin to GND) to
determine the automatic start-up voltage:
VIN START 1.25
END OF LIFE
Especially, just using the pull-up resistor RUP (the
pull-down resistor is not connected), the
VIN-START is determined by input UVLO, and the
minimum resistor value is:
(4)
The NB669 employs soft start (SS) mechanism
to ensure smooth output during power-up. When
the EN pin becomes high, the internal reference
voltage ramps up gradually; hence, the output
voltage ramps up smoothly, as well. Once the
reference voltage reaches the target value, the
soft start finishes and it enters into steady state
operation.
If the output is pre-biased to a certain voltage
during startup, the IC will disable the switching of
both high-side and low-side switches until the
voltage on the internal reference exceeds the
sensed output voltage at the internal FB node.
5V Linear Regulator
There is a built-in 100-mA standby linear
regulator which outputs 5V.The 5V LDO is
intended mainly for auxiliary 5V supply for the
notebook system during standby mode.
Add a ceramic capacitor with a value between
4.7μF and 22μF placed close to the LDO pins to
stabilize LDOs.
5V LDO Switch Over
When the output voltage becomes higher than
4.77V and the power good flag is generated,
internal 5V LDO regulator is shut off and the LDO
output is connected to Vout pin by the internal
switch over MOSFET. The 20-us power good
deglitch time helps a switch over without glitch.
CLK for Charge Pump
The 300kHz CLK signal can be used to drive an
external charge pump circuit to generate
approximately 12-15V DC voltage. The CLK
voltage becomes available once the VIN is higher
than UVLO threshold. Example of charge pump
control circuit is shown in Figure 7.
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NB669, 24V, HIGH CURRENT SYNCHRONOUS BUCK CONVERTER WITH LDO
END OF LIFE
CLK
100nF
100nF
5V
12V/100mA
100nF
PGND
100nF
PGND
100nF
PGND
Figure 7—Charge Pump Circuit
Power Good (PG)
The NB669 has power-good (PG) output used to
indicate whether the output voltage of the Buck
regulator is ready or not. The PG pin is the open
drain of a MOSFET. It should be connected to
VCC or other voltage source through a resistor
(e.g. 100k). After the input voltage is applied, the
MOSFET is turned on so that the PG pin is pulled
to GND before SS is ready. After FB voltage
reaches 95% of REF voltage, the PG pin is
pulled high after a delay. The PG delay time is
0.5ms.
When the FB voltage drops to 85% of REF
voltage, the PG pin will be pulled low.
Over Current Protection
NB669 has cycle-by-cycle over current limiting
control. The current-limit circuit employs a
"valley" current-sensing algorithm. The part uses
the Rds(on) of the low side MOSFET as a
current-sensing element. If the magnitude of the
current-sense signal is above the current-limit
threshold, the PWM is not allowed to initiate a
new cycle.
The trip level is fixed internally. The inductor
current is monitored by the voltage between GND
pin and SW pin. GND is used as the positive
current sensing node so that GND should be
connected to the source terminal of the bottom
MOSFET.
Since the comparison is done during the high
side MOSFET OFF and low side MOSFET ON
state, the OC trip level sets the valley level of the
inductor current. Thus, the load current at overcurrent threshold, IOC, can be calculated as
follows:
IOC I _ limit
NB669 Rev. 1.03
8/27/2014
Iinductor
2
(6)
In an over-current condition, the current to the
load exceeds the current to the output capacitor;
thus the output voltage tends to fall off.
Eventually, it will end up with crossing the under
voltage protection threshold and shutdown. And
fault latching can be reset by EN going low or
Power-cycling of VIN.
Over/Under-Voltage Protection (OVP/UVP)
NB669 monitors output voltage to detect over
and under voltage. When the feedback voltage
becomes higher than 115% of the target voltage,
the controller will enter Dynamic Regulation
Period. During this period, the LS will off when
the LS current goes to -1A, this will then
discharge the output and try to keep it within the
normal range. If the dynamic regulation can not
limit the increasing of the Vo, once the feedback
voltage becomes higher than 130% of the
feedback voltage, the OVP comparator output
goes high and the circuit latches as the high-side
MOSFET driver OFF and the low-side MOSFET
driver turn on acting as an -1A current source.
When the feedback voltage becomes lower than
60% of the target voltage, the UVP comparator
output goes high if the UV still occurs after 26us
delay; then the fault latch will be triggered--latches HS off and LS on; the LS FET keeps on
until the inductor current goes zero. Also fault
latching can be reset by EN going low or Powercycling of VIN.
UVLO Protection
The NB669 has under-voltage lock-out protection
(UVLO). When the VCC voltage is higher than
the UVLO rising threshold voltage, the part will
be powered up. It shuts off when the VIN voltage
is lower than the UVLO falling threshold voltage.
This is non-latch protection. The part is disabled
when the VCC voltage falls below 4.65V. If an
application requires a higher under-voltage
lockout (UVLO), use the EN pin as shown in
Figure 8 to adjust the input voltage UVLO by
using two external resistors. It is recommended
to use the enable resistors to set the UVLO
falling threshold (VSTOP) above 4.65V. The
rising threshold (VSTART) should be set to
provide enough hysteresis to allow for any input
supply variations. Besides fault latching can be
reset by EN going low or Power-cycling of VIN.
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NB669, 24V, HIGH CURRENT SYNCHRONOUS BUCK CONVERTER WITH LDO
END OF LIFE
VIN
RUP
NB669
EN Comparator
EN
RDOWN
Figure 8—Adjustable UVLO
Thermal Shutdown
Thermal shutdown is employed in the NB669.
The junction temperature of the IC is internally
monitored. If the junction temperature exceeds
the threshold value (typical 150ºC), the converter
shuts off. This is a non-latch protection. There is
about 25ºC hysteresis. Once the junction
temperature drops to about 125ºC, it initiates a
SS.
Output Discharge
NB669 discharges the output when EN is low, or
the controller is turned off by the protection
functions (UVP & OCP, OCP, OVP, UVLO, and
thermal shutdown). The part discharges outputs
using an internal 6Ω MOSFET.
NB669 Rev. 1.03
8/27/2014
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NB669, 24V, HIGH CURRENT SYNCHRONOUS BUCK CONVERTER WITH LDO
END OF LIFE
APPLICATION INFORMATION
VOUT
Input Capacitor
The input current to the step-down converter is
discontinuous and therefore requires a capacitor
to supply the AC current to the step-down
converter while maintaining the DC input voltage.
Ceramic capacitors are recommended for best
performance and should be placed as close to
the VIN pin as possible. Capacitors with X5R and
X7R ceramic dielectrics are recommended
because they are fairly stable with temperature
fluctuations.
The capacitors must also have a ripple current
rating greater than the maximum input ripple
current of the converter. The input ripple current
can be estimated as follows:
ICIN IOUT
VOUT
V
(1 OUT )
VIN
VIN
(7)
The worst-case condition occurs at VIN = 2VOUT,
where:
ICIN
IOUT
2
(8)
For simplification, choose the input capacitor with
an RMS current rating greater than half of the
maximum load current.
The input capacitance value determines the input
voltage ripple of the converter. If there is an input
voltage ripple requirement in the system, choose
the input capacitor that meets the specification.
The input voltage ripple can be estimated as
follows::
VIN
IOUT
V
V
OUT (1 OUT )
FSW CIN VIN
VIN
(9)
Under worst-case conditions where VIN = 2VOUT:
VIN
IOUT
1
4 FSW CIN
(10)
Output Capacitor
The output capacitor is required to maintain the
DC output voltage. Ceramic or POSCAP
capacitors are recommended. The output voltage
ripple can be estimated as:
NB669 Rev. 1.03
8/27/2014
VOUT
V
1
(1 OUT ) (RESR
) (11)
FSW L
VIN
8 FSW COUT
In the case of ceramic capacitors, the impedance
at the switching frequency is dominated by the
capacitance. The output voltage ripple is mainly
caused by the capacitance. For simplification, the
output voltage ripple can be estimated as:
VOUT
VOUT
V
(1 OUT )
2
8 FSW L COUT
VIN
(12)
In the case of POSCAP capacitors, the ESR
dominates the impedance at the switching
frequency. The ramp voltage generated from the
ESR is high enough to stabilize the system.
Therefore, an external ramp is not needed. A
minimum ESR value around 12mΩ is required to
ensure stable operation of the converter. For
simplification, the output ripple can be
approximated as:
VOUT
VOUT
V
(1 OUT ) RESR
FSW L
VIN
(13)
Maximum output capacitor limitation should be
also considered in design application. NB669 has
an around 1.8ms soft-start time period. If the
output capacitor value is too high, the output
voltage can’t reach the design value during the
soft-start time, and then it will fail to regulate. The
maximum output capacitor value CO_MAX can be
limited approximately by:
CO _ MAX (ILIM _ AVG IOUT ) Tss / VOUT
(14)
Where, ILIM_AVG is the average start-up current
during soft-start period. Tss is the soft-start time.
Inductor
The inductor is necessary to supply constant
current to the output load while being driven by
the switched input voltage. A larger-value
inductor will result in less ripple current that will
result in lower output ripple voltage. However, a
larger-value inductor will have a larger physical
footprint, higher series resistance, and/or lower
saturation current. A good rule for determining
the inductance value is to design the peak-topeak ripple current in the inductor to be in the
range of 30% to 40% of the maximum output
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15
NB669, 24V, HIGH CURRENT SYNCHRONOUS BUCK CONVERTER WITH LDO
current, and that the peak inductor current is
below the maximum switch current limit. The
inductance value can be calculated by:
VOUT
V
L
(1 OUT )
FSW IL
VIN
(15)
Where ΔIL is the peak-to-peak inductor ripple
current.
The inductor should not saturate under the
maximum inductor peak current, where the peak
inductor current can be calculated by:
VOUT
V
(16)
ILP IOUT
(1 OUT )
2FSW L
VIN
PCB Layout Guide
The following guidelines should be followed when
designing the PC board for the NB669:
1. The high current paths (GND, IN, and SW)
should be placed very close to the device
with short, direct and wide traces.
END OF LIFE
2. Put the input capacitors as close to the IN
and GND pins as possible.
3. Put the decoupling capacitor as close to the
VCC and AGND pins as possible. Place the
Cap close to AGND if the distance is long.
And place >3 Vias if via is required to reduce
the leakage inductance.
4. Keep the VOUT sensing trace far away from
the SW node.Vias should also be avoided on
the VOUT sensing trace.
5. Keep the BST voltage path (BST, C3, and
SW) as short as possible.
6. Keep the IN and GND pads connected with
large copper and use at least two layers for
IN and GND trace to achieve better thermal
performance. Also, add several Vias with
10mil_drill/18mil_copper_width close to the
IN and GND pads to help on thermal
dissipation.
7. AGND connects PGND with KELVIN
Connecting.
8. Four-layer layout is strongly recommended to
achieve better thermal performance.
Note:
Please refer to the PCB Layout Application Note
for more details.
NB669 Rev. 1.03
8/27/2014
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NB669, 24V, HIGH CURRENT SYNCHRONOUS BUCK CONVERTER WITH LDO
END OF LIFE
AGND KELVIN
CONNECT TO PGND
14
EN
ENLDO
AGND
13
12
11
10
SW
VIN
1
9
15
2
16
4
5
6
PG
CLK
LDO
7
VOUT
VOUT
3
8
VOUT
GND
DO NOT CONNECT
TO AGND HERE
Figure 9—Recommend Layout
Recommend Design Example
A typical application schematic is shown in
Figure 10 when large ESR caps are used, and
Figure 11 shows the schematic when low ESR
caps are applied. The typical performance and
NB669 Rev. 1.03
8/27/2014
circuit waveforms have been shown in the
Typical Performance Characteristics section. For
more possible applications of this device, please
refer to related Evaluation Board Datasheets.
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NB669, 24V, HIGH CURRENT SYNCHRONOUS BUCK CONVERTER WITH LDO
END OF LIFE
TYPICAL APPLICATION
Figure 10---Typical Application Circuit with Poscap
NB669 VIN=6.5-22V, VOUT=5V, IOUT=6A, FSW=500kHz
Figure 11---Typical Application Circuit with Low ESR Ceramic Capacitor
NB669 VIN=6.5-22V, VOUT=5V, IOUT=6A, FSW=500kHz
NB669 Rev. 1.03
8/27/2014
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NB669, 24V, HIGH CURRENT SYNCHRONOUS BUCK CONVERTER WITH LDO
END OF LIFE
PACKAGE INFORMATION
QFN16 (3X3mm)
PIN 1 ID
MARKING
PIN 1 ID
0.10x45 ? YP.
PIN 1 ID
INDEX AREA
TOP VIEW
BOTTOM VIEW
SIDE VIEW
NOTE:
0.10x45°
1) ALL DIMENSIONS ARE IN MILLIMETERS.
2) EXPOSED PADDLE SIZE DOES NOT INCLUDE
MOLD FLASH .
3) LEAD COPLANARITY SHALL BE 0.10
MILLIMETERS MAX.
4) JEDEC REFERENCE IS MO-220.
5) DRAWING IS NOT TO SCALE .
RECOMMENDED LAND PATTERN
NOTICE: The information in this document is subject to change without notice. Users should warrant and guarantee that third
party Intellectual Property rights are not infringed upon when integrating MPS products into any application. MPS will not
assume any legal responsibility for any said applications.
NB669 Rev. 1.03
8/27/2014
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