MPDTH03060YAS

MPDTH03060Y** Application 1 DC-DC Converter Application Manual MPDTH03060Y** 10-A, 3.3-V Input Non-Isolated DDR/QDR Memory Bus Termination Module Features ･ Output Over-Current Protection (Non-Latching, Auto-Reset) o ･ Operating Temp: -40 to +85 C ･ Point-of-Load Alliance Compatible • VTT Bus Termination Output (Output Track the System Vref) • 10-A Output Current • 3.3-V Input Voltage • DDR and QDR Compatible • Efficiencies up to 91 % 3 • 57 W/in Power Density • On/Off Inhibit(for Vtt Standby) • Under-Voltage Lockout NOMINAL SIZE = 25.27 mm x 15.75 mm Description Pin Configuration The MPDTH03060Y are a series of ready-to-use switching regulator modules from Murata designed specifically for bus termination in DDR and QDR memory applications. Operating 3.3-V input, the module generates a VTT output that will source or sink up to 10 A of current to accurately track their Vref input. VTT is the required bus termination supply voltage, and Vref is the reference voltage for the memory and chipset bus receiver comparators. Vref is usually set to half the VDDQ power supply voltage. The MPDTH03060Y employs an actively switched synchronous rectifier output to provide state-of-the-art stepdown switching conversion. The products are small in size (25.4mm × 15.75mm), and are an ideal choice where space, performance, and high efficiency are desired, along with the convenience of a ready-to-use module. Operating features include an on/off inhibit and output over-current protection (source mode only). The on/off inhibit feature allows the VTT bus to be turned off to save power in a standby mode of operation. To ensure tight load regulation, an output remote sense is also provided. Package options include both throughhole and surface mount configurations. Pin 1 2 3 4 5 6 7 8 9 10 Function GND Vin Inhibit No Connect Vo Sense VTT GND Vref No Connect No Connect Standard Application R1: 1kΩ Vref Vin VDDQ VTT 8 2 6 Vo Sense Vin 5 MPDTH03060Y + Cin: 330µF R2: 1kΩ Inhibit 4 3 9 10 1 RL + Co1: 470µF Co2: 200µF 7 GND Open=ON Short=OFF Cin : Required 330µF, Capacitor Co1 : Required 470µF, Low-ESR Electrolytic Capacitor Co2 : Ceramic Capacitor for Optimum response, 200µF Note: 1. This datasheet is downloaded from the website of Murata Manufacturing co., ltd. Therefore, it’ s specifications are subject to change or our products in it may be discontinued without advance notice. Please check with our sales representatives or product engineers before ordering. 2. This datasheet has only typical specifications because there is no space for detailed specifications. Therefore, please approve our product specifications or transact the approval sheet for product specifications before ordering. 2006.10.2 1 MPDTH03060Y** Application 2 10-A, 3.3-V Input Non-Isolated DDR/QDR Memory Bus Termination Module Ordering Information Output Voltage (MPDTH03060□xx) Code Y Notes Package Options (MPDTH03060x□□) Voltage Code 0.55V-1.8V(Adjustable) AH AS Description Horiz. T/H SMD(*1) (1) Pb free (Sn-Ag-Cu) pin solder material. Pin Description Vin: The positive input voltage power node to the module, which is referenced to common GND. VTT: This is the regulated power output from the module with respect to the GND node, and the tracking termination supply for the application data and address buses. It is precisely regulated to the voltage applied to the module's Vref input, and is active about 20 ms after a valid input source is applied to the module. Once active it will track the voltage applied at Vref. GND: This is the common ground connection for the VIN and VTT power connections. It is also the 0 VDC reference for the control inputs. Inhibit: The Inhibit pin is an open-collector/drain negative logic input that is referenced to GND. Applying a low-level ground signal to this input turns off the output voltage, VTT. Although the module is inhibited, a voltage, VDDQ will be present at the output terminals, fed through the DDR memory. When the Inhibit is active, the input current drawn by the regulator is significantly reduced. If the Inhibit pin is left open circuit, the module will produce an output whenever a valid input source is applied. See the Typical DDR Application Diagram in the Application Information section for reference. Vref: The module senses the voltage at this input to regulate the output voltage, VTT. The voltage at Vref is also the reference voltage for the system bus receiver comparators. It is normally set to precisely half the bus Vref 8 driver supply voltage (VDDQ÷ 2), using a resistor divider. The Thevenin impedance of the network driving the Vref pin should not exceed 500 Ω. See the Typical DDR Application Diagram in the Application Information section for reference. Vo Sense: The sense input allows the regulation circuit to compensate for voltage drop between the module and the load. For optimal voltage accuracy Vo Sense should be connected to VTT. No Connect: No connection. Note: 1. This datasheet is downloaded from the website of Murata Manufacturing co., ltd. Therefore, it’ s specifications are subject to change or our products in it may be discontinued without advance notice. Please check with our sales representatives or product engineers before ordering. 2. This datasheet has only typical specifications because there is no space for detailed specifications. Therefore, please approve our product specifications or transact the approval sheet for product specifications before ordering. 2006.10.2 MPDTH03060Y** Application 3 10-A, 3.3-V Input Non-Isolated DDR/QDR Memory Bus Termination Module Environmental & Absolute Maximum Ratings (Voltages are with respect to GND) Characteristics Control Input Voltage Operating Temperature Range Strage Temperature Solder Reflow Temperature Symbols Vref Ta Ts Treflow Conditions Over Vin Range Surface temperature of module body or pins Min -0.3 -40(i) -40 Typ - Max Vin+0.3 85 125 245(ii) Units V o C o C o C Notes: (i) For operation below 0 oC the external capacitors must have stable characteristics. Use either a low ESR tantalum, Os-Con, or ceramic capacitor. (ii) During reflow of SMD package version do not elevate peak temperature of the module, pins or internal components above the stated maximum Electrical Specifications o (Unless otherwise stated, Ta =25 C, Vin =3.3 V, Vref =1.25 V, Cin =330µF, Co1 =470µF, Co2 =200µF, and Io =Iomax) Characteristics Output Current Input Voltage Range Tracking range for Vref Tracking tolerance to Vref Efficiency Vo Ripple (pk-pk) Short Circuit Protection Load transient response Rising UVLO Threshold Falling UVLO Threshold Inhibit Control (pin4) Input High Voltage Input Low Voltage Input Low Current Input Standby Current Switching Frequency External Input Capacitance External Output Capacitance MTBF Symbols Io Vin ∆Vref |VTT-Vref| η Vr Io trip ttr ∆Vtr UVLOr UVLOf VIH VIL IILinhibit Iin inh Frq Cin Cout MTBF Conditions Over ∆Vref Range Over Io Range Over line, load and temperature Io=0A Io=8A 20 MHz bandwidth Reset, Followed by Auto-Recovery 15 A/µs load step, from –1. 5A to 1.5A Recovery Time Vo Deviation Vin Increasing Vin Decreasing Referenced to GND Pin to GND Inhibit (pin 3) to GND, Over Vin and Io Ranges Capacitance Non-Ceramic(ESR≧4mΩ) Per Bellcore TR-332 o 50 % stress, Ta =40 C, Ground Benign Min Typ Max Units 0 2.95(2) 0.55 -10 - 86 20 20 ±10(1) 3.65 1.8 10 - A V V mV % mVpp A 1.9 30 25 2.45 2.1 40 2.8 - µsec mV V V Vin-0.5 -0.2 330(3) 470(4) - 130 10 300 200(4) Open(2) 0.6 5500(5) 300 6 - - V µA mA kHz µF µF 6 10 Hrs Notes: (1) Rating is conditional on the module being directly soldered to a 4-layer PCB with 1 oz. copper. See the SOA curves or contact the factory for appropriate derating. (2) This control pin has an internal pull-up to the input voltage VIN. If it is left open-circuit the module will operate when input power isapplied. A small low-leakage (