NCP4306DADZZDASNT1G

DATA SHEET www.onsemi.com Secondary Side Synchronous Rectification Driver for High Efficiency SMPS Topologies 8 1 SOIC−8 NB CASE 751−07 1 TSOP−6 CASE 318G−02 8 NCP4306 The NCP4306 is high performance driver tailored to control a synchronous rectification MOSFET in switch mode power supplies. Thanks to its high performance drivers and versatility, it can be used in various topologies such as DCM or CCM flyback, quasi resonant flyback, forward and half bridge resonant LLC. The combination of externally or fixed adjustable minimum off-time and on-time blanking periods helps to fight the ringing induced by the PCB layout and other parasitic elements. A reliable and noise less operation of the SR system is insured due to the Self Synchronization feature. The NCP4306 also utilizes Kelvin connection of the driver to the MOSFET to achieve high efficiency operation at full load and utilizes a light load detection architecture to achieve high efficiency at light load. The precise turn−off threshold, extremely low turn−off delay time and high sink current capability of the driver allow the maximum synchronous rectification MOSFET conduction time and enables maximum SMPS efficiency. The high accuracy driver and 5 V gate clamp enables the use of GaN MOSFETs. Features • Self−Contained Control of Synchronous Rectifier in CCM, DCM and • • • • • • • • • • • • • • • QR for Flyback or LLC Applications Precise True Secondary Zero Current Detection Typically 15 ns Turn off Delay from Current Sense Input to Driver Rugged Current Sense Pin (up to 200 V) Ultrafast Turn−off Trigger Interface / Disable Input (10.5 ns) Adjustable or Fixed Minimum ON−Time Adjustable or Fixed Minimum OFF-Time with Ringing Detection Improved Robust Self Synchronization Capability 7 A / 2 A Peak Current Sink / Source Drive Capability Operating Voltage Range up to VCC = 35 V Automatic Light−load Disable Mode GaN Transistor Driving Capability Low Startup and Disable Current Consumption Maximum Operation Frequency up to 1 MHz TSOP6, SOIC8, DFN8 4x4 and DFN8 2x2.2 Packages This is a Pb−Free Device 1 1 DFN8, 4x4 CASE 488AF DFN8, 2.0x2.2, 0.5P CASE 506BP MARKING DIAGRAMS 8 XXXXXXXX ALYWX XXXAYWG G 1 G 1 SOIC−8 NB XXXXXX XXXXXX ALYWG G DFN8, 4x4 TSOP−6 1 XXMG G DFN8, 2.0x2.2, 0.5P See detailed marking information on page 2 of this data sheet. XXXXX A L Y W M G = Specific Device Code = Assembly Location = Wafer Lot = Year = Work Week = Date Code = Pb−Free Package (Note: Microdot may be in either location) ORDERING INFORMATION See detailed ordering and shipping information on page 2 of this data sheet. Typical Applications • • • • Notebook Adapters High Power Density AC / DC Power Supplies (Cell Phone Chargers) LCD TVs All SMPS with High Efficiency Requirements © Semiconductor Components Industries, LLC, 2017 January, 2022 − Rev. 8 1 Publication Order Number: NCP4306/D NCP4306 ORDERING INFORMATION TABLE Table 1. AVAILABLE DEVICES Device Package Shipping † SOIC−8 (Pb−Free) 2500 / Tape and Reel TSOP−6 (Pb−Free) 3000 / Tape and Reel DFN−8 4x4 (Pb−Free) 4000 / Tape and Reel DFN−8 2x2.2 (Pb−Free) 3000 / Tape and Reel Package Marking NCP4306AAAZZZADR2G 6AAAZZZA NCP4306AADZZZADR2G 6AADZZZA NCP4306AAHZZZADR2G 6AAHZZZA NCP4306DADZZDASNT1G 6AC NCP4306DAHZZAASNT1G 6AD NCP4306DADZZBASNT1G 6AK NCP4306AAAZZZAMNTWG 4306AAAZZZA NCP4306AADZZZAMNTWG 4306AADZZZA NCP4306AAAZZZAMN1TBG 6A NCP4306AADZZZAMN1TBG 6D †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. See the onsemi Device Nomenclature document (TND310/D) for a full description of the naming convention used for image sensors. For reference documentation, including information on evaluation kits, please visit our web site at www.onsemi.com. C3 R1 Tr1 M1 RLLD +VBULK MIN_TON LLD RMIN_TON RMIN_TOFF VCC MIN_TOFF NCP4306 +VOUT M3 N2 LLC STAGE CONTROL DRV GND CS TRIG C2 RTN M2 N1 D1 N3 M4 C1 OK1 DRV VCC MIN_TOFF GND CS MIN_TON LLD RLLD RMIN_TON RMIN_TOFF R2 C4 TRIG NCP4306 Figure 1. Typical Application Example – LLC Converter with optional LLD and Trigger Utilization www.onsemi.com 2 NCP4306 +VOUT VBULK TR1 R1 C1 C2 C5 R3 D3 VCC FLYBACK CONTROL CIRCUITRY M2 D4 C3 DRV M1 VCC FB GND C4 CS DRV MIN_TOFF GND OK1 CS TRIG LLD D5 NCP4306 RLLD R2 RMIN_TON RMIN_TOFF MIN_TON Figure 2. Typical Application Example – DCM, CCM or QR Flyback Converter with optional LLD and disabled TRIG +VOUT VBULK C1 TR1 R1 C2 C5 D3 R3 VCC M2 D4 FLYBACK CONTROL CIRCUITRY C3 M1 DRV CS VCC CS LLD NCP4306 RMIN_TOFF GND MIN_TOFF RLLD DRV FB GND C4 D5 OK1 Figure 3. Typical Application Example – DCM, CCM or QR Flyback Converter with NCP4306 in TSOP6 (v Cxxxxxx) www.onsemi.com 3 NCP4306 +VOUT VBULK TR1 R1 C1 C2 R3 C8 R5 D3 VCC C4 C3 DRV C7 M1 GND DRV VCC GND MIN_TOFF COMP CS CS R2 R4 MIN_TON NCP4306 RMIN_TOFF R3 M2 D4 PRIMARY SIDE FLYBACK CONTROLLER RMIN_TON ZCD C5 C6 Figure 4. Typical Application Example – Primary Side Flyback Converter and NCP4306 in TSOP6 PIN FUNCTION DESCRIPTION Table 2. PIN FUNCTION DESCRIPTION TSOP6 Bxxxxxx TSOP6 Cxxxxxx TSOP6 Dxxxxxx TSOP6 Exxxxxx TSOP6 Fxxxxxx TSOP6 Gxxxxxx SOIC8, DFN8 Axxxxxx Pin Name 6 6 6 6 6 6 1 VCC − 5 5 5 − 2 MIN_TOFF Adjust the minimum off time period by connecting resistor to ground 5 − 4 − 5 − 3 MIN_TON Adjust the minimum on time period by connecting resistor to ground 4 4 − − − 4 4 LLD This input modulates the driver clamp level and / or turns the driver off during light load conditions − − − 4 4 5 5 TRIG / DIS Ultrafast turn−off input that can be used to turn off the SR MOSFET in CCM applications in order to improve efficiency. Activates disable mode if pulled−up for more than 100 μs 3 3 3 3 3 3 6 CS 2 2 2 2 2 2 7 GND Ground connection for the SR MOSFET driver and VCC decoupling capacitor. Ground connection for minimum tON and tOFF adjust resistors, LLD and trigger inputs. GND pin should be wired directly to the SR MOSFET source terminal / soldering point using Kelvin connection. DFN8 exposed flag should be connected to GND. 1 1 1 1 1 1 8 DRV Driver output for the SR MOSFET www.onsemi.com 4 Description Supply voltage pin Current sense pin detects if the current flows through the SR MOSFET and / or its body diode NCP4306 Exception time generator MIN_TON EN ELAPSED DISABLE Disable detection LLD EXT_ADJ INT_ADJ CS Minimum ON time generator CS detection ELAPSED INT_ADJ EN DRIVER dV/dt CS_ON CS_OFF CS_RESET DRVOUT DRV Control logic VDD RESET MIN_TOFF EXT_ADJ INT_ADJ Minimum OFF time generator ELAPSED EN TRIG DISABLE VCC managment UVLO VCC DISABLE TRIG/DIS Disable detection 10 μA VTRIG Figure 5. Internal Circuit Architecture – NCP4306 www.onsemi.com 5 GND NCP4306 ABSOLUTE MAXIMUM RATINGS Table 3. ABSOLUTE MAXIMUM RATINGS Rating Symbol Value Unit VCC −0.3 to 37.0 V VTRIG / DIS, VMIN_TON, VMIN_TOFF, VLLD −0.3 to VCC V Driver Output Voltage VDRV −0.3 to 17.0 V Current Sense Input Voltage VCS −4 to 200 V VCS_DYN −10 to 200 V IMIN_TON, IMIN_TOFF, ILLD, ITRIG −10 to 10 mA DRV Pin Current (tPW = 10 μs) IDRV_DYN −3 to 12 A VCC Pin Current (tPW = 10 μs) IVCC_DYN 3 A Junction to Air Thermal Resistance, 1 oz 1 in2 Copper Area, SOIC8 RθJ−A_SOIC8 200 °C / W Junction to Air Thermal Resistance, 1 oz 1 in2 Copper Area TSOP6 RθJ−A_TSOP6 250 °C / W Junction to Air Thermal Resistance, 1 oz 1 in2 Copper Area DFN8 4x4 RθJ−A_DFN8_4x4 80 °C / W Junction to Air Thermal Resistance, 1 oz 1 in2 Copper Area DFN8 2x2.2 RθJ−A_DFN8_2x2.2 85 °C / W Maximum Junction Temperature TJMAX 150 °C Storage Temperature TSTG −60 to 150 °C ESD Capability, Human Body Model (except pin CS) (Note 1) ESDHBM 2000 V ESD Capability, Human Body Model Pin CS ESDHBM 600 V ESD Capability, Machine Model (Note 1) ESDMM 200 V ESD Capability, Charged Device Model (Note 1) ESDCDM Class C3 - Supply Voltage TRIG / DIS, MIN_TON, MIN_TOFF, LLD Input Voltage (Note 3) Current Sense Dynamic Input Voltage (tPW = 200 ns) MIN_TON, MIN_TOFF, LLD, TRIG Input Current Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. This device series contains ESD protection and exceeds the following tests: Except pin CS: Human Body Model 2000 V per JEDEC Standard JESD22−A114E. All pins: Machine Model Method 200 V per JEDEC Standard JESD22−A115−A Charged Machine Model per JEDEC Standard JESD22−C101F 2. This device meets latchup tests defined by JEDEC Standard JESD78D. 3. If voltage higher than 22 V is connected to pin, pin input current increases. Internal ESD clamp contains 24 V Zener diode with 3 kΩ in series. It is recommended to add serial resistance in case of higher input voltage to limit input pin current. Table 4. RECOMMENDED OPERATING CONDITION Parameter Maximum Operating Voltage Operating Junction Temperature Symbol Min VCC TJ −40 www.onsemi.com 6 Max Unit 35 V 125 °C NCP4306 ELECTRICAL CHARACTERISTICS Table 5. ELECTRICAL CHARACTERISTICS −40 ºC ≤ TJ ≤ 125 ºC; VCC = 12 V; CDRV = 0 nF; RMIN_TON = RMIN_TOFF = 10 kΩ or internally set values; VLLD = 3.0 V or LLD internally disabled; VTRIG / DIS = 0 V; VCS = 4 V, unless otherwise noted. Typical values are at TJ = +25 ºC Test Conditions Parameter Symbol Min Typ Max Unit VCCON 3.7 4.0 4.2 V VCCOFF 3.2 3.5 3.7 SUPPLY SECTION VCC UVLO VCC rising VCC falling VCC UVLO Hysteresis Start−up Delay Current Consumption, tMIN_TON = tMIN_TOFF = 1 μs, tLLD = 130 μs VCC rising from 0 to VCCON + 1 V @ tr = 10 μs VCCHYS 0.5 V tSTART_DEL 50 80 μs ICC 1.8 2.5 mA CDRV = 0 nF, fCS = 100 kHz xAxxxxx xBxxxxx 1.7 2.4 CDRV = 1 nF, fCS = 100 kHz xAxxxxx 2.8 4.0 xBxxxxx 2.1 3.4 CDRV = 10 nF, fCS = 100 kHz xAxxxxx 12 15 xBxxxxx 6.7 9.0 Current Consumption ICC 1.4 2.2 mA Current Consumption below UVLO VCC = VCCOFF – 0.1 V ICC_UVLO 35 60 μA Current Consumption in Disable Mode t > tLLD , VLLD = 0.55 V ICC_DIS 60 100 μA VTRIG / DIS = 5 V; VLLD = 0.55 V 60 100 t > tLLD, LLD set internally 37 80 VTRIG / DIS = 5 V, LLD set internally 37 80 DRIVER OUTPUT Output Voltage Rise−Time CDRV = 10 nF, 10 % to 90 % VDRVMAX, VCS = 4 to −1 V tr 60 100 ns Output Voltage Fall−Time CDRV = 10 nF, 90 % to 10 % VDRVMAX, VCS = −1 to 4 V tf 25 45 ns Driver Source Resistance Driver Sink Resistance Output Peak Source Current Output Peak Sink Current Maximum Driver Pulse Length Maximum Driver Output Voltage RDRV_SOURCE 2 Ω RDRV_SINK 0.5 Ω IDRV_SOURCE 2 A IDRV_SINK 7 A tDRV_ON_MAX 4 ms VDRVMAX VCC = 35 V, CDRV > 1 nF, (ver. xAxxxxx) VCC = 35 V, CDRV > 1 nF, (ver. xBxxxxx) Minimum Driver Output Voltage VDRVMIN VCC = VCCOFF + 200 mV, (ver. xAxxxxxx) VCC = VCCOFF + 200 mV, (ver. xBxxxxxx) 9 10 11 4.5 5.0 5.5 3.4 3.7 3.9 3.4 3.7 3.9 V V CS INPUT Total Propagation Delay From CS to DRV Output On VCS goes down from 4 to −1 V, tf_CS 1/4 tLLD Figure 80. LLD Internal Block Diagram www.onsemi.com 39 S R Q Disable NCP4306 Table 6. PIN FUNCTION DESCRIPTION LLD setting tLLD [ms] IC disabled 70 130 280 540 1075 LLD disabled RLLD [kW] 470* *floating pin allowed, small cap for noise robustness improvement recommended and IC starts to wake up (takes tLLD_DIS_REC, system wake up is controlled same as exit from disable mode by TRIG / DIS pin). End of conduction phase (CS voltage goes positive) starts LLD timer. If next conduction phase comes shortly after first (pulses in skip burst) so shortly than tLLD / 4 just LLD timer is reset. LLD timer length is set back to tLLD only when new conduction phase comes after previous in time between tLLD / 4 to tLLD / 2. This situation happens when load is slowly increased and skip bursts come more often. Logic function is also described by bubble diagram in Figure 81. LLD timer is running every time when CS pin voltage is positive (body diode and or transistor not conducting). If conduction doesn’t come sooner than LLD timer elapses, DISABLE flag is set (IC is sent into low consumption mode), LLD timer length is changed to tLLD / 2 (this adds some hysteresis in system and helps keeping overall system stable) and timer is also reset. SR controller waits for falling edge at CS pin (begin of new conduction cycle). When CS goes negative, disable mode is deactivated Start LLD TIM is RUNNING LLD_CMP & TIM CNT < 1/4 tLLD Reset TIM DISABLE = 0 LLD_CMP DISABLE = 1 tTIM = 1/2 tLLD Reset TIM Reset TIM DISABLE = 0 tTIM = tLLD Figure 81. LLD Operation Bubble Diagram Example of LLD operation with flyback convertor can be seen in Figure 82. SMPS works under heavy load from point 0 to 1 where switching pulses comes regularly at high frequency that resets LLD timer soon after begin of counting. Load is significantly decreased to light load at point 1 so primary controller turns to skip mode. LLD timer elapses during skip so controller enters disable mode with very low consumption and change LLD timer maximum to tLLD / 2. Switching pulse in skip comes at time 3, this resets LLD timer and starts IC wake−up. Controller is waked up fully before point 4 and turns−on SR transistor. There is again no switching from 4 to 6 and thanks to it, LLD timer elapses at point 5 and controller enters disable mode again. Disable mode is ended at time 6, because new cycle comes. SR controller wakes−up and next pulse in skip burst is conducted via SR transistor. Time between 7 and 8 is delay between skip burst. Time is still less than tLLD / 4, LLD timer interval is not changed. Pulse at time 8 is fully conducted via SR transistor, because controller was not in disable mode before pulse came. No switching period between 9 and 11 is longer than tLLD / 2 that changes LLD timer setting to tLLD. This is because shorter delay between skip burst means higher load. Pulses are transferred via SR transistor at time 11 and 12, because disable mode was not activated. Load is being decreased again between time 12 to 15 so at time 15 SR controller enters disable mode and LLD timer time is reduced again to tLLD / 2. Second pulse in skip burst is again transferred via turned on SR transistor. Disable mode is activated after tLLD / 2 at time 18. Load is sharply changed at time 19 that means LLD timer is reset each pulse and timers time is kept at tLLD / 2. Load is removed at time 20 and disable is activated at time 21. Suitable LLD timer setting for flyback type of SMPS is 540 or 1075 μs (for special type 280 μs). www.onsemi.com 40 NCP4306 VDS = VCS t1 t2 t4 t2 t1 t2 DRV DIS ICC 0 t4 t1 t2 LLD tim tLLD 1 2 3 4 5 6 7 8 9 101112 13 14 15 16 17 18 19 20 21 22 Figure 82. LLD Operation with Flyback SMPS at time 8 respectively 9. Skip burst ends at time 12, LLD timers elapse at time 13 and 14 (reached tLLD / 2) and SR controllers enter disable mode. Controllers wake up at time 15 and 16 same as was in time 6 and 7. SMPS goes into skip in time 21, but load is connected soon and SMPS starts to operate under higher load from time 22. LLD timers reach time higher than tLLD / 4 but lower than tLLD / 2 so LLD timers maximum is set to tLLD. LLD timer setting for LLC may be set to lower times. Example of LLD operation with LLC convertor can be seen in Figure 83. SMPS works under heavy load from point 0 to 3. Both LLD timers are reset each cycle before LLD timer reaches tLLD / 4 and disable mode is not activated. SMPS load decreases at point 3 and goes into skip. LLD timers elapse during no switching time and change LLD timer time to tLLD / 2. When skip burst comes at time 6 channel 2 starts to wake up, channel 1 starts to wake up at time 7. Both channels are ready to conduct via SR transistor VDS1 = VCS1 VDS2 = VCS2 DRV1 DRV2 DIS1 DIS2 t2 0 1 2 3 t4 t1 LLD tim1 tLLD1 LLD tim2 tLLD1 4 5 6 7 8 9 10 11 12 13 14 15 16 17 Figure 83. LLD Operation with LLC SMPS www.onsemi.com 41 19 20 21 22 23 24 25 26 27 28 NCP4306 Operation flow and dV / dt features are never activated both at same time. Operation starts in bubble start where system comes when VCC is higher than UVLO level and / or disable mode is activated (by LLD or TRIG / DIS pin). Followed bubble diagram at Figure 84 shows overall operation flow. Black bubbles are fundamental parts of system. States for dV / dt feature are colored by blue color and states for LLC feature (exception timer) are in red. LLC Figure 84. Overall Operation Bubble Diagram Power dissipation calculation significantly. Therefore, the MOSFET switch always operates under Zero Voltage Switching (ZVS) conditions when in a synchronous rectification system. The following steps show how to approximately calculate the power dissipation and DIE temperature of the NCP4306 controller. Note that real results can vary due to the effects of the PCB layout on the thermal resistance. It is important to consider the power dissipation in the MOSFET driver of a SR system. If no external gate resistor is used and the internal gate resistance of the MOSFET is very low, nearly all energy losses related to gate charge are dissipated in the driver. Thus it is necessary to check the SR driver power losses in the target application to avoid over temperature and to optimize efficiency. In SR systems the body diode of the SR MOSFET starts conducting before SR MOSFET is turned−on, because there is some delay from VTH_CS_ON detect to turn−on the driver. On the other hand, the SR MOSFET turn off process always starts before the drain to source voltage rises up Step 1 – MOSFET gate to source capacitance: During ZVS operation the gate to drain capacitance does not have a Miller effect like in hard switching systems because the drain to source voltage does not change (or its change is negligible). Figure 85. Typical MOSFET Capacitances Dependency on VDS and VGS Voltages www.onsemi.com 42 NCP4306 C iss + C gs ) C gd (eq. 4) C rss + C gd (eq. 5) C oss + C ds ) C gd (eq. 6) NCP4306 offers both a 5 V gate clamp and a 10 V gate clamp for those MOSFET that require higher gate to source voltage. The total driving loss can be calculated using the selected gate driver clamp voltage and the input capacitance of the MOSFET: Therefore, the input capacitance of a MOSFET operating in ZVS mode is given by the parallel combination of the gate to source and gate to drain capacitances (i.e. Ciss capacitance for given gate to source voltage). The total gate charge, Qg_total, of most MOSFETs on the market is defined for hard switching conditions. In order to accurately calculate the driving losses in a SR system, it is necessary to determine the gate charge of the MOSFET for operation specifically in a ZVS system. Some manufacturers define this parameter as Qg_ZVS. Unfortunately, most datasheets do not provide this data. If the Ciss (or Qg_ZVS) parameter is not available then it will need to be measured. Please note that the input capacitance is not linear (as shown Figure 85) and it needs to be characterized for a given gate voltage clamp level. P DRV_total + V CC − + RDRV_SINK_EQ f SW (eq. 7) The total driving power loss won’t only be dissipated in the IC, but also in external resistances like the external gate resistor (if used) and the MOSFET internal gate resistance (Figure 86). Because NCP4306 features a clamped driver, it’s high side portion can be modeled as a regular driver switch with equivalent resistance and a series voltage source. The low side driver switch resistance does not drop immediately at turn−off, thus it is necessary to use an equivalent value (RDRV_SIN_EQK) for calculations. This method simplifies power losses calculations and still provides acceptable accuracy. Internal driver power dissipation can then be calculated using equation 8: VCC RDRV_SOURCE_EQ C g_ZVS Where: VCC is the NCP4306 supply voltage VCLAMP is the driver clamp voltage Cg_ZVS is the gate to source capacitance of the MOSFET in ZVS mode fsw is the switching frequency of the target application Step 2 – Gate drive losses calculation: Gate drive losses are affected by the gate driver clamp voltage. Gate driver clamp voltage selection depends on the type of MOSFET used (threshold voltage versus channel resistance). The total power losses (driving loses and conduction losses) should be considered when selecting the gate driver clamp voltage. Most of today’s MOSFETs for SR systems feature low RDS_ON for 5 V VGS voltage. The VCC − VCLAMP V CLAMP DRV RG_EXT SR MOSFET RG_INT GND CG_ZVS Figure 86. Equivalent Schematic of Gate Drive Circuitry www.onsemi.com 43 NCP4306 P DRV_IC + 1 2 C g_ZVS V CLAMP ) 1 2 C g_ZVS V CLAMP 2 2 f SW f SW ǒ ǒ R DRV_SOURCE_EQ V CLAMP f SW (V CC ) V CLAMP) Ǔ (eq. 8) Step 4 – IC die temperature arise calculation: The die temperature can be calculated now that the total internal power losses have been determined (driver losses plus internal IC consumption losses). The package thermal resistance is specified in the maximum ratings table for a 35 mm thin copper layer with 1 in2 copper area. The die temperature is calculated as: T DIE + (P DRV_IC ) P CC) Step 3 – IC consumption calculation: In this step, power dissipation related to the internal IC consumption is calculated. This power loss is given by the ICC current and the IC supply voltage. The ICC current depends on switching frequency and also on the selected min tON and tOFF periods because there is current flowing out from the MIN_TON and MIN_TOFF pins. The most accurate method for calculating these losses is to measure the ICC current when CLOAD = 0 nF and the IC is switching at the target frequency with given min_tON and min_tOFF adjust resistors. IC consumption losses can be calculated as: I CC ) C g_ZVS R DRV_SOURCE_EQ ) R G_EXT ) R g_int Where: RDRV_SINK_EQ is the NCP4306 driver low side switch equivalent resistance (1.6 Ω) RDRV_SOURCE_EQ is the NCP4306 driver high side switch equivalent resistance (7 Ω) RG_EXT is the external gate resistor (if used) Rg_int is the internal gate resistance of the MOSFET P CC + V CC Ǔ R DRV_SINK_EQ R DRV_SINK_EQ ) R G_EXT ) R g_int R qJ*A ) T A (eq. 10) Where: PDRV_IC is the IC driver internal power dissipation PCC is the IC control internal power dissipation R J−A is the thermal resistance from junction to ambient TA is the ambient temperature (eq. 9) www.onsemi.com 44 NCP4306 OPN coding table NCP4306 OPN is built from prefix of NCP4306 and postfix that consist of seven letters. Meaning of these letters are shown in table 7. Table 7. OPN CODING TABLE NCP4306xxxxxxx Postfix Index Parameter Postfix 1 Pinout A MIN_TON, MIN_TOFF, LLD, TRIG / DIS − 8 pins 2 3 4 5 DRV dV / dt + exception MIN_TON MIN_TOFF Parameter B MIN_TON, LLD C MIN_TOFF, LLD D MIN_TON, MIN_TOFF E MIN_TOFF, TRIG / DIS F MIN_TON, TRIG / DIS G TRIG / DIS, LLD H None A DRV CLMP = 10 V B DRV CLMP = 5 V A None D Flyback (dV / dt) − 100 V / μs H LLC exception − multiplier 4 A 130 ns B 220 ns C 310 ns D 400 ns E 500 ns F 600 ns G 700 ns H 800 ns I 1000 ns J 1200 ns K 1400 ns L 1700 ns M 2000 ns Z External A 0.9 μs B 1.0 μs C 1.1 μs D 1.2 μs E 1.4 μs F 1.6 μs G 1.8 μs H 2.0 μs I 2.2 μs J 2.4 μs K 2.6 μs L 2.9 μs M 3.2 μs N 3.5 μs O 3.9 μs Z External www.onsemi.com 45 NCP4306 Table 7. OPN CODING TABLE (continued) NCP4306xxxxxxx Postfix Index Parameter Postfix 6 LLD A 68 μs B 130 μs C 280 μs D 540 μs E 1075 μs F Disabled Z External A − 7 Reserved www.onsemi.com 46 Parameter MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS TSOP−6 CASE 318G−02 ISSUE V 1 SCALE 2:1 D H ÉÉ ÉÉ 6 E1 1 NOTE 5 5 2 L2 4 GAUGE PLANE E 3 L b SEATING PLANE C DETAIL Z e DIM A A1 b c D E E1 e L L2 M c A 0.05 M DATE 12 JUN 2012 NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH. MINIMUM LEAD THICKNESS IS THE MINIMUM THICKNESS OF BASE MATERIAL. 4. DIMENSIONS D AND E1 DO NOT INCLUDE MOLD FLASH, PROTRUSIONS, OR GATE BURRS. MOLD FLASH, PROTRUSIONS, OR GATE BURRS SHALL NOT EXCEED 0.15 PER SIDE. DIMENSIONS D AND E1 ARE DETERMINED AT DATUM H. 5. PIN ONE INDICATOR MUST BE LOCATED IN THE INDICATED ZONE. A1 DETAIL Z MIN 0.90 0.01 0.25 0.10 2.90 2.50 1.30 0.85 0.20 0° MILLIMETERS NOM MAX 1.00 1.10 0.06 0.10 0.38 0.50 0.18 0.26 3.00 3.10 2.75 3.00 1.50 1.70 0.95 1.05 0.40 0.60 0.25 BSC 10° − STYLE 1: PIN 1. DRAIN 2. DRAIN 3. GATE 4. SOURCE 5. DRAIN 6. DRAIN STYLE 2: PIN 1. EMITTER 2 2. BASE 1 3. COLLECTOR 1 4. EMITTER 1 5. BASE 2 6. COLLECTOR 2 STYLE 3: PIN 1. ENABLE 2. N/C 3. R BOOST 4. Vz 5. V in 6. V out STYLE 4: PIN 1. N/C 2. V in 3. NOT USED 4. GROUND 5. ENABLE 6. LOAD STYLE 5: PIN 1. EMITTER 2 2. BASE 2 3. COLLECTOR 1 4. EMITTER 1 5. BASE 1 6. COLLECTOR 2 STYLE 6: PIN 1. COLLECTOR 2. COLLECTOR 3. BASE 4. EMITTER 5. COLLECTOR 6. COLLECTOR STYLE 7: PIN 1. COLLECTOR 2. COLLECTOR 3. BASE 4. N/C 5. COLLECTOR 6. EMITTER STYLE 8: PIN 1. Vbus 2. D(in) 3. D(in)+ 4. D(out)+ 5. D(out) 6. GND STYLE 9: PIN 1. LOW VOLTAGE GATE 2. DRAIN 3. SOURCE 4. DRAIN 5. DRAIN 6. HIGH VOLTAGE GATE STYLE 10: PIN 1. D(OUT)+ 2. GND 3. D(OUT)− 4. D(IN)− 5. VBUS 6. D(IN)+ STYLE 11: PIN 1. SOURCE 1 2. DRAIN 2 3. DRAIN 2 4. SOURCE 2 5. GATE 1 6. DRAIN 1/GATE 2 STYLE 12: PIN 1. I/O 2. GROUND 3. I/O 4. I/O 5. VCC 6. I/O STYLE 13: PIN 1. GATE 1 2. SOURCE 2 3. GATE 2 4. DRAIN 2 5. SOURCE 1 6. DRAIN 1 STYLE 14: PIN 1. ANODE 2. SOURCE 3. GATE 4. CATHODE/DRAIN 5. CATHODE/DRAIN 6. CATHODE/DRAIN STYLE 15: PIN 1. ANODE 2. SOURCE 3. GATE 4. DRAIN 5. N/C 6. CATHODE STYLE 16: PIN 1. ANODE/CATHODE 2. BASE 3. EMITTER 4. COLLECTOR 5. ANODE 6. CATHODE STYLE 17: PIN 1. EMITTER 2. BASE 3. ANODE/CATHODE 4. ANODE 5. CATHODE 6. COLLECTOR GENERIC MARKING DIAGRAM* RECOMMENDED SOLDERING FOOTPRINT* 6X 0.60 XXXAYWG G 1 6X 3.20 XXX A Y W G 0.95 PITCH DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. DOCUMENT NUMBER: DESCRIPTION: 98ASB14888C TSOP−6 1 IC 0.95 XXX MG G = Specific Device Code =Assembly Location = Year = Work Week = Pb−Free Package STANDARD XXX = Specific Device Code M = Date Code G = Pb−Free Package *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “ G”, may or may not be present. Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 1 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2019 www.onsemi.com MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS DFN8, 4x4 CASE 488AF−01 ISSUE C 1 SCALE 2:1 A B D PIN ONE REFERENCE 2X 0.15 C 2X 0.15 C 0.10 C 8X ÉÉ ÉÉ ÉÉ 0.08 C DETAIL A E OPTIONAL CONSTRUCTIONS EXPOSED Cu DETAIL B ÇÇÇÇ (A3) A A1 C D2 ÇÇÇÇ e 8X SEATING PLANE ÉÉÉ ÉÉÉ ÇÇÇ A3 A1 ALTERNATE CONSTRUCTIONS 8X MILLIMETERS MIN MAX 0.80 1.00 0.00 0.05 0.20 REF 0.25 0.35 4.00 BSC 1.91 2.21 4.00 BSC 2.09 2.39 0.80 BSC 0.20 −−− 0.30 0.50 −−− 0.15 XXXXXX XXXXXX ALYWG G E2 5 DIM A A1 A3 b D D2 E E2 e K L L1 GENERIC MARKING DIAGRAM* L 4 ÇÇÇÇ 8 MOLD CMPD DETAIL B SIDE VIEW K ÇÇÇ ÇÇÇ ÉÉÉ TOP VIEW 1 NOTES: 1. DIMENSIONS AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.15 AND 0.30MM FROM TERMINAL TIP. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. 5. DETAILS A AND B SHOW OPTIONAL CONSTRUCTIONS FOR TERMINALS. L L L1 NOTE 4 DETAIL A DATE 15 JAN 2009 b XXXX = Specific Device Code A = Assembly Location L = Wafer Lot Y = Year W = Work Week G = Pb−Free Package (Note: Microdot may be in either location) 0.10 C A B 0.05 C NOTE 3 BOTTOM VIEW SOLDERING FOOTPRINT* 2.21 8X *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “ G”, may or may not be present. 0.63 4.30 2.39 PACKAGE OUTLINE 8X 0.35 0.80 PITCH DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. DOCUMENT NUMBER: DESCRIPTION: 98AON15232D DFN8, 4X4, 0.8P Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 1 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2019 www.onsemi.com MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS DFN8, 2.0x2.2, 0.5P CASE 506BP−01 ISSUE A 8 DATE 13 JAN 2010 1 SCALE 4:1 A B D PIN ONE REFERENCE 2X NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.15 AND 0.30 mm FROM TERMINAL. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. L L L1 ÉÉÉ ÉÉÉ ÉÉÉ DETAIL A E ALTERNATE TERMINAL CONSTRUCTIONS 0.10 C 2X 0.10 C ÇÇÇ ÇÇÇ ÉÉÉ EXPOSED Cu TOP VIEW (A3) DETAIL B 0.05 C DIM A A1 A3 b D D2 E E2 e K L L1 A MOLD CMPD DETAIL B 9X ALTERNATE CONSTRUCTIONS 0.05 C NOTE 4 SIDE VIEW A1 C SEATING PLANE D2 DETAIL A L 1 8 K 5 e 1.43 1.05 0.20 0.25 --- 1 4 E2 8X 0.20 0.10 C A B 8X b 0.10 C A B e/2 BOTTOM VIEW 0.05 C MILLIMETERS TYP MAX --1.00 --0.05 0.20 REF --0.30 2.00 BSC --1.53 2.20 BSC --1.25 0.50 BSC 0.22 0.30 --0.35 --0.15 GENERIC MARKING DIAGRAM* 0.10 C A B 8X MIN 0.80 0.00 NOTE 3 XXMG G XX = Specific Device Code M = Date Code G = Pb−Free Device *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “ G”, may or may not be present. SOLDERING FOOTPRINT* 1.63 ÇÇ Ç ÇÇ ÇÇ ÇÇÇÇÇÇÇ 1.15 ÇÇÇÇÇÇÇ ÇÇÇÇÇÇÇ ÇÇÇÇÇÇÇ 1 0.50 PITCH 8X 0.45 2.50 8X 0.28 DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. DOCUMENT NUMBER: DESCRIPTION: 98AON38697E DFN8, 2.0X2.2, 0.5P Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 1 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2019 www.onsemi.com MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS SOIC−8 NB CASE 751−07 ISSUE AK 8 1 SCALE 1:1 −X− DATE 16 FEB 2011 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. 751−01 THRU 751−06 ARE OBSOLETE. NEW STANDARD IS 751−07. A 8 5 S B 0.25 (0.010) M Y M 1 4 −Y− K G C N X 45 _ SEATING PLANE −Z− 0.10 (0.004) H M D 0.25 (0.010) M Z Y S X J S 8 8 1 1 IC 4.0 0.155 XXXXX A L Y W G IC (Pb−Free) = Specific Device Code = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package XXXXXX AYWW 1 1 Discrete XXXXXX AYWW G Discrete (Pb−Free) XXXXXX = Specific Device Code A = Assembly Location Y = Year WW = Work Week G = Pb−Free Package *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “G”, may or may not be present. Some products may not follow the Generic Marking. 1.270 0.050 SCALE 6:1 INCHES MIN MAX 0.189 0.197 0.150 0.157 0.053 0.069 0.013 0.020 0.050 BSC 0.004 0.010 0.007 0.010 0.016 0.050 0 _ 8 _ 0.010 0.020 0.228 0.244 8 8 XXXXX ALYWX G XXXXX ALYWX 1.52 0.060 0.6 0.024 MILLIMETERS MIN MAX 4.80 5.00 3.80 4.00 1.35 1.75 0.33 0.51 1.27 BSC 0.10 0.25 0.19 0.25 0.40 1.27 0_ 8_ 0.25 0.50 5.80 6.20 GENERIC MARKING DIAGRAM* SOLDERING FOOTPRINT* 7.0 0.275 DIM A B C D G H J K M N S mm Ǔ ǒinches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. STYLES ON PAGE 2 DOCUMENT NUMBER: DESCRIPTION: 98ASB42564B SOIC−8 NB Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 2 onsemi and are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2019 www.onsemi.com SOIC−8 NB CASE 751−07 ISSUE AK DATE 16 FEB 2011 STYLE 1: PIN 1. EMITTER 2. COLLECTOR 3. COLLECTOR 4. EMITTER 5. EMITTER 6. BASE 7. BASE 8. EMITTER STYLE 2: PIN 1. COLLECTOR, DIE, #1 2. COLLECTOR, #1 3. COLLECTOR, #2 4. COLLECTOR, #2 5. BASE, #2 6. EMITTER, #2 7. BASE, #1 8. EMITTER, #1 STYLE 3: PIN 1. DRAIN, DIE #1 2. DRAIN, #1 3. DRAIN, #2 4. DRAIN, #2 5. GATE, #2 6. SOURCE, #2 7. GATE, #1 8. SOURCE, #1 STYLE 4: PIN 1. ANODE 2. ANODE 3. ANODE 4. ANODE 5. ANODE 6. ANODE 7. ANODE 8. COMMON CATHODE STYLE 5: PIN 1. DRAIN 2. DRAIN 3. DRAIN 4. DRAIN 5. GATE 6. GATE 7. SOURCE 8. SOURCE STYLE 6: PIN 1. SOURCE 2. DRAIN 3. DRAIN 4. SOURCE 5. SOURCE 6. GATE 7. GATE 8. SOURCE STYLE 7: PIN 1. INPUT 2. EXTERNAL BYPASS 3. THIRD STAGE SOURCE 4. GROUND 5. DRAIN 6. GATE 3 7. SECOND STAGE Vd 8. FIRST STAGE Vd STYLE 8: PIN 1. COLLECTOR, DIE #1 2. BASE, #1 3. BASE, #2 4. COLLECTOR, #2 5. COLLECTOR, #2 6. EMITTER, #2 7. EMITTER, #1 8. COLLECTOR, #1 STYLE 9: PIN 1. EMITTER, COMMON 2. COLLECTOR, DIE #1 3. COLLECTOR, DIE #2 4. EMITTER, COMMON 5. EMITTER, COMMON 6. BASE, DIE #2 7. BASE, DIE #1 8. EMITTER, COMMON STYLE 10: PIN 1. GROUND 2. BIAS 1 3. OUTPUT 4. GROUND 5. GROUND 6. BIAS 2 7. INPUT 8. GROUND STYLE 11: PIN 1. SOURCE 1 2. GATE 1 3. SOURCE 2 4. GATE 2 5. DRAIN 2 6. DRAIN 2 7. DRAIN 1 8. DRAIN 1 STYLE 12: PIN 1. SOURCE 2. SOURCE 3. SOURCE 4. GATE 5. DRAIN 6. DRAIN 7. DRAIN 8. DRAIN STYLE 13: PIN 1. N.C. 2. SOURCE 3. SOURCE 4. GATE 5. DRAIN 6. DRAIN 7. DRAIN 8. DRAIN STYLE 14: PIN 1. N−SOURCE 2. N−GATE 3. P−SOURCE 4. P−GATE 5. P−DRAIN 6. P−DRAIN 7. N−DRAIN 8. N−DRAIN STYLE 15: PIN 1. ANODE 1 2. ANODE 1 3. ANODE 1 4. ANODE 1 5. CATHODE, COMMON 6. CATHODE, COMMON 7. CATHODE, COMMON 8. CATHODE, COMMON STYLE 16: PIN 1. EMITTER, DIE #1 2. BASE, DIE #1 3. EMITTER, DIE #2 4. BASE, DIE #2 5. COLLECTOR, DIE #2 6. COLLECTOR, DIE #2 7. COLLECTOR, DIE #1 8. COLLECTOR, DIE #1 STYLE 17: PIN 1. VCC 2. V2OUT 3. V1OUT 4. TXE 5. RXE 6. VEE 7. GND 8. ACC STYLE 18: PIN 1. ANODE 2. ANODE 3. SOURCE 4. GATE 5. DRAIN 6. DRAIN 7. CATHODE 8. CATHODE STYLE 19: PIN 1. SOURCE 1 2. GATE 1 3. SOURCE 2 4. GATE 2 5. DRAIN 2 6. MIRROR 2 7. DRAIN 1 8. MIRROR 1 STYLE 20: PIN 1. SOURCE (N) 2. GATE (N) 3. SOURCE (P) 4. GATE (P) 5. DRAIN 6. DRAIN 7. DRAIN 8. DRAIN STYLE 21: PIN 1. CATHODE 1 2. CATHODE 2 3. CATHODE 3 4. CATHODE 4 5. CATHODE 5 6. COMMON ANODE 7. COMMON ANODE 8. CATHODE 6 STYLE 22: PIN 1. I/O LINE 1 2. COMMON CATHODE/VCC 3. COMMON CATHODE/VCC 4. I/O LINE 3 5. COMMON ANODE/GND 6. I/O LINE 4 7. I/O LINE 5 8. COMMON ANODE/GND STYLE 23: PIN 1. LINE 1 IN 2. COMMON ANODE/GND 3. COMMON ANODE/GND 4. LINE 2 IN 5. LINE 2 OUT 6. COMMON ANODE/GND 7. COMMON ANODE/GND 8. LINE 1 OUT STYLE 24: PIN 1. BASE 2. EMITTER 3. COLLECTOR/ANODE 4. COLLECTOR/ANODE 5. CATHODE 6. CATHODE 7. COLLECTOR/ANODE 8. COLLECTOR/ANODE STYLE 25: PIN 1. VIN 2. N/C 3. REXT 4. GND 5. IOUT 6. IOUT 7. IOUT 8. IOUT STYLE 26: PIN 1. GND 2. dv/dt 3. ENABLE 4. ILIMIT 5. SOURCE 6. SOURCE 7. SOURCE 8. VCC STYLE 29: PIN 1. BASE, DIE #1 2. EMITTER, #1 3. BASE, #2 4. EMITTER, #2 5. COLLECTOR, #2 6. COLLECTOR, #2 7. COLLECTOR, #1 8. COLLECTOR, #1 STYLE 30: PIN 1. DRAIN 1 2. DRAIN 1 3. GATE 2 4. SOURCE 2 5. SOURCE 1/DRAIN 2 6. SOURCE 1/DRAIN 2 7. SOURCE 1/DRAIN 2 8. GATE 1 DOCUMENT NUMBER: DESCRIPTION: 98ASB42564B SOIC−8 NB STYLE 27: PIN 1. ILIMIT 2. OVLO 3. UVLO 4. INPUT+ 5. SOURCE 6. SOURCE 7. SOURCE 8. DRAIN STYLE 28: PIN 1. SW_TO_GND 2. DASIC_OFF 3. DASIC_SW_DET 4. GND 5. V_MON 6. VBULK 7. VBULK 8. VIN Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 2 OF 2 onsemi and are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2019 www.onsemi.com onsemi, , and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. 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