NTD4860NT4G

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Other names and brands may be claimed as the property of others. NTD4860N MOSFET – Power, Single, N-Channel, DPAK/IPAK 25 V, 65 A Features http://onsemi.com Trench Technology Low RDS(on) to Minimize Conduction Losses Low Capacitance to Minimize Driver Losses Optimized Gate Charge to Minimize Switching Losses These are Pb−Free Devices V(BR)DSS RDS(ON) MAX ID MAX 7.5 mW @ 10 V 25 V 65 A 11.1 mW @ 4.5 V Applications D • VCORE Applications • DC−DC Converters • High/Low Side Switching N−Channel G S MAXIMUM RATINGS (TJ = 25°C unless otherwise stated) Value Unit Drain−to−Source Voltage VDSS 25 V Gate−to−Source Voltage VGS ±20 V ID 13 A Continuous Drain Current RqJA (Note 1) TA = 25°C Power Dissipation RqJA (Note 1) TA = 25°C PD 2.0 W Continuous Drain Current RqJA (Note 2) TA = 25°C ID 10.4 A Power Dissipation RqJA (Note 2) TA = 85°C Steady State 10 TA = 85°C TA = 25°C ID 1.28 TC = 25°C Power Dissipation RqJC (Note 1) TC = 25°C PD 50 W TA = 25°C IDM 130 A TA = 25°C IDmaxPkg 45 A TJ, TSTG −55 to +175 °C IS 42 A TC = 85°C tp=10ms Current Limited by Package Operating Junction and Storage Temperature Source Current (Body Diode) A 65 50 Drain to Source dV/dt dV/dt 6 V/ns Single Pulse Drain−to−Source Avalanche Energy (TJ = 25°C, VDD = 50 V, VGS = 10 V, IL = 13 Apk, L = 1.0 mH, RG = 25 W) EAS 84.5 mJ Lead Temperature for Soldering Purposes (1/8” from case for 10 s) TL 260 °C Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. © Semiconductor Components Industries, LLC, 2014 May, 2019 − Rev. 2 1 2 3 DPAK CASE 369AA (Bent Lead) STYLE 2 1 1 2 3 3 IPAK CASE 369AC (Straight Lead) 1 2 3 IPAK CASE 369D (Straight Lead DPAK) STYLE 2 MARKING DIAGRAMS & PIN ASSIGNMENTS W Continuous Drain Current RqJC (Note 1) Pulsed Drain Current 4 8.0 PD 4 4 4 Drain 4 Drain AYWW 48 60NG Symbol AYWW 48 60NG Parameter 4 Drain AYWW 48 60NG • • • • • 2 1 2 3 1 Drain 3 Gate Source Gate Drain Source 1 2 3 Gate Drain Source A Y WW 4860N G = Assembly Location* = Year = Work Week = Device Code = Pb−Free Package * The Assembly Location code (A) is front side optional. In cases where the Assembly Location is stamped in the package, the front side assembly code may be blank. ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 6 of this data sheet. Publication Order Number: NTD4860N/D NTD4860N THERMAL RESISTANCE MAXIMUM RATINGS Symbol Value Junction−to−Case (Drain) Parameter RqJC 3 Junction−to−TAB (Drain) RqJC−TAB 3.5 Junction−to−Ambient – Steady State (Note 1) RqJA 75 Junction−to−Ambient – Steady State (Note 2) RqJA 117 Unit °C/W 1. Surface−mounted on FR4 board using 1 sq−in pad, 1 oz Cu. 2. Surface−mounted on FR4 board using the minimum recommended pad size. ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise specified) Parameter Symbol Test Condition Min Drain−to−Source Breakdown Voltage V(BR)DSS VGS = 0 V, ID = 250 mA 25 Drain−to−Source Breakdown Voltage Temperature Coefficient V(BR)DSS/ TJ Typ Max Unit OFF CHARACTERISTICS Zero Gate Voltage Drain Current Gate−to−Source Leakage Current IDSS V 21 VGS = 0 V, VDS = 20 V mV/°C TJ = 25°C 1.0 TJ = 125°C 10 IGSS VDS = 0 V, VGS = ±20 V VGS(TH) VGS = VDS, ID = 250 mA mA ±100 nA 2.5 V ON CHARACTERISTICS (Note 3) Gate Threshold Voltage Negative Threshold Temperature Coefficient VGS(TH)/TJ Drain−to−Source On Resistance RDS(on) Forward Transconductance gFS 1.45 5.2 mV/°C VGS = 10 V ID = 30 A 6.1 7.5 VGS = 4.5 V ID = 30 A 8.9 11.1 VDS = 1.5 V, ID = 15 A 48 mW S CHARGES AND CAPACITANCES Input Capacitance CISS Output Capacitance COSS Reverse Transfer Capacitance CRSS 169 Total Gate Charge QG(TOT) 11 Threshold Gate Charge QG(TH) Gate−to−Source Charge QGS Gate−to−Drain Charge Total Gate Charge 1308 VGS = 0 V, f = 1.0 MHz, VDS = 12 V VGS = 4.5 V, VDS = 15 V, ID = 30 A QGD QG(TOT) 342 1.2 3.9 pF 16.5 nC 4.7 VGS = 10 V, VDS = 15 V, ID = 30 A 21.8 nC SWITCHING CHARACTERISTICS (Note 4) Turn−On Delay Time Rise Time Turn−Off Delay Time Fall Time td(ON) tr td(OFF) 12.2 VGS = 4.5 V, VDS = 15 V, ID = 15 A, RG = 3.0 W tf 20.1 15.2 ns 4.3 Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 3. Pulse Test: pulse width ≤ 300 ms, duty cycle ≤ 2%. 4. Switching characteristics are independent of operating junction temperatures. http://onsemi.com 2 NTD4860N ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise specified) (continued) Parameter Symbol Test Condition Min Typ Max Unit SWITCHING CHARACTERISTICS (Note 4) Turn−On Delay Time Rise Time Turn−Off Delay Time Fall Time td(ON) tr td(OFF) 7.1 VGS = 11.5 V, VDS = 15 V, ID = 15 A, RG = 3.0 W tf 17 ns 22 2.3 DRAIN−SOURCE DIODE CHARACTERISTICS Forward Diode Voltage Reverse Recovery Time VSD TJ = 25°C 0.9 TJ = 125°C 0.76 tRR Charge Time ta Discharge Time tb Reverse Recovery Charge VGS = 0 V, IS = 30 A 1.2 V 12.7 VGS = 0 V, dIS/dt = 100 A/ms, IS = 30 A 7.0 ns 5.7 QRR 3.5 Source Inductance LS 2.49 Drain Inductance, DPAK LD 0.0164 Drain Inductance, IPAK LD Gate Inductance LG 3.46 Gate Resistance RG 0.75 nC PACKAGE PARASITIC VALUES TA = 25°C 1.88 nH W Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 3. Pulse Test: pulse width ≤ 300 ms, duty cycle ≤ 2%. 4. Switching characteristics are independent of operating junction temperatures. http://onsemi.com 3 NTD4860N TYPICAL PERFORMANCE CURVES VDS ≥ 10 V 3.8 V 50 TJ = 25°C 3.6 V 40 3.4 V 30 3.2 V 20 3.0 V 10 2.8 V 0 1 2 3 4 TJ = 125°C 10 TJ = 25°C TJ = −55°C 0 2 1 3 4 5 Figure 2. Transfer Characteristics 0.032 0.028 0.024 0.020 0.016 0.012 0.008 0.004 3 4 5 6 7 8 9 10 11 0.012 TJ = 25°C 0.011 0.010 0.009 VGS = 4.5 V 0.008 0.007 0.006 VGS = 11.5 V 0.005 0.004 10 20 30 40 50 60 VGS, GATE−TO−SOURCE VOLTAGE (VOLTS) ID, DRAIN CURRENT (AMPS) Figure 3. On−Resistance vs. Gate−to−Source Voltage Figure 4. On−Resistance vs. Drain Current and Gate Voltage 1.8 10000 VGS = 0 V ID = 30 A VGS = 10 V IDSS, LEAKAGE (nA) RDS(on), DRAIN−TO−SOURCE RESISTANCE (NORMALIZED) 20 Figure 1. On−Region Characteristics ID = 30 A TJ = 25°C 1.6 30 VGS, GATE−TO−SOURCE VOLTAGE (VOLTS) 0.040 2 40 VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) 0.036 0 50 0 5 RDS(on), DRAIN−TO−SOURCE RESISTANCE (W) 0 RDS(on), DRAIN−TO−SOURCE RESISTANCE (W) 60 4V 10V ID, DRAIN CURRENT (AMPS) ID, DRAIN CURRENT (AMPS) 60 1.4 1.2 1.0 TJ = 150°C 1000 TJ = 125°C 100 0.8 0.6 −50 −25 0 25 50 75 100 125 150 175 10 2 4 6 8 10 12 14 16 18 TJ, JUNCTION TEMPERATURE (°C) VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) Figure 5. On−Resistance Variation with Temperature Figure 6. Drain−to−Source Leakage Current vs. Drain Voltage http://onsemi.com 4 20 NTD4860N C, CAPACITANCE (pF) 2000 1500 VGS , GATE−TO−SOURCE VOLTAGE (VOLTS) TYPICAL PERFORMANCE CURVES VGS = 0 V TJ = 25°C Ciss 1000 Coss 500 Crss 0 0 5 10 15 20 25 DRAIN−TO−SOURCE VOLTAGE (VOLTS) 10 8 6 IS, SOURCE CURRENT (AMPS) 100 2 td(off) tr td(on) tf 10 RG, GATE RESISTANCE (OHMS) 10 15 20 25 VGS = 0 V 25 20 15 10 5 10 ms 100 ms VGS = 20 V SINGLE PULSE TC = 25°C 1 ms 10 ms dc RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 1 0.5 0.6 0.7 0.8 1.0 0.9 Figure 10. Diode Forward Voltage vs. Current 100 10 TJ = 25°C VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS) 10 100 VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) EAS, SINGLE PULSE DRAIN−TO−SOURCE AVALANCHE ENERGY (mJ) I D, DRAIN CURRENT (AMPS) 5 QG, TOTAL GATE CHARGE (nC) 0 0.4 100 1000 0.1 0.1 ID = 30 A TJ = 25°C 0 0 Figure 9. Resistive Switching Time Variation vs. Gate Resistance 1 Q2 30 VDD = 15 V ID = 15 A VGS = 11.5 V t, TIME (ns) Q1 Figure 8. Gate−To−Source and Drain−To−Source Voltage vs. Total Charge 1000 1 1 VGS 4 Figure 7. Capacitance Variation 10 QT 100 ID = 13 A 90 80 70 60 50 40 30 20 10 0 25 Figure 11. Maximum Rated Forward Biased Safe Operating Area 50 75 100 125 150 TJ, JUNCTION TEMPERATURE (°C) Figure 12. Maximum Avalanche Energy vs. Starting Junction Temperature http://onsemi.com 5 175 NTD4860N r(t), EFFECTIVE TRANSIENT THERMAL RESISTANCE (NORMALIZED) TYPICAL PERFORMANCE CURVES 1.0 D = 0.5 0.2 0.1 0.1 0.05 P(pk) 0.02 0.01 SINGLE PULSE 0.01 1.0E-05 1.0E-04 t1 t2 DUTY CYCLE, D = t1/t2 1.0E-03 1.0E-02 t, TIME (ms) RqJC(t) = r(t) RqJC D CURVES APPLY FOR POWER PULSE TRAIN SHOWN READ TIME AT t1 TJ(pk) − TC = P(pk) RqJC(t) 1.0E-01 1.0E+00 1.0E+01 Figure 13. Thermal Response ORDERING INFORMATION Package Shipping† NTD4860NT4G DPAK (Pb−Free) 2500 / Tape & Reel NTD4860N−1G IPAK (Pb−Free) 75 Units / Rail NTD4860N−35G IPAK Trimmed Lead (3.5 ± 0.15 mm) (Pb−Free) 75 Units / Rail Device †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. http://onsemi.com 6 NTD4860N PACKAGE DIMENSIONS DPAK (SINGLE GUAGE) CASE 369AA ISSUE B A E b3 c2 B Z D 1 L4 A 4 L3 b2 e 2 NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: INCHES. 3. THERMAL PAD CONTOUR OPTIONAL WITHIN DIMENSIONS b3, L3 and Z. 4. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH, PROTRUSIONS, OR BURRS. MOLD FLASH, PROTRUSIONS, OR GATE BURRS SHALL NOT EXCEED 0.006 INCHES PER SIDE. 5. DIMENSIONS D AND E ARE DETERMINED AT THE OUTERMOST EXTREMES OF THE PLASTIC BODY. 6. DATUMS A AND B ARE DETERMINED AT DATUM PLANE H. C H DETAIL A 3 DIM A A1 b b2 b3 c c2 D E e H L L1 L2 L3 L4 Z c b 0.005 (0.13) M H C L2 GAUGE PLANE C L SEATING PLANE A1 L1 DETAIL A ROTATED 905 CW STYLE 2: PIN 1. GATE 2. DRAIN 3. SOURCE 4. DRAIN SOLDERING FOOTPRINT* 6.20 0.244 2.58 0.102 5.80 0.228 3.00 0.118 1.60 0.063 INCHES MIN MAX 0.086 0.094 0.000 0.005 0.025 0.035 0.030 0.045 0.180 0.215 0.018 0.024 0.018 0.024 0.235 0.245 0.250 0.265 0.090 BSC 0.370 0.410 0.055 0.070 0.108 REF 0.020 BSC 0.035 0.050 −−− 0.040 0.155 −−− 6.17 0.243 SCALE 3:1 mm Ǔ ǒinches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. http://onsemi.com 7 MILLIMETERS MIN MAX 2.18 2.38 0.00 0.13 0.63 0.89 0.76 1.14 4.57 5.46 0.46 0.61 0.46 0.61 5.97 6.22 6.35 6.73 2.29 BSC 9.40 10.41 1.40 1.78 2.74 REF 0.51 BSC 0.89 1.27 −−− 1.01 3.93 −−− NTD4860N PACKAGE DIMENSIONS 3 IPAK, STRAIGHT LEAD CASE 369AC ISSUE O B V NOTES: 1.. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2.. CONTROLLING DIMENSION: INCH. 3. SEATING PLANE IS ON TOP OF DAMBAR POSITION. 4. DIMENSION A DOES NOT INCLUDE DAMBAR POSITION OR MOLD GATE. C E R DIM A B C D E F G H J K R V W A SEATING PLANE K W F J G D H 3 PL 0.13 (0.005) W INCHES MIN MAX 0.235 0.245 0.250 0.265 0.086 0.094 0.027 0.035 0.018 0.023 0.037 0.043 0.090 BSC 0.034 0.040 0.018 0.023 0.134 0.142 0.180 0.215 0.035 0.050 0.000 0.010 MILLIMETERS MIN MAX 5.97 6.22 6.35 6.73 2.19 2.38 0.69 0.88 0.46 0.58 0.94 1.09 2.29 BSC 0.87 1.01 0.46 0.58 3.40 3.60 4.57 5.46 0.89 1.27 0.000 0.25 IPAK CASE 369D ISSUE C C B V NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. E R 4 Z A S 1 2 3 −T− SEATING PLANE K J F D G H 3 PL 0.13 (0.005) M DIM A B C D E F G H J K R S V Z INCHES MIN MAX 0.235 0.245 0.250 0.265 0.086 0.094 0.027 0.035 0.018 0.023 0.037 0.045 0.090 BSC 0.034 0.040 0.018 0.023 0.350 0.380 0.180 0.215 0.025 0.040 0.035 0.050 0.155 −−− MILLIMETERS MIN MAX 5.97 6.35 6.35 6.73 2.19 2.38 0.69 0.88 0.46 0.58 0.94 1.14 2.29 BSC 0.87 1.01 0.46 0.58 8.89 9.65 4.45 5.45 0.63 1.01 0.89 1.27 3.93 −−− STYLE 2: PIN 1. GATE 2. DRAIN 3. SOURCE 4. DRAIN T ON Semiconductor and the are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries. SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. 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This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada Email: orderlit@onsemi.com N. American Technical Support: 800−282−9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81−3−5817−1050 http://onsemi.com 8 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative NTD4860N/D