Operational Amplifier,
Rail-to-Rail Output, 3 MHz
BW
TLV271, TLV272, NCV272,
TLV274, NCV274
The TLV/NCV27x operational amplifiers provide rail−to−rail
output operation. The output can swing within 320 mV to the positive
rail and 50 mV to the negative rail. This rail−to−rail operation enables
the user to make optimal use of the entire supply voltage range while
taking advantage of 3 MHz bandwidth. The opamp can operate on
supply voltage as low as 2.7 V over the temperature range of −40°C to
125°C. The high bandwidth provides a slew rate of 2.4 V/ms while
only consuming 550 mA of quiescent current. Likewise the opamp can
run on a supply voltage as high as 16 V (single) and 36 V (dual quad)
making it ideal for a broad range of battery−operated applications.
Since this is a CMOS device it has high input impedance and low bias
currents making it ideal for interfacing to a wide variety of signal
sensors. In addition it comes in a variety of compact packages with
different pinout styles allowing for use in high−density PCB’s.
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5
1
TSOP−5
CASE 483
8
1
SOIC−8
CASE 751
Micro8
CASE 846A
Features
•
•
•
•
•
•
•
•
•
•
Rail−To−Rail Output
Wide Bandwidth: 3 MHz
High Slew Rate: 2.4 V/ms
Wide Power−Supply Range: 2.7 V to 16 V (TLV271),
36 V (TLV/NCV272/274)
Low Supply Current: 550 mA
Low Input Bias Current: 45 pA
Wide Temperature Range: −40°C to 125°C
TSOP−5, Micro−8, SOIC−8, SOIC−14, TSSOP−14 Packages
NCV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
14
14
1
SOIC−14 NB
CASE 751A
1
TSSOP−14
CASE 948G
DEVICE MARKING INFORMATION
See general marking information in the device marking
section on page 2 of this data sheet.
ORDERING INFORMATION
See detailed ordering and shipping information on page 3 of
this data sheet.
Applications
•
•
•
•
•
•
Notebook Computers
Portable Instruments
Signal Conditioning
Automotive
Power Supplies
Current Sensing
© Semiconductor Components Industries, LLC, 2013
July, 2020 − Rev. 7
1
Publication Order Number:
TLV271/D
TLV271, TLV272, NCV272, TLV274, NCV274
MARKING DIAGRAMS
Single Channel Configuration
TLV271
5
XXX
= ADG (TLV271SN1T1G)
= ADH (TLV271SN2T1G)
A
= Assembly Location
Y
= Year
W
= Work Week
G
= Pb−Free Package
(Note: Microdot may be in either location)
XXXAYWG
G
1
TSOP−5
CASE 483
Dual Channel Configuration
TLV272, NCV272
8
8
V272
ALYW
G
V272
AYWG
G
1
1
Micro8
CASE 846A
SOIC−8
CASE 751
Quad Channel Configuration
TLV274, NCV274
14
14
V274
ALYWG
G
V274G
AWLYWW
1
1
TSSOP−14
CASE 948G
SOIC−14 NB
CASE 751A
XXXXX
A
WL, L
Y
WW, W
G or G
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
(Note: Microdot may be in either location)
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2
TLV271, TLV272, NCV272, TLV274, NCV274
PIN CONNECTIONS
Single Channel Configuration
TLV271
IN+
3
1
VEE
2
4
IN−
IN+
3
Style 1 Pinout (SN1T1)
(Top View)
1
IN− 1
2
−
IN+ 1
3
+
VSS
4
VDD
4
IN−
Style 2 Pinout (SN2T1)
(Top View)
Quadruple Channel Configuration
TLV274, NCV274
Dual Channel Configuration
TLV272, NCV272
OUT 1
5
−
2
OUT
+
VDD
VEE
5
−
1
+
OUT
OUT 1 1
14 OUT 4
8
VDD
IN− 1 2
−
− 13 IN− 4
7
OUT 2
IN+ 1 3
+
+ 12 IN+ 4
−
6
IN− 2
+
5
IN+ 2
VDD 4
11 VSS
IN+ 2 5
+
+ 10 IN+ 3
IN− 2 6
−
−
OUT 2 7
9 IN− 3
8 OUT 3
ORDERING INFORMATION
Device
TLV271SN1T1G
(Style 1 Pinout)
TLV271SN2T1G
(Style 2 Pinout)
TLV272DR2G
TLV272DMR2G
TLV274DR2G
TLV274DTBR2G
NCV272DR2G*
NCV272DMR2G*
NCV274DR2G*
NCV274DTBR2G*
Configuration
Automotive
Marking
Package
ADG
Single
3000 / Tape and Reel
TSOP−5
ADH
Dual
Shipping†
No
Quad
Dual
Yes
Quad
3000 / Tape and Reel
V272
SOIC−8
2500 / Tape and Reel
V272
Micro−8/MSOP−8
4000 / Tape and Reel
V274
SOIC−14
2500 / Tape and Reel
V274
TSSOP−14
2500 / Tape and Reel
V272
SOIC−8
2500 / Tape and Reel
V272
Micro−8/MSOP−8
4000 / Tape and Reel
V274
SOIC−14
2500 / Tape and Reel
V274
TSSOP−14
2500 / Tape and Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*NCV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP
Capable.
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3
TLV271, TLV272, NCV272, TLV274, NCV274
MAXIMUM RATINGS
Symbol
Rating
Value
Unit
16.5
36
V
V
Input Differential Voltage
$Supply Voltage
V
Input Common Mode Voltage Range (Note 1)
−0.2 V to (VDD +
0.2 V)
V
Maximum Input Current
$10
mA
Output Current Range
$100
mA
Continuous Total Power Dissipation (Note 1)
200
mW
TJ
Maximum Junction Temperature
150
°C
TA
Operating Ambient Temperature Range (free−air)
−40 to 125
°C
Storage Temperature Range
−65 to 150
°C
2
kV
TBD
2
1
kV
kV
kV
260
°C
VDD
Supply Voltage (Note 1)
VID
VI
II
IO
TSTG
TLV271
TLV/NCV272/274
ESDHBM
ESD Capability, Human Body Model
ESDCDM
ESD Capability, Charged Device Model
TLV271
TLV/NCV272
TLV/NCV274
Mounting Temperature (Infrared or Convection − 20 sec)
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected.
1. Continuous short−circuit operation to ground at elevated ambient temperature can result in exceeding the maximum allowed junction
temperature of 150°C. Output currents in excess of 45 mA over long term may adversely affect reliability. Shorting output to either V+
or V− will adversely affect reliability.
THERMAL INFORMATION
Parameter
Junction−to−Ambient
Symbol
qJA
Package
Single Layer
Board (Note 2)
Multi−Layer
Board (Note 3)
TSOP−5
333
195
Micro−8 / MSOP−8
236
167
SOIC−8
190
131
SOIC−14
142
101
TSSOP−14
179
128
2. Values based on a 1S standard PCB according to JEDEC51−3 with 1.0 oz copper and a 300 mm2 copper area
3. Values based on a 1S2P standard PCB according to JEDEC51−7 with 1.0 oz copper and a 100 mm2 copper area
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4
Unit
°C/W
TLV271, TLV272, NCV272, TLV274, NCV274
TLV271 DC ELECTRICAL CHARACTERISTICS
(VDD = 2.7V, 3.3V, 5V & $5 V (Note 4), TA = 25°C, RL w 10 kW unless otherwise noted)
Parameter
Symbol
Input Offset Voltage
VIO
Conditions
Min
VIC = VDD/2, VO = VDD/2, RL = 10 kW, RS = 50 W
Typ
Max
Unit
0.5
5
mV
TA = −40°C to +105°C
Offset Voltage Drift
ICVOS
Common Mode
Rejection Ratio
CMRR
7
VIC = VDD/2, VO = VDD/2, RL = 10 kW, RS = 50 W
0 V v VIC v VDD − 1.35 V, RS = 50 W
VDD = 2.7 V
TA = −40°C to +105°C
VDD = 5 V
TA = −40°C to +105°C
Large Signal
Voltage Gain
AVD
VDD = $5 V
VDD = 2.7 V to 16 V, VIC = VDD/2, No Load
70
TA = −40°C to +105°C
65
VDD = 2.7 V
VO(pp) = VDD/2, RL = 10 kW
VDD = 3.3 V
VDD = 5 V
TA = −40°C to +105°C
VDD = $5 V
TA = −40°C to +105°C
ri(d)
Common−mode
Input Capacitance
CIC
97
140
135
dB
106
dB
97
123
100
127
86
VO(pp) = VDD/2, RL = 10 kW
Differential Input
Resistance
130
76
VO(pp) = VDD/2, RL = 10 kW
IIO
dB
76
TA = −40°C to +105°C
Input Offset Current
69
66
TA = −40°C to +105°C
IB
65
TA = −40°C to +105°C
VO(pp) = VDD/2, RL = 10 kW
Input Bias Current
mV/°C
62
0 V v VIC v VDD − 1.35 V, RS = 50 W
PSRR
2
70
55
0 V v VIC v VDD − 1.35 V, RS = 50 W
Power Supply
Rejection Ratio
58
100
130
90
VDD = 5 V, VIC = VDD/2, VO = VDD/2,
RS = 50 W
VDD = 5 V, VIC = VDD/2, VO = VDD/2,
RS = 50 W
f = 21 kHz
4. VDD = ±5 V is shorthand for VDD = +5 V and VEE = −5 V.
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5
TA = 25°C
45
TA = 105°C
TA = 25°C
150
pA
1000
45
TA = 105°C
150
pA
1000
1000
GW
8
pF
TLV271, TLV272, NCV272, TLV274, NCV274
TLV271 DC ELECTRICAL CHARACTERISTICS
(VDD = 2.7V, 3.3V, 5V & $5 V (Note 4), TA = 25°C, RL w 10 kW unless otherwise noted)
Parameter
Symbol
Output Swing
(High−level)
VOH
Conditions
VDD = 2.7 V
VIC = VDD/2, IOH = −1 mA
TA = −40°C to +105°C
VDD = 3.3 V
TA = −40°C to +105°C
2.55
2.58
TA = −40°C to +105°C
VDD = $5 V
TA = −40°C to +105°C
V
3.15
3.21
4.8
4.93
4.92
4.96
4.9
VDD = 2.7 V
VIC = VDD/2, IOH = −5 mA
TA = −40°C to +105°C
1.9
V
2.1
1.5
VDD = 3.3 V
VIC = VDD/2, IOH = −5 mA
TA = −40°C to +105°C
2.5
2.89
2.1
VDD = 5 V
VIC = VDD/2, IOH = −5 mA
TA = −40°C to +105°C
4.5
4.68
4.35
VDD = $5 V
VIC = VDD/2, IOH = −5 mA
TA = −40°C to +105°C
4.7
4.78
4.65
VDD = 2.7 V
VIC = VDD/2, IOL = −1 mA
0.1
TA = −40°C to +105°C
0.15
V
0.22
VDD = 3.3 V
VIC = VDD/2, IOL = −1 mA
0.03
TA = −40°C to +105°C
0.15
0.22
VIC = VDD/2, IOL = −1 mA
VDD = 5 V
0.03
VDD = $5 V
0.05
TA = −40°C to +105°C
0.1
0.15
VIC = VDD/2, IOL = −1 mA
TA = −40°C to +105°C
0.08
0.1
VDD = 2.7 V
VIC = VDD/2, IOL = −5 mA
0.5
TA = −40°C to +105°C
0.7
V
1.1
VDD = 3.3 V
VIC = VDD/2, IOL = −5 mA
0.13
TA = −40°C to +105°C
0.7
1.1
VDD = 5 V
VIC = VDD/2, IOL = −5 mA
0.13
TA = −40°C to +105°C
0.4
0.5
VDD = $5 V
VIC = VDD/2, IOL = −5 mA
0.16
TA = −40°C to +105°C
IO
Unit
4.75
VIC = VDD/2, IOH = −1 mA
Output Current
Max
3.00
VDD = 5 V
VIC = VDD/2, IOH = −1 mA
VOL
Typ
2.48
VIC = VDD/2, IOH = −1 mA
Output Swing
(Low−level)
Min
0.3
0.35
VO = 0.5 V from rail, VDD = 2.7 V
VO = 0.5 V from rail, VDD = 5 V
VO = 0.5 V from rail, VDD = 10 V
4. VDD = ±5 V is shorthand for VDD = +5 V and VEE = −5 V.
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6
Positive rail
4.0
Negative rail
5.0
Positive rail
7.0
Negative rail
8.0
Positive rail
13
Negative rail
12
mA
TLV271, TLV272, NCV272, TLV274, NCV274
TLV271 DC ELECTRICAL CHARACTERISTICS
(VDD = 2.7V, 3.3V, 5V & $5 V (Note 4), TA = 25°C, RL w 10 kW unless otherwise noted)
Parameter
Symbol
Power Supply
Quiescent Current
IDD
Conditions
VO = VDD/2
Min
Typ
Max
Unit
VDD = 2.7 V
380
560
mA
VDD = 3.3 V
385
620
VDD = 5 V
390
660
VDD = 10 V
400
TA = −40°C to +105°C
800
1000
4. VDD = ±5 V is shorthand for VDD = +5 V and VEE = −5 V.
TLV271 AC ELECTRICAL CHARACTERISTICS
(VDD = 2.7 V, 5 V, & $5 V (Note 5), TA = 25°C, and RL w 10 kW unless otherwise noted)
Parameter
Symbol
Unity Gain
Bandwidth
UGBW
Slew Rate at Unity
Gain
SR
Conditions
RL = 2 kW, CL = 10 pF
VO(pp) = VDD/2, RL = 10 kW, CL = 50 pF
Min
VDD = 2.7 V
3.2
VDD = 5 V to
10 V
3.5
VDD = 2.7 V
TA = −40°C to +105°C
VDD = 5 V
TA = −40°C to +105°C
VDD = $5 V
TA = −40°C to +105°C
Gain Margin
Settling Time to
0.1%
Total Harmonic
Distortion plus
Noise
tS
THD+N
en
Input−Referred
Current Noise
in
MHz
V/mS
1.45
2.3
1.8
2.6
1.3
RL = 2 kW, CL = 10 pF
45
°
RL = 2 kW, CL = 10 pF
14
dB
mS
V−step(pp) = 1 V, AV = −1, RL = 2 kW,
CL = 10 pF
VDD = 2.7 V
2.9
V−step(pp) = 1 V, AV = −1, RL = 2 kW,
CL = 47 pF
VDD = 5 V,
$5 V
2.0
AV = 1
0.004
AV = 10
0.04
AV = 100
0.3
VDD = 2.7 V, VO(pp) = VDD/2, RL = 2 kW,
f = 10 kHz
VDD = 5 V, $ 5 V, VO(pp) = VDD/2, RL =
2 kW, f = 10 kHz
Input−Referred
Voltage Noise
2.1
Unit
1.2
VO(pp) = VDD/2, RL = 10 kW, CL = 50 pF
qm
1.35
Max
1
VO(pp) = VDD/2, RL = 10 kW, CL = 50 pF
Phase Margin
Typ
AV = 1
0.004
AV = 10
0.04
AV = 100
0.03
f = 1 kHz
30
f = 10 kHz
20
f = 1 kHz
0.6
5. VDD = ±5 V is shorthand for VDD = +5 V and VEE = −5 V.
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7
%
nV/√Hz
fA/√Hz
TLV271, TLV272, NCV272, TLV274, NCV274
TLV/NCV 272/274 DC ELECTRICAL CHARACTERISTICS
((VDD = 2.7 V, 5 V, 10 V, 36 V), TA = 25°C, RL w 10 kW unless otherwise noted)
Parameter
Symbol
Input Offset Voltage
VIO
Conditions
Min
VIC = VDD/2, VO = VDD/2, RL = 10 kW
Typ
Max
Unit
1.3
±3
mV
TA = −40°C to +125°C
±4
Offset Voltage Drift
ICVOS
VIC = VDD/2, VO = VDD/2, RL = 10 kW
Common Mode
Rejection Ratio
CMRR
VCM = VSS + 0.2 V to VDD − 1.35 V
VDD = 2.7 V
TA = −40°C to +125°C
VDD = 5 V
TA = −40°C to +125°C
VDD = 10 V
TA = −40°C to +125°C
Large Signal
Voltage Gain
AVD
VDD = 36 V
(TLV/NCV272)
(TLV/NCV274)
114
VDD = 2.7 V
VO(pp) = VDD/2, RL = 10 kW
VDD = 5 V
145
96
135
dB
118
dB
96
120
86
VDD = 10 V
98
120
88
VDD = 36 V
VO(pp) = VDD/2, RL = 10 kW
TA = −40°C to +125°C
98
120
88
VDD = 5 V, VIC = VDD/2, VO = VDD/2
VDD = 2.7 to 36 V,
TA = −40°C to +125°C
XTLK
130
86
TA = −40°C to +125°C
Channel Separation
120
100
VO(pp) = VDD/2, RL = 10 kW
IIO
110
TA = −40°C to +125°C
TA = −40°C to +125°C
Input Offset Current
125
95
85
TA = −40°C to +125°C
IB
102
VDD = 2.7 V to 36 V, VIC = VDD/2, No Load
VO(pp) = VDD/2, RL = 10 kW
Input Bias Current
dB
87
VCM = VSS + 0.2 V to VDD − 1.35 V
PSRR
mV/°C
80
VCM = VSS + 0.2 V to VDD − 1.35 V
Power Supply
Rejection Ratio
2
110
69
VCM = VSS + 0.2 V to VDD − 1.35 V
TA = −40°C to +125°C
90
VDD = 5 V, VIC = VDD/2, VO = VDD/2,
RS = 50 W
TA = 25°C
5
200
TLV/NCV272
2000
TLV/NCV274
1500
TA = 25°C
2
75
pA
pA
VDD = 2.7 to 36 V,
TA = −40°C to +125°C
TLV/NCV272
DC
TLV/NCV272
100
dB
TLV/NCV274
115
dB
500
TLV/NCV274
200
Differential Input
Resistance
Ri(d)
5
GW
Common−mode
Input Capacitance
CIC
3.5
pF
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8
TLV271, TLV272, NCV272, TLV274, NCV274
TLV/NCV 272/274 DC ELECTRICAL CHARACTERISTICS
((VDD = 2.7 V, 5 V, 10 V, 36 V), TA = 25°C, RL w 10 kW unless otherwise noted)
Parameter
Symbol
Output Swing
(High−level)
VOH
Conditions
Min
VDD = 2.7 V
VIC = VDD/2
Typ
Max
Unit
0.006
0.15
V
TA = −40°C to +125°C
0.22
VIC = VDD/2
VDD = 5 V
0.013
VDD = 10 V
0.023
TA = −40°C to +125°C
0.25
VIC = VDD/2
TA = −40°C to +125°C
VDD = 36 V
0.074
TA = −40°C to +125°C
VOL
VIC = VDD/2
VDD = 2.7 V
0.005
VDD = 5 V
0.01
TA = −40°C to +125°C
VDD = 10 V
0.022
TA = −40°C to +125°C
0.10
0.3
0.35
VIC = VDD/2
VDD = 36 V
0.065
Positive rail
50
Negative rail
70
Positive rail
60
Negative rail
50
Positive rail
65
Negative rail
50
Positive rail
65
Negative rail
50
VDD = 2.7 V
405
525
VDD = 5 V
410
530
VDD = 10 V
416
540
VDD = 36 V
465
600
TA = −40°C to +125°C
0.3
0.35
VDD = 2.7 V
VDD = 5 V
VDD = 10 V
VDD = 36 V
IDD
V
0.15
VIC = VDD/2
Power Supply
Quiescent Current
0.15
0.22
TA = −40°C to +125°C
IO
0.10
0.15
VIC = VDD/2
Output Current
0.08
0.10
VIC = VDD/2
Output Swing
(Low−level)
0.20
VO = VDD/2,
Per channel, no load
TA = −40°C to +105°C
mA
mA
700
NOTE: Power dissipation must be limited to prevent junction temperature from exceeding 150°C. See Absolute Maximum Ratings for more
information.
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9
TLV271, TLV272, NCV272, TLV274, NCV274
TLV/NCV 272/274 AC ELECTRICAL CHARACTERISTICS
((VDD = 2.7 V, 5 V, 10 V, 36 V), TA = 25°C, and RL w 10 kW unless otherwise noted)
Parameter
Symbol
Unity Gain
Bandwidth
UGBW
Slew Rate at Unity
Gain
SR
Phase Margin
qm
Gain Margin
Settling Time to
0.1%
Total Harmonic
Distortion plus
Noise
tS
THD+N
Input−Referred
Voltage Noise
en
Input−Referred
Current Noise
in
Conditions
Min
Typ
Max
Unit
CL = 25 pF
VDD = 2.7 V
3
MHz
CL = 20 pF, RL = 2 kW
VDD = 2.7 V
2.8
V/mS
VDD = 5 V
2.7
VDD = 10 V
2.6
VDD = 36 V
2.4
CL = 25 pF
50
°
CL = 25 pF
14
dB
mS
VO = 1 Vpp, Gain = 1, CL = 20 pF
VDD = 2.7 V
0.6
VO = 3 Vpp, Gain = 1, CL = 20 pF
VDD = 5 V
1.2
VO = 8.5 Vpp, Gain = 1, CL = 20 pF
VDD = 10 V
3.4
VO = 10 Vpp, Gain = 1, CL = 20 pF
VDD = 36 V
3.2
VIN = 0.5 Vpp, f = 1 kHz, Av = 1
VDD = 2.7 V
0.05
VIN = 2.5 Vpp, f = 1 kHz, Av = 1
VDD = 5 V
0.009
VIN = 7.5 Vpp, f = 1 kHz, Av = 1
VDD = 10 V
0.004
VIN = 28.5 Vpp, f = 1 kHz, Av = 1
VDD = 36 V
0.001
f = 1 kHz
30
f = 10 kHz
20
f = 1 kHz
90
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10
%
nV/√Hz
fA/√Hz
TLV271, TLV272, NCV272, TLV274, NCV274
0
RL = 2 kW
25°C
−10
−20
−40
−50
2.5 V
−60
5V
2.7 V
−70
−80
−90
10 V
10
LOW LEVEL OUTPUT VOLTAGE (V)
2.5
100
1k
10k
100k
1M
200
150
100
0
−100
−40 −25 −10
5
20 35
50
65
Figure 2. Input Bias and Offset Current vs.
Temperature for TLV271
2.5
25°C
105°C
1.5
−40°C
1
0.5
0
10
20
30
40
50
60
70
VDD = 2.5 V
2
−40°C
1.5
25°C
105°C
1
0.5
0
80
0
10
20
30
40
50
LOW LEVEL OUTPUT CURRENT (mA)
Figure 3. 2.5 V VOL vs. Iout
Figure 4. 2.5 V VOH vs. Iout
3.3
HIGH LEVEL OUTPUT VOLTAGE (V)
25°C
2.7
105°C
2.4
2.1
1.8
−40°C
1.5
1.2
0.9
0.6
0.3
0
60
LOW LEVEL OUTPUT CURRENT (mA)
VDD = 3.3 V
3
80 95 110 125
Figure 1. CMRR vs. Frequency for TLV271
3.3
LOW LEVEL OUTPUT VOLTAGE (V)
Input Offset
−50
FREE AIR TEMPERATURE (°C)
2
0
Input Bias
50
FREQUENCY (Hz)
VDD = 2.5 V
0
250
HIGH LEVEL OUTPUT VOLTAGE (V)
CMRR (dB)
−30
INPUT BIAS AND OFFSET CURRENT (pA)
TYPICAL CHARACTERISTICS
10
20
30
40
50
60
70
80
90
80
VDD = 3.3 V
3
2.7
2.4
105°C
2.1
1.8
1.5
25°C
1.2
0.9
−40°C
0.6
0.3
0
0
10
20
30
40
50
60
70
HIGH LEVEL OUTPUT CURRENT (mA)
LOW LEVEL OUTPUT CURRENT (mA)
Figure 5. 3.3 V VOL vs. Iout
Figure 6. 3.3 V VOH vs. Iout
www.onsemi.com
11
70
80
90
TLV271, TLV272, NCV272, TLV274, NCV274
TYPICAL CHARACTERISTICS
HIGH LEVEL OUTPUT VOLTAGE (V)
105°C
4
3
−40°C
25°C
2
1
0
0
10
LOW LEVEL OUTPUT VOLTAGE (V)
5
VDD = 5.0 V
10
20
30
40
50
60
70
25°C
105°C
1
0
0
10
20
30
40
50
60
70
Figure 7. VOL vs. Iout
Figure 8. VOH vs. Iout
10
7
6
105°C
5
4
25°C
3
2
1
−40°C
0
10
20
30
40
50
60
70
80
80
VDD = 10 V
9
8
7
6
25°C
5
4
−40°C
3
105°C
2
1
0
0
10
20
30
40
50
60 70 80
90
100 110 120
LOW LEVEL OUTPUT CURRENT (mA)
HIGH LEVEL OUTPUT CURRENT (mA)
Figure 9. 10 V VOL vs. Iout
Figure 10. 10 V VOH vs. Iout
12
0.7
AV = 10
RL = 2k
CL = 10 pF
TA = 25°C
THD = 5%
VDD = 10 V
10
9
8
SUPPLY CURRENT (mA)
11
Vout P−P (V)
−40°C
2
HIGH LEVEL OUTPUT CURRENT (mA)
8
0
3
LOW LEVEL OUTPUT CURRENT (mA)
VDD = 10 V
9
VDD = 5.0 V
4
80
HIGH LEVEL OUTPUT VOLTAGE (V)
LOW LEVEL OUTPUT VOLTAGE (V)
5
7
6
VDD = 5 V
5
4
3
VDD = 2.7 V
2
VDD = 2.5 V
1
0
0.01
0.6
T = 125°C
T = 85°C
0.5
T = 25°C
0.4
T = −40°C
0.3
0.2
FREQUENCY (kHz)
12
18
24
SUPPLY VOLTAGE (V)
Figure 11. Peak−to−Peak Output vs. Supply vs.
Frequency
Figure 12. Quiescent Current Per Channel vs.
Supply Voltage for TLV/NCV272/274
0.1
1
10
100
1k
10k
0
www.onsemi.com
12
6
30
36
TLV271, TLV272, NCV272, TLV274, NCV274
TYPICAL CHARACTERISTICS
0
−30
−40
100
−50
−60
−70
80
60
40
−80
−90
20
−100
0
100
1k
10k
100k
10
100
1k
10k
100k
1M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 13. PSRR vs. Frequency for TLV271
Figure 14. PSRR vs. Frequency for
TLV/NCV272/274
140
180
Phase
2.7 V
OPEN LOOP GAIN (dB)
120
100
80
Gain
10 V
60
40
Gain
5V
20
135
Phase
5V
90
Phase
10 V
45
Gain
2.7 V
0
−20
1
10
100
1k
10k
100k
PHASE MARGIN (°C)
−110
VS = 2.7 V, VDD
VS = 2.7 V, VSS
VS = 36 V, VDD
VS = 36 V VSS
120
PSRR (dB)
−20
PSRR (dB)
140
RL = 2 kW,
Input = 200 mVpp,
AV = 1,
VDD = 2.5 V to 10 V,
TA = 25°C
−10
0
10M
1M
FREQUENCY (Hz)
Figure 15. Open Loop Gain and Phase vs.
Frequency
4.5
4
10 V
5V
3.5
3
2.7 V
2.5
2
−40
2.5 V
3
2
SR− @ 25°C
SR− @ −40°C
1
SR+ @ −40°C
RL = 2k
CL = 10 pF
−20
SR+ @ 105°C
SR− @ 105°C
SLEW RATE (V/ms)
FREQUENCY (MHz)
4
SR+ @ 25°C
0
20
40
60
80
100
0
0
0.5
1
1.5
2
2.5
3
TEMPERATURE (°C)
SUPPLY VOLTAGE (V)
Figure 16. Gain Bandwidth Product vs.
Temperature
Figure 17. Slew Rate vs. Supply Voltage
www.onsemi.com
13
3.5
TLV271, TLV272, NCV272, TLV274, NCV274
TYPICAL CHARACTERISTICS
4
SR+ 10 V
VOLTAGE NOISE (nV√Hz)
SLEW RATE (V/ms)
SR− 10 V
10k
SR+ 5 V
SR− 5 V
3
SR+ 2.7 V
2
1
SR− 2.7 V
VS = ±2.5 V
Vin = GND,
Av = 22 RTI
1k
100
10
1
−60
−40 −20
0
20
40
60
80
100
120
1
10
100
1k
10k
FREE AIR TEMPERATURE (°C)
FREQUENCY (Hz)
Figure 18. Slew Rate vs. Temperature
Figure 19. Voltage Noise vs. Frequency
VS = ±1.25 V
Av = −1
RL = 2 kW
100k
250 mV/div
250 mV/div
VS = +2.5 V
Av = +1
RL = 2 kW
Figure 20. 2.5 V Inverting Large Signal Pulse
Response
Figure 21. 2.5 V Non−Inverting Large Signal
Pulse Response
VS = ±1.25 V
Av = −1
RL = 2 kW
VS = +2.5 V
Av = +1
RL = 2 kW
25 mV/div
500 ns/div
25 mV/div
500 ns/div
500 ns/div
500 ns/div
Figure 22. 2.5 V Inverting Small Signal Pulse
Response
Figure 23. 2.5 V Non−Inverting Small Signal
Pulse Response
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14
TLV271, TLV272, NCV272, TLV274, NCV274
TYPICAL CHARACTERISTICS
VS = +3 V
Av = +1
RL = 2 kW
250 mV/div
250 mV/div
VS = ±1.5 V
Av = −1
RL = 2 kW
Figure 24. 3 V Inverting Large Signal Pulse
Response
Figure 25. 3 V Non−Inverting Large Signal
Pulse Response
VS = ±1.5 V
Av = −1
RL = 2 kW
VS = +3 V
Av = +1
RL = 2 kW
25 mV/div
500 ns/div
25 mV/div
500 ns/div
500 ns/div
500 ns/div
Figure 26. 3 V Inverting Small Signal Pulse
Response
Figure 27. 3 V Non−Inverting Small Signal
Pulse Response
VS = +6 V
Av = +1
RL = 2 kW
500 mV/div
500 mV/div
VS = ±3 V
Av = −1
RL = 2 kW
500 ns/div
500 ns/div
Figure 28. 6 V Inverting Large Signal Pulse
Response
Figure 29. 6 V Non−Inverting Large Signal
Pulse Response
www.onsemi.com
15
TLV271, TLV272, NCV272, TLV274, NCV274
TYPICAL CHARACTERISTICS
VS = +6 V
Av = +1
RL = 2 kW
25 mV/div
25 mV/div
VS = +6 V
Av = −1
RL = 2 kW
500 ns/div
500 ns/div
Figure 30. 6 V Inverting Small Signal Pulse
Response
Figure 31. 6 V Non−Inverting Small Signal
Pulse Response
120
60
40
100
OUTPUT VOLTAGE RELATIVE TO
VSS (V)
1k
10k
100k
200
−200
−25
1M
0
25
50
75
100
125
TEMPERATURE (°C)
Figure 32. CMRR vs. Frequency for
TLV/NCV272/274
Figure 33. Input Bias and Offset Current vs.
Temperature for TLV/NCV272/274
T = −40°C
T = 25°C
T = 85°C
T = 125°C
0.8
0.6
0.4
0.2
VS = 36 V
0
400
FREQUENCY (Hz)
1
0
600
0
RL = 10 kW
TA = 25°C
0
10
IIB+
IIB−
IOS
800
CURRENT (pA)
80
20
VS = 36 V
1000
2
4
6
8
10
12
14
16
18
20
OUTPUT VOLTAGE RELATIVE TO VDD (V)
)
100
(
1200
VS = 2.7 V
VS = 5 V
VS = 10 V
VS = 36 V
1.4
T = −40°C
T = 25°C
T = 85°C
T = 125°C
1.2
1
0.8
0.6
0.4
0.2
0
VS = 36 V
0
2
4
6
8
10
12
14
16
18
OUTPUT CURRENT (mA)
OUTPUT CURRENT (mA)
Figure 34. Low Level Output vs. Output
Current for TLV/NCV272/274
Figure 35. High Level Output vs. Output
Current for TLV/NCV272/274
www.onsemi.com
16
20
TLV271, TLV272, NCV272, TLV274, NCV274
TYPICAL CHARACTERISTICS
18.1
Input
Output
18
Input
Output
18.05
VOLTAGE (V)
18.05
VOLTAGE (V)
18.075
VS = 36 V
AV = +1
RL = 10 kW
18.025
18
VS = 36 V
AV = +1
RL = 10 kW
17.975
17.95
17.95
17.9
−20
0
20
40
17.925
−20
60
0
TIME (ms)
20
Figure 37. Inverting Small Signal Transient
Response for TLV/NCV272/274
24
25
22
VS = 36 V
AV = −1
RL = 10 kW
20
20
VOLTAGE (V)
VOLTAGE (V)
60
TIME (ms)
Figure 36. Non−inverting Small Signal
Transient Response for TLV/NCV272/274
15
10
−20
40
VS = 36 V
AV = +1
RL = 10 kW
Input
Output
0
20
18
16
14
12
40
10
−20
60
TIME (ms)
Input
Output
0
20
40
TIME (ms)
Figure 38. Non−inverting Large Signal
Transient Response for TLV/NCV272/274
Figure 39. Inverting Large Signal Transient
Response for TLV/NCV272/274
www.onsemi.com
17
60
TLV271, TLV272, NCV272, TLV274, NCV274
APPLICATIONS
50 k
R1
5.0 k
VDD
VDD
R2
10 k
MC1403
2.5 V
VO
TLV271
VO
TLV271
VDD
−
Vref
−
+
+
1
V ref + V DD
2
R1
V O + 2.5 V(1 )
)
R2
R
R
Figure 40. Voltage Reference
fO +
C
C
1
2pRC
For: fo = 1.0 kHz
R = 16 kW
C = 0.01 mF
Figure 41. Wien Bridge Oscillator
VDD
C
R1
Vin
R2
C
R3
−
Hysteresis
Vin
R1
+
R2
VOH
Vref
TLV271
−
VO
VOL
VO
CO = 10 C
Vref
VO
+
CO
TLV271
VinL
Given: fo = center frequency
A(fo) = gain at center frequency
VinH
Choose value fo, C
Q
Then : R3 +
pf O C
Vref
R1
(V OL * V ref) ) V ref
R1 ) R2
R1
V inH +
(V OH * V ref) ) V ref
R1 ) R2
R1
H+
(V OH * V OL)
R1 ) R2
V inL +
R1 +
R2 +
R3
2 A(f O)
R1 R3
4Q 2 R1 * R3
Figure 42. Comparator with Hysteresis
For less than 10% error from operational amplifier,
((QO fO)/BW) < 0.1 where fo and BW are expressed in Hz.
If source impedance varies, filter may be preceded with
voltage follower buffer to stabilize filter parameters.
Figure 43. Multiple Feedback Bandpass Filter
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18
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
TSOP−5
CASE 483
ISSUE N
5
1
SCALE 2:1
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH
THICKNESS. MINIMUM LEAD THICKNESS IS THE
MINIMUM THICKNESS OF BASE MATERIAL.
4. DIMENSIONS A AND B DO NOT INCLUDE MOLD
FLASH, PROTRUSIONS, OR GATE BURRS. MOLD
FLASH, PROTRUSIONS, OR GATE BURRS SHALL NOT
EXCEED 0.15 PER SIDE. DIMENSION A.
5. OPTIONAL CONSTRUCTION: AN ADDITIONAL
TRIMMED LEAD IS ALLOWED IN THIS LOCATION.
TRIMMED LEAD NOT TO EXTEND MORE THAN 0.2
FROM BODY.
D 5X
NOTE 5
2X
DATE 12 AUG 2020
0.20 C A B
0.10 T
M
2X
0.20 T
5
B
1
4
2
B
S
3
K
DETAIL Z
G
A
A
TOP VIEW
DIM
A
B
C
D
G
H
J
K
M
S
DETAIL Z
J
C
0.05
H
C
SIDE VIEW
SEATING
PLANE
END VIEW
GENERIC
MARKING DIAGRAM*
SOLDERING FOOTPRINT*
0.95
0.037
MILLIMETERS
MIN
MAX
2.85
3.15
1.35
1.65
0.90
1.10
0.25
0.50
0.95 BSC
0.01
0.10
0.10
0.26
0.20
0.60
0_
10 _
2.50
3.00
1.9
0.074
5
5
XXXAYWG
G
1
1
Analog
2.4
0.094
XXX = Specific Device Code
A
= Assembly Location
Y
= Year
W = Work Week
G
= Pb−Free Package
1.0
0.039
XXX MG
G
Discrete/Logic
XXX = Specific Device Code
M = Date Code
G
= Pb−Free Package
(Note: Microdot may be in either location)
0.7
0.028
SCALE 10:1
mm Ǔ
ǒinches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
DOCUMENT NUMBER:
DESCRIPTION:
98ARB18753C
TSOP−5
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2018
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOIC−8 NB
CASE 751−07
ISSUE AK
8
1
SCALE 1:1
−X−
DATE 16 FEB 2011
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
A
8
5
S
B
0.25 (0.010)
M
Y
M
1
4
−Y−
K
G
C
N
X 45 _
SEATING
PLANE
−Z−
0.10 (0.004)
H
M
D
0.25 (0.010)
M
Z Y
S
X
J
S
8
8
1
1
IC
4.0
0.155
XXXXX
A
L
Y
W
G
IC
(Pb−Free)
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
XXXXXX
AYWW
1
1
Discrete
XXXXXX
AYWW
G
Discrete
(Pb−Free)
XXXXXX = Specific Device Code
A
= Assembly Location
Y
= Year
WW
= Work Week
G
= Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
1.270
0.050
SCALE 6:1
INCHES
MIN
MAX
0.189
0.197
0.150
0.157
0.053
0.069
0.013
0.020
0.050 BSC
0.004
0.010
0.007
0.010
0.016
0.050
0 _
8 _
0.010
0.020
0.228
0.244
8
8
XXXXX
ALYWX
G
XXXXX
ALYWX
1.52
0.060
0.6
0.024
MILLIMETERS
MIN
MAX
4.80
5.00
3.80
4.00
1.35
1.75
0.33
0.51
1.27 BSC
0.10
0.25
0.19
0.25
0.40
1.27
0_
8_
0.25
0.50
5.80
6.20
GENERIC
MARKING DIAGRAM*
SOLDERING FOOTPRINT*
7.0
0.275
DIM
A
B
C
D
G
H
J
K
M
N
S
mm Ǔ
ǒinches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
STYLES ON PAGE 2
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42564B
SOIC−8 NB
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 2
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
SOIC−8 NB
CASE 751−07
ISSUE AK
DATE 16 FEB 2011
STYLE 1:
PIN 1. EMITTER
2. COLLECTOR
3. COLLECTOR
4. EMITTER
5. EMITTER
6. BASE
7. BASE
8. EMITTER
STYLE 2:
PIN 1. COLLECTOR, DIE, #1
2. COLLECTOR, #1
3. COLLECTOR, #2
4. COLLECTOR, #2
5. BASE, #2
6. EMITTER, #2
7. BASE, #1
8. EMITTER, #1
STYLE 3:
PIN 1. DRAIN, DIE #1
2. DRAIN, #1
3. DRAIN, #2
4. DRAIN, #2
5. GATE, #2
6. SOURCE, #2
7. GATE, #1
8. SOURCE, #1
STYLE 4:
PIN 1. ANODE
2. ANODE
3. ANODE
4. ANODE
5. ANODE
6. ANODE
7. ANODE
8. COMMON CATHODE
STYLE 5:
PIN 1. DRAIN
2. DRAIN
3. DRAIN
4. DRAIN
5. GATE
6. GATE
7. SOURCE
8. SOURCE
STYLE 6:
PIN 1. SOURCE
2. DRAIN
3. DRAIN
4. SOURCE
5. SOURCE
6. GATE
7. GATE
8. SOURCE
STYLE 7:
PIN 1. INPUT
2. EXTERNAL BYPASS
3. THIRD STAGE SOURCE
4. GROUND
5. DRAIN
6. GATE 3
7. SECOND STAGE Vd
8. FIRST STAGE Vd
STYLE 8:
PIN 1. COLLECTOR, DIE #1
2. BASE, #1
3. BASE, #2
4. COLLECTOR, #2
5. COLLECTOR, #2
6. EMITTER, #2
7. EMITTER, #1
8. COLLECTOR, #1
STYLE 9:
PIN 1. EMITTER, COMMON
2. COLLECTOR, DIE #1
3. COLLECTOR, DIE #2
4. EMITTER, COMMON
5. EMITTER, COMMON
6. BASE, DIE #2
7. BASE, DIE #1
8. EMITTER, COMMON
STYLE 10:
PIN 1. GROUND
2. BIAS 1
3. OUTPUT
4. GROUND
5. GROUND
6. BIAS 2
7. INPUT
8. GROUND
STYLE 11:
PIN 1. SOURCE 1
2. GATE 1
3. SOURCE 2
4. GATE 2
5. DRAIN 2
6. DRAIN 2
7. DRAIN 1
8. DRAIN 1
STYLE 12:
PIN 1. SOURCE
2. SOURCE
3. SOURCE
4. GATE
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 13:
PIN 1. N.C.
2. SOURCE
3. SOURCE
4. GATE
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 14:
PIN 1. N−SOURCE
2. N−GATE
3. P−SOURCE
4. P−GATE
5. P−DRAIN
6. P−DRAIN
7. N−DRAIN
8. N−DRAIN
STYLE 15:
PIN 1. ANODE 1
2. ANODE 1
3. ANODE 1
4. ANODE 1
5. CATHODE, COMMON
6. CATHODE, COMMON
7. CATHODE, COMMON
8. CATHODE, COMMON
STYLE 16:
PIN 1. EMITTER, DIE #1
2. BASE, DIE #1
3. EMITTER, DIE #2
4. BASE, DIE #2
5. COLLECTOR, DIE #2
6. COLLECTOR, DIE #2
7. COLLECTOR, DIE #1
8. COLLECTOR, DIE #1
STYLE 17:
PIN 1. VCC
2. V2OUT
3. V1OUT
4. TXE
5. RXE
6. VEE
7. GND
8. ACC
STYLE 18:
PIN 1. ANODE
2. ANODE
3. SOURCE
4. GATE
5. DRAIN
6. DRAIN
7. CATHODE
8. CATHODE
STYLE 19:
PIN 1. SOURCE 1
2. GATE 1
3. SOURCE 2
4. GATE 2
5. DRAIN 2
6. MIRROR 2
7. DRAIN 1
8. MIRROR 1
STYLE 20:
PIN 1. SOURCE (N)
2. GATE (N)
3. SOURCE (P)
4. GATE (P)
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 21:
PIN 1. CATHODE 1
2. CATHODE 2
3. CATHODE 3
4. CATHODE 4
5. CATHODE 5
6. COMMON ANODE
7. COMMON ANODE
8. CATHODE 6
STYLE 22:
PIN 1. I/O LINE 1
2. COMMON CATHODE/VCC
3. COMMON CATHODE/VCC
4. I/O LINE 3
5. COMMON ANODE/GND
6. I/O LINE 4
7. I/O LINE 5
8. COMMON ANODE/GND
STYLE 23:
PIN 1. LINE 1 IN
2. COMMON ANODE/GND
3. COMMON ANODE/GND
4. LINE 2 IN
5. LINE 2 OUT
6. COMMON ANODE/GND
7. COMMON ANODE/GND
8. LINE 1 OUT
STYLE 24:
PIN 1. BASE
2. EMITTER
3. COLLECTOR/ANODE
4. COLLECTOR/ANODE
5. CATHODE
6. CATHODE
7. COLLECTOR/ANODE
8. COLLECTOR/ANODE
STYLE 25:
PIN 1. VIN
2. N/C
3. REXT
4. GND
5. IOUT
6. IOUT
7. IOUT
8. IOUT
STYLE 26:
PIN 1. GND
2. dv/dt
3. ENABLE
4. ILIMIT
5. SOURCE
6. SOURCE
7. SOURCE
8. VCC
STYLE 29:
PIN 1. BASE, DIE #1
2. EMITTER, #1
3. BASE, #2
4. EMITTER, #2
5. COLLECTOR, #2
6. COLLECTOR, #2
7. COLLECTOR, #1
8. COLLECTOR, #1
STYLE 30:
PIN 1. DRAIN 1
2. DRAIN 1
3. GATE 2
4. SOURCE 2
5. SOURCE 1/DRAIN 2
6. SOURCE 1/DRAIN 2
7. SOURCE 1/DRAIN 2
8. GATE 1
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42564B
SOIC−8 NB
STYLE 27:
PIN 1. ILIMIT
2. OVLO
3. UVLO
4. INPUT+
5. SOURCE
6. SOURCE
7. SOURCE
8. DRAIN
STYLE 28:
PIN 1. SW_TO_GND
2. DASIC_OFF
3. DASIC_SW_DET
4. GND
5. V_MON
6. VBULK
7. VBULK
8. VIN
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 2 OF 2
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOIC−14 NB
CASE 751A−03
ISSUE L
14
1
SCALE 1:1
D
DATE 03 FEB 2016
A
B
14
8
A3
E
H
L
1
0.25
B
M
DETAIL A
7
13X
M
b
0.25
M
C A
S
B
S
0.10
X 45 _
M
A1
e
DETAIL A
h
A
C
SEATING
PLANE
DIM
A
A1
A3
b
D
E
e
H
h
L
M
MILLIMETERS
MIN
MAX
1.35
1.75
0.10
0.25
0.19
0.25
0.35
0.49
8.55
8.75
3.80
4.00
1.27 BSC
5.80
6.20
0.25
0.50
0.40
1.25
0_
7_
INCHES
MIN
MAX
0.054 0.068
0.004 0.010
0.008 0.010
0.014 0.019
0.337 0.344
0.150 0.157
0.050 BSC
0.228 0.244
0.010 0.019
0.016 0.049
0_
7_
GENERIC
MARKING DIAGRAM*
SOLDERING FOOTPRINT*
6.50
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSION
SHALL BE 0.13 TOTAL IN EXCESS OF AT
MAXIMUM MATERIAL CONDITION.
4. DIMENSIONS D AND E DO NOT INCLUDE
MOLD PROTRUSIONS.
5. MAXIMUM MOLD PROTRUSION 0.15 PER
SIDE.
14
14X
1.18
XXXXXXXXXG
AWLYWW
1
1
1.27
PITCH
14X
XXXXX
A
WL
Y
WW
G
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
0.58
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
STYLES ON PAGE 2
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42565B
SOIC−14 NB
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 2
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
SOIC−14
CASE 751A−03
ISSUE L
DATE 03 FEB 2016
STYLE 1:
PIN 1. COMMON CATHODE
2. ANODE/CATHODE
3. ANODE/CATHODE
4. NO CONNECTION
5. ANODE/CATHODE
6. NO CONNECTION
7. ANODE/CATHODE
8. ANODE/CATHODE
9. ANODE/CATHODE
10. NO CONNECTION
11. ANODE/CATHODE
12. ANODE/CATHODE
13. NO CONNECTION
14. COMMON ANODE
STYLE 2:
CANCELLED
STYLE 3:
PIN 1. NO CONNECTION
2. ANODE
3. ANODE
4. NO CONNECTION
5. ANODE
6. NO CONNECTION
7. ANODE
8. ANODE
9. ANODE
10. NO CONNECTION
11. ANODE
12. ANODE
13. NO CONNECTION
14. COMMON CATHODE
STYLE 4:
PIN 1. NO CONNECTION
2. CATHODE
3. CATHODE
4. NO CONNECTION
5. CATHODE
6. NO CONNECTION
7. CATHODE
8. CATHODE
9. CATHODE
10. NO CONNECTION
11. CATHODE
12. CATHODE
13. NO CONNECTION
14. COMMON ANODE
STYLE 5:
PIN 1. COMMON CATHODE
2. ANODE/CATHODE
3. ANODE/CATHODE
4. ANODE/CATHODE
5. ANODE/CATHODE
6. NO CONNECTION
7. COMMON ANODE
8. COMMON CATHODE
9. ANODE/CATHODE
10. ANODE/CATHODE
11. ANODE/CATHODE
12. ANODE/CATHODE
13. NO CONNECTION
14. COMMON ANODE
STYLE 6:
PIN 1. CATHODE
2. CATHODE
3. CATHODE
4. CATHODE
5. CATHODE
6. CATHODE
7. CATHODE
8. ANODE
9. ANODE
10. ANODE
11. ANODE
12. ANODE
13. ANODE
14. ANODE
STYLE 7:
PIN 1. ANODE/CATHODE
2. COMMON ANODE
3. COMMON CATHODE
4. ANODE/CATHODE
5. ANODE/CATHODE
6. ANODE/CATHODE
7. ANODE/CATHODE
8. ANODE/CATHODE
9. ANODE/CATHODE
10. ANODE/CATHODE
11. COMMON CATHODE
12. COMMON ANODE
13. ANODE/CATHODE
14. ANODE/CATHODE
STYLE 8:
PIN 1. COMMON CATHODE
2. ANODE/CATHODE
3. ANODE/CATHODE
4. NO CONNECTION
5. ANODE/CATHODE
6. ANODE/CATHODE
7. COMMON ANODE
8. COMMON ANODE
9. ANODE/CATHODE
10. ANODE/CATHODE
11. NO CONNECTION
12. ANODE/CATHODE
13. ANODE/CATHODE
14. COMMON CATHODE
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42565B
SOIC−14 NB
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 2 OF 2
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
Micro8
CASE 846A−02
ISSUE K
DATE 16 JUL 2020
SCALE 2:1
GENERIC
MARKING DIAGRAM*
8
XXXX
AYWG
G
1
XXXX
A
Y
W
G
= Specific Device Code
= Assembly Location
= Year
= Work Week
= Pb−Free Package
(Note: Microdot may be in either location)
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
DOCUMENT NUMBER:
DESCRIPTION:
98ASB14087C
MICRO8
STYLE 1:
PIN 1.
2.
3.
4.
5.
6.
7.
8.
SOURCE
SOURCE
SOURCE
GATE
DRAIN
DRAIN
DRAIN
DRAIN
STYLE 2:
PIN 1.
2.
3.
4.
5.
6.
7.
8.
SOURCE 1
GATE 1
SOURCE 2
GATE 2
DRAIN 2
DRAIN 2
DRAIN 1
DRAIN 1
STYLE 3:
PIN 1.
2.
3.
4.
5.
6.
7.
8.
N-SOURCE
N-GATE
P-SOURCE
P-GATE
P-DRAIN
P-DRAIN
N-DRAIN
N-DRAIN
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
TSSOP−14 WB
CASE 948G
ISSUE C
14
DATE 17 FEB 2016
1
SCALE 2:1
14X K REF
0.10 (0.004)
0.15 (0.006) T U
M
T U
V
S
S
S
N
2X
14
L/2
0.25 (0.010)
8
M
B
−U−
L
PIN 1
IDENT.
N
F
7
1
0.15 (0.006) T U
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL
NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL
IN EXCESS OF THE K DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
S
DETAIL E
K
A
−V−
K1
J J1
ÉÉÉ
ÇÇÇ
ÇÇÇ
ÉÉÉ
SECTION N−N
−W−
C
0.10 (0.004)
−T− SEATING
PLANE
H
G
D
DETAIL E
DIM
A
B
C
D
F
G
H
J
J1
K
K1
L
M
MILLIMETERS
INCHES
MIN
MAX
MIN MAX
4.90
5.10 0.193 0.200
4.30
4.50 0.169 0.177
−−−
1.20
−−− 0.047
0.05
0.15 0.002 0.006
0.50
0.75 0.020 0.030
0.65 BSC
0.026 BSC
0.50
0.60 0.020 0.024
0.09
0.20 0.004 0.008
0.09
0.16 0.004 0.006
0.19
0.30 0.007 0.012
0.19
0.25 0.007 0.010
6.40 BSC
0.252 BSC
0_
8_
0_
8_
GENERIC
MARKING DIAGRAM*
14
SOLDERING FOOTPRINT
XXXX
XXXX
ALYWG
G
7.06
1
1
0.65
PITCH
14X
0.36
14X
1.26
DIMENSIONS: MILLIMETERS
DOCUMENT NUMBER:
98ASH70246A
DESCRIPTION:
TSSOP−14 WB
A
L
Y
W
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
(Note: Microdot may be in either location)
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
onsemi,
, and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates
and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property.
A listing of onsemi’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. onsemi reserves the right to make changes at any time to any
products or information herein, without notice. The information herein is provided “as−is” and onsemi makes no warranty, representation or guarantee regarding the accuracy of the
information, product features, availability, functionality, or suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use
of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products
and applications using onsemi products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information
provided by onsemi. “Typical” parameters which may be provided in onsemi data sheets and/or specifications can and do vary in different applications and actual performance may
vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. onsemi does not convey any license
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Buyer purchase or use onsemi products for any such unintended or unauthorized application, Buyer shall indemnify and hold onsemi and its officers, employees, subsidiaries, affiliates,
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