ENW-C9B01A1EF

  PAN4620 IEEE® 802.15.4 and Bluetooth® Low Energy Module Product Specification Rev. 0.1 Wireless Modules  PAN4620 802.15.4 and BLE Module Overview The PAN4620 is Panasonic’s Internet of Things ® dual mode module comprising NXP ’s Kinetis MKW41Z512CAT4 SoC - a 2.4 GHz 802.15.4 and ® Bluetooth Low Energy wireless radio ® microcontroller based on an ARM Cortex-M0+ core. Characteristics • Transceiver frequency range 2360 MHz to 2483.5 MHz • • • Programmable transmitter output power: -30 dBm to 3 dBm Receiver sensitivity (BLE): -93 dBm ® Receiver sensitivity typical for IEEE Standard 802.15.4: -98 dBm Features • UART, SPI, I²C, TSI, ADC & DAC • Same form factor and compatible pinout for • Typical receiver current consumption (3.6 V supply): 8.5 mA • Transmitter current consumption (3.6 V supply, 0 dBm): 7.6 mA • Bluetooth® • Bluetooth® LE 4.2 compliant implementation VCC, GND, Reset, UART, I²C, and SWD as PAN1026, PAN1760, PAN1760A, and PAN1761 • Single and concurrent operation of IEEE 802.15.4 and BLE ® Open to various known application layers or proprietary solutions • Surface Mount Type dimensions: 15.6 mm x 8.7 mm x 1.9 mm • • On module 32 MHz and 32 kHz crystal • • • • Core: Up to 48 MHz 32 bit ARM Cortex-M0+ ® certified by BT SIG • • Supporting software consisting of BLE host stack and profiles and IPv6 6LoBLE ® Bluetooth Developer Studio Plug-In ® SoC: NXP Kinetis KW41Z – 2.4 GHz 802.15.4 and BLE 4.2 Wireless Radio Microcontroller ® Memory: 512 kB of flash and 128 kB of SRAM Voltage range: 1.8 V to 4.2 V Temperature range: -40 °C to 85 °C IEEE® 802.15.4 • IEEE® standard 802.15.4 compliant • Supporting software consisting of 802.15.4 MAC/PHY implementation, Simple Media Access ® ® Controller (SMAC), and NXP ’s certified Thread stack Block Diagram Product Specification Rev. 0.1 Page 2  PAN4620 802.15.4 and BLE Module By purchase of any of the products described in this document the customer accepts the document's validity and declares their agreement and understanding of its contents and recommendations. Panasonic Industrial Devices Europe GmbH (Panasonic) reserves the right to make changes as required at any time without notification. Please consult the most recently issued Product Specification before initiating or completing a design. © Panasonic Industrial Devices Europe GmbH 2017. This specification sheet is copyrighted. Reproduction of this document is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Do not disclose it to a third party. All rights reserved. This Product Specification does not lodge the claim to be complete and free of mistakes. Engineering Samples (ES) If Engineering Samples are delivered to the customer, these samples have the status “Engineering Samples”. This means that the design of this product is not yet concluded. Engineering Samples may be partially or fully functional, and they may differ from the published Product Specification. Engineering Samples are not qualified and they are not to be used for reliability testing or series production. Disclaimer The customer acknowledges that samples may deviate from the Product Specification and may bear defects due to their status of development and the lack of qualification mentioned above. Panasonic rejects any liability or product warranty for Engineering Samples. In particular, Panasonic disclaims liability for damages caused by:  The use of the Engineering Sample other than for evaluation purposes, particularly the installation or integration in another product to be sold by the customer,  Deviation or lapse in function of the Engineering Sample,  Improper use of the Engineering Sample. Panasonic Industrial Devices Europe GmbH disclaims any liability for consequential and incidental damages. In case of any queries regarding the Engineering Samples, please contact your local sales partner or the related product manager. Product Specification Rev. 0.1 Page 3  PAN4620 802.15.4 and BLE Module Table of Contents 1 2 3 4 5 6 7 About This Document......................................................................................................................... 6 1.1 Purpose and Audience .............................................................................................................. 6 1.2 Revision History ......................................................................................................................... 6 1.3 Use of Symbols ......................................................................................................................... 6 1.4 Related Documents ................................................................................................................... 6 Overview .............................................................................................................................................. 7 2.1 Block Diagram ........................................................................................................................... 8 2.2 Pin Configuration ....................................................................................................................... 9 2.3 Transceiver Features ............................................................................................................... 13 Detailed Description ......................................................................................................................... 16 3.1 Dimensions .............................................................................................................................. 16 3.2 Footprint .................................................................................................................................. 17 3.3 Packaging ................................................................................................................................ 18 3.4 Case Marking .......................................................................................................................... 21 Specification ..................................................................................................................................... 22 4.1 Default Test Conditions ........................................................................................................... 22 4.2 Absolute Maximum Ratings ..................................................................................................... 22 4.3 Recommended Operating Conditions ...................................................................................... 23 4.4 Current Consumption............................................................................................................... 24 4.5 Internal Operating Frequencies ............................................................................................... 24 4.6 Interface Specification ............................................................................................................. 25 4.7 Flash electrical specifications .................................................................................................. 40 4.8 General switching specification ............................................................................................... 41 4.9 Transceiver Feature Summary ................................................................................................ 42 4.10 Reliability Tests ....................................................................................................................... 47 4.11 Recommended Soldering Profile ............................................................................................. 48 Cautions ............................................................................................................................................ 49 5.1 Design Notes ........................................................................................................................... 49 5.2 Installation Notes ..................................................................................................................... 49 5.3 Usage Condition Notes ............................................................................................................ 50 5.4 Storage Notes .......................................................................................................................... 50 5.5 Safety Cautions ....................................................................................................................... 50 5.6 Other Cautions ........................................................................................................................ 51 5.7 Life Support Policy ................................................................................................................... 51 Regulatory and Certification Information ....................................................................................... 52 6.1 Federal Communications Commission (FCC) for US .............................................................. 52 6.2 Innovation, Science, and Economic Development (ISED) for Canada .................................... 52 6.3 European Conformity According to RED (2014/53/EU) ........................................................... 52 6.4 Bluetooth ................................................................................................................................ 52 6.5 RoHS and REACH Declaration ............................................................................................... 52 ® Appendix ........................................................................................................................................... 53 7.1 Ordering Information ................................................................................................................ 53 Product Specification Rev. 0.1 Page 4  PAN4620 802.15.4 and BLE Module 7.2 List of Acronyms ...................................................................................................................... 54 7.3 Contact Details ........................................................................................................................ 55 Product Specification Rev. 0.1 Page 5  PAN4620 802.15.4 and BLE Module 1 About This Document 1 About This Document 1.1 Purpose and Audience This Product Specification provides details on the functional, operational, and electrical characteristics of the Panasonic PAN4620 module. It is intended for hardware design, application, and Original Equipment Manufacturers (OEM) engineers. The product is referred to as “the PAN4620” or “the module” within this document. 1.2 1.3 Revision History Revision Date Modifications/Remarks 0.1 28.02.2018 1st preliminary version. Use of Symbols Symbol Description Note Indicates important information for the proper use of the product. Non-observance can lead to errors. Attention Indicates important notes that, if not observed, can put the product’s functionality at risk.  [chapter number] [chapter title] Cross reference Indicates cross references within the document. Example: Description of the symbols used in this document  1.3 Use of Symbol. 1.4 Related Documents Please refer to the Panasonic website for related documents  7.3.2 Product Information. Product Specification Rev. 0.1 Page 6  PAN4620 802.15.4 and BLE Module 2 Overview 2 Overview The PAN4620 is Panasonic’s Internet of Things dual mode module comprising NXP’s Kinetis KW41Z SoC - a 2.4 GHz 802.15.4 and Bluetooth® Low Energy wireless radio microcontroller ® based on an ARM Cortex-M0+ core. To provide maximum flexibility, the module can be operated in stand-alone and hosted mode. With 512 kB flash memory and 128 kB SRAM the PAN4620 can easily be used as a stand-alone controller eliminating the need for an external processor, saving complexity, space and cost. It is thus well suited for very small and low-power applications. However, also the integration of 802.15.4 and/or BLE connectivity into existing applications can easily be achieved when using the PAN4620 in hosted mode. ® Using the PAN4620 with low power consumption in combination with NXP ’s certified Thread stack, BLE stack or a combination of both for concurrent operation allows to meet IoT ® application requirements without the need for a gateway. Since Thread does not define an application layer, various application layers can be used, such as dotdot, IoTivity, OpenDOF, and others. ® FCC, IC, and CE approval are under way. Please refer to the Panasonic website for related documents  7.3.2 Product Information. Further information on the variants and versions  7.1 Ordering Information. For further information please also refer to the MKW41Z512CAT4 datasheet and reference ® manual from NXP . Product Specification Rev. 0.1 Page 7  PAN4620 802.15.4 and BLE Module 2 Overview 2.1 Block Diagram Product Specification Rev. 0.1 Page 8  PAN4620 802.15.4 and BLE Module 2 Overview 2.2 Pin Configuration Pin Assignment Top view with all values in [mm] Pin Functions No Pin Name Alternative Pin Pin Type Description A1 GND Ground Connect to ground A2 NC A3 RESET A4 NC A5 VCC Power Supply voltage 1.8 V to 4.2 V A6 VCC Power Supply voltage 1.8 V to 4.2 V A7 GND Ground Connect to ground A8 PTC18 Digital I/O Can be configured to use the mentioned alternative pin functions. Not connected PTA2, TPM0_CH3 Digital I/O Can be configured to use the mentioned alternative pin functions. Not connected TSI0_CH6, LLWU_P2, SPI0_SIN, I2C1_SDA, LPUART0_TX, BSM_DATA, DTM_TX Product Specification Rev. 0.1 Page 9  PAN4620 802.15.4 and BLE Module 2 Overview No Pin Name A9 Alternative Pin Pin Type Description GND Ground Connect to ground A11 GND Ground Connect to ground A12 GND Ground Connect to ground B1 NC B2 PTA17 Not connected TSI0_CH11, LLWU_P5, Digital I/O Can be configured to use the mentioned alternative pin functions. Digital I/O Can be configured to use the mentioned alternative pin functions. Digital I/O Can be configured to use the mentioned alternative pin functions. RF_RESET, SPI1_SIN, TPM_CLKIN1 B3 PTC19 TSI0_CH7, LLWU_P3, SPI0_PCS0, I2C0_SCL, LPUART0_CTS_b, BSM_CLK, BLE_RF_ACTIVE B4 PTC17 TSI0_CH5, LLWU_P1 SPI0_SOUT, I2C1_SCL LPUART0_RX, BSM_FRAME, DTM_RX B5 PTC16 TSI0_CH4, LLWU_P0, SPI0_SCK, I2C0_SDA, LPUART0_RTS_b, TPM0_CH3 Digital I/O Can be configured to use the mentioned alternative pin functions. B6 PTA16 TSI0_CH10, LLWU_P4, Digital I/O Can be configured to use the mentioned alternative pin functions. SPI1_SOUT, TPM0_CH0 B7 NC Not connected B8 NC Not connected B9 NC Not connected C1 NC Not connected C2 PTA19 TSI0_CH13, ADC0_SE5, Digital I/O Can be configured to use the mentioned alternative pin functions. LLWU_P7, SPI1_PCS0, TPM2_CH1 C3 PTA18 TSI0_CH12, LLWU_P6, SPI1_SCK, TPM2_CH0 Digital I/O Can be configured to use the mentioned alternative pin functions. C4 SWDIO PTA0, TSI0_CH8, SPI0_PCS1, TPM1_CH0, SWD_DIO Digital I/O Can be configured to use the mentioned alternative pin functions. C5 SWDCLK PTA1, TSI0_CH9, SPI1_PCS0, TPM1_CH1, SWD_CLK Digital I/O Can be configured to use the mentioned alternative pin functions. Product Specification Rev. 0.1 Page 10  PAN4620 802.15.4 and BLE Module 2 Overview No Pin Name Alternative Pin Pin Type Description C6 PTC1 I2C0_SDA, Digital I/O Can be configured to use the mentioned alternative pin functions. LPUART0_RTS_b, TPM0_CH2, BLE_RF_ACTIVE C7 NC Not connected C8 GND Ground Connect to ground C9 GND Ground Connect to ground D1 PTB0 Digital I/O Can be configured to use the mentioned alternative pin functions. Digital I/O Can be configured to use the mentioned alternative pin functions. Digital I/O Can be configured to use the mentioned alternative pin functions. Digital I/O Can be configured to use the mentioned alternative pin functions. LLWU_P8, XTAL_OUT_EN, I2C0_SCL, CMP0_OUT, TPM0_CH1, CLKOUT D2 PTB1 ADC0_SE1, CMP0_IN5, DTM_RX, I2C0_SDA, LPTMR0_ALT1, TPM0_CH2, CMT_IRO D3 PTB2 ADC0_SE3, CMP0_IN3, RF_NOT_ALLOWED, DTM_TX, TPM1_CH0 D4 PTB3 ADC0_SE2, CMP0_IN4, CLKOUT, TPM1_CH1, RTC_CLKOUT D5 NC Not connected D6 NC Not connected D7 GND Ground Connect to ground D8 GND Ground Connect to ground D9 ANT E1 PTC3 TSI0_CH15, LLWU_P11, Digital I/O RX_SWITCH, I2C1_SDA, Can be configured to use the mentioned alternative pin functions. LPUART0_TX, TPM0_CH1, DTM_TX E2 PTC2 TSI0_CH14, LLWU_P10, TX_SWITCH, I2C1_SCL, LPUART0_RX, CMT_IRO, DTM_RX E3 NC Not connected E4 NC Not connected E5 PTC0 LLWU_P9, I2C0_SCL, LPUART0_CTS_b, TPM0_CH1 Product Specification Rev. 0.1 Digital I/O Digital I/O Can be configured to use the mentioned alternative pin functions. Can be configured to use the mentioned alternative pin functions. Page 11  PAN4620 802.15.4 and BLE Module 2 Overview No Pin Name Alternative Pin Pin Type Description E6 PTC6 TSI0_CH2, LLWU_P14, XTAL_OUT_EN, I2C1_SCL, LPUART0_RX, TPM2_CH0, BSM_FRAME Digital I/O Can be configured to use the mentioned alternative pin functions. E7 NC E8 GND Ground Connect to ground E9 GND Ground Connect to ground F1 GND Ground Connect to ground F2 NC F3 ADC0_DP0, CMP0_IN0 Analog F4 ADC0_DM0, CMP0_IN1 Analog F5 PTC4 TSI0_CH0, LLWU_P12, LPUART0_CTS_b, TPM1_CH0, BSM_DATA Digital I/O Can be configured to use the mentioned alternative pin functions. F6 PTB18 DAC0_OUT, ADC0_SE4, CMP0_IN2, I2C1_SCL, TPM_CLKIN0, TPM0_CH0 Digital I/O Can be configured to use the mentioned alternative pin functions. F7 PTC7 TSI0_CH3, LLWU_P15, SPI0_PCS2, I2C1_SDA, LPUART0_TX, TPM2_CH1, BSM_DATA Digital I/O Can be configured to use the mentioned alternative pin functions. F8 PTC5 TSI0_CH1, LLWU_P13, RF_NOT_ALLOWED Digital I/O Can be configured to use the mentioned alternative pin functions. Not connected Not connected LPTMR0_ALT2, LPUART0_RTS_b, TPM1_CH1, BSM_CLK F9 GND Ground Connect to ground F11 GND Ground Connect to ground F12 GND Ground Connect to ground Product Specification Rev. 0.1 Page 12  PAN4620 802.15.4 and BLE Module 2 Overview 2.3 Transceiver Features The PAN4620 features an integrated chip antenna and corresponding matching networks. Both, a high accuracy 32 MHz crystal and a low frequency clock are integrated in the module. Therefore, no external crystal is required to make full use of the reduced power modes. The operating frequency is in the ISM band and the MBAN band from 2360 MHz to 2483.5 MHz with a programmable output power from -30 dBm to 3 dBm 2.3.1 Bluetooth® Features  Bluetooth LE v4.2 (1 Mbps)  Two simultaneous connections (2 independent hardware connection engines)  Receive sensitivity of –93 dBm ® For further information see  4.9 Transceiver Feature Summary. 2.3.2 IEEE® 802.15.4 Features  IEEE Standard 802.15.4-2011 compliant OQPSK modulation  Receive sensitivity of -98 dBm (Receive sensitivity in generic FSK modes depends on mode selection and data rate.)  Hardware acceleration for packet processing/link layer  NXP ’s certified Thread stack ® ® ® For further information see  4.9 Transceiver Feature Summary. 2.3.3 MCU Features ® The KW41Z features an ARM Cortex-M0+MCU with up to 48 MHz. As compared to Cortex-M0, the Cortex-M0+ uses an optimized 2-stage pipeline microarchitecture for reduced power consumption and improved architectural performance (cycles per instruction). 2.3.3.1 Interrupt Controller  Supports up to 32 interrupt request sources  32 vectored interrupts, 4 programmable priority levels  Includes a single non-maskable interrupt  Supports interrupt handling when system clocking is disabled in low power modes Product Specification Rev. 0.1 Page 13  PAN4620 802.15.4 and BLE Module 2 Overview 2.3.3.2 On chip memory 2.3.3.3 2.3.4 2.3.5  512 kB flash memory implemented as two equal 256 kB blocks.  One block can be read or erased, while code is being executed or read from the other.  Flash can be marked execute only in 8 kB blocks to prevent code being from being read by third parties.  128 kB SRAM  The chip features security circuitry to prevent unauthorized access to RAM and flash contents through the debugger. Debug Controller  Serial wire debug (SWD) interface  Hardware breakpoint unit for 2 code addresses  Hardware watchpoint unit for 2 data items  Micro trace buffer for program tracing Security Features  Advanced encryption standard accelerator (AES-128 Accelerator)  True random number generator (TRNG)  Flash memory protection Power Management Control Unit  Supports external voltage sources of 2.1 V to 4.2 V and is therefore ideally suited for single coin-cell battery operation.  Programmable power saving modes  Integrated low frequency clock to make full use of the reduced power modes  Available wake-up from power saving modes via internal and external sources  Integrated power-on reset (POR)  Integrated low voltage detect (LVD) with reset (brownout) capability  Selectable LVD trip points  Programmable low voltage warning (LVW) interrupt capability  Individual peripheral clocks can be gated off to reduce current consumption  Internal buffered bandgap reference voltage  Factory programmed trim for bandgap and LVD  1 kHz low power oscillator (LPO) Product Specification Rev. 0.1 Page 14  PAN4620 802.15.4 and BLE Module 2 Overview 2.3.6 Peripheral Features  16-bit analog-to-digital converter  12-Bit digital-to-analog converter  High-speed analog comparator (CMP)  Timer: low power timer (LPTMR), timer/PWM, programmable interrupt timer (PIT),  Real-time clock (RTC)  Inter-integrated circuit (I²C), two channels, up to 400 kHz, multi-master operation  Low power universal asynchronous receiver transmitter (LPUART), one channel fullduplex operation  Serial peripheral interface (SPI), master and slave mode, full-duplex, three-wire synchronous transfers  Carrier modulator timer (CMT) with four modes of operation  Touch sensor input with up to 16 external electrodes  24 General purpose Input/Outputs  GPIOs can be configured to function as a interrupt driven keyboard scanning matrix For further information see 4.6 Interface Specification. Product Specification Rev. 0.1 Page 15  PAN4620 802.15.4 and BLE Module 3 Detailed Description 3 Detailed Description 3.1 Dimensions All dimensions are in millimeters. No. Item Dimension Tolerance Remark 1 Width 8.70 ± 0.35 2 Length 15.60 ± 0.35 3 Height 1.80 Product Specification Rev. 0.1 ± 0.35 With case Page 16  PAN4620 802.15.4 and BLE Module 3 Detailed Description 3.2 Footprint The outer dimensions have a tolerance of 0.35 mm. Top view with all values in [mm] Product Specification Rev. 0.1 Page 17  PAN4620 802.15.4 and BLE Module 3 Detailed Description 3.3 Packaging The product is an engineering sample status product and will be delivered in the package described below. 3.3.1 Tape Dimensions 3.3.2 Packing in Tape Direction of unreeling (for customer) trailer (empty) 1 x circumference / hub (min 160mm) component packed area standard 1500pcs leader (empty) minimum 10 pitch Top cover tape more than 1 x circumference plus 100mm to avoid fixing of tape end on sealed modules. Empty spaces in the component packed area shall be less than two per reel and those spaces shall not be consecutive. 100730-PAN1720.vsd The top cover tape shall not be found on reel holes and it shall not stick out from the reel. Product Specification Rev. 0.1 Page 18  PAN4620 802.15.4 and BLE Module 3 Detailed Description 3.3.3 Component Direction 3.3.4 Reel Dimension Product Specification Rev. 0.1 Page 19  PAN4620 802.15.4 and BLE Module 3 Detailed Description 3.3.5 3.3.6 Package Label (1T) Lot code (1P) Customer order number, if applicable (2P) Order number (9D) Date code (Q) Quantity (HW/SW) Hardware/software version Total Package Product Specification Rev. 0.1 Page 20  PAN4620 802.15.4 and BLE Module 3 Detailed Description 3.4 Case Marking 1 PAN4620 2 Hardware/Software Version 3 ENW-No. / Model Name 4 FCC ID 5 IC ID 6 Lot code 7 Engineering Sample marking, if applicable 8 Marking for Pin 1 9 2D barcode, for internal usage only Product Specification Rev. 0.1 Page 21  PAN4620 802.15.4 and BLE Module 4 Specification 4 Specification All specifications are over temperature and process, unless indicated otherwise. 4.1 Default Test Conditions Temperature: Humidity: Supply Voltage: 4.2 25 ± 10 °C 40 to 85 % RH 3.6 V Absolute Maximum Ratings The maximum ratings may not be exceeded under any circumstances, not even momentarily or individually, as permanent damage to the module may result. Symbol Parameter TSTOR Storage Temperature VESD ESD robustness RF input power Condition Min. Typ. Max. Units -40 +85 °C Electrostatic discharge voltage, human body model -2000 +2000 V Electrostatic discharge voltage, charged-device model -500 +500 V Pmax 10 dBm VDD Supply voltage -0.3 4.2 V VIO Voltage on any IO pin -0.3 VDD+0.3 V Product Specification Rev. 0.1 Page 22  PAN4620 802.15.4 and BLE Module 4 Specification 4.3 Recommended Operating Conditions The maximum ratings may not be exceeded under any circumstances, not even momentarily or individually, as permanent damage to the module may result. Symbol VDD Parameter Condition Supply voltage DCDC converter needs 2.1 V min to start, the supply can drop to min. of 1.8 V after DCDC converter settles. Min. Typ. Start up 2.1 4.2 V 2.48 GHz 1 Input frequency TA Ambient temperature range -40 VIO Voltage on any IO pin ID Instantaneous max. current VIL Logic low input voltage Logic high input voltage Units Operating 1.8 fIN VIH Max. 2.36 Single pin limit (applies to all port pins) 25 85 °C -0.3 VDD+0.3 V -25 25 mA 0 0.3∙ V VDD INT 0.7∙VDD INT 2 VDD INT V 1 DC-DC converter requires slightly higher input voltage during startup. Bit DCDC_STS_DC_OK will be set when the DC-DC converter finished the startup sequence. Typical startup time is 50 ms and it varies with the loading of the converter. 2 VDD INT is the internal LDO regulated voltage supplying various circuit blocks, VDD INT=1.2 V. Product Specification Rev. 0.1 Page 23  PAN4620 802.15.4 and BLE Module 4 Specification 4.4 Current Consumption The current consumption depends on the user scenario and on the setup and timing in the power modes. Assume VDD = 3.6 V, Tamb = 25 °C, if nothing else is stated. 4.5 Parameter Condition Min. Typ. Max. Units Typical average RX current Measured under continuous RX with MCU stop / Flash doze 8.4 mA Typical average TX (0 dBm) current Measured under continuous TX with MCU stop / Flash doze 7.6 mA Typical average RX current Measured under continuous RX with MCU run / Flash enabled 10.2 mA Typical average TX (0 dBm) current Measured under continuous TX with MCU run / Flash enabled 9.6 mA Low Power Mode current Current consumption in very low leakage stop mode 182 nA Internal Operating Frequencies Symbol Parameter Condition Max. Unit fSYS System and core clock Normal run mode 48 MHz fBUS Bus clock Normal run mode 24 MHz fFLASH Flash clock Normal run mode 24 MHz fLPTMR LPTMR clock Normal run mode 24 MHz fSYS System and core clock VLPR and VLPS mode 3 4 MHz fBUS Bus clock VLPR and VLPS mode 3 1 MHz fFLASH Flash clock VLPR and VLPS mode 3 1 MHz fLPTMR LPTMR clock VLPR and VLPS mode 3 24 MHz fERCLK External reference clock VLPR and VLPS mode 3 16 MHz 4 3 The frequency limitations in VLPR and VLPS modes here override any frequency specification listed in the timing specification for any other module. These same frequency limits apply to VLPS, whether VLPS was entered from RUN or from VLPR. 4 The LPTMR can be clocked at this speed in VLPR or VLPS only when the source is an external pin. Product Specification Rev. 0.1 Page 24  PAN4620 802.15.4 and BLE Module 4 Specification Symbol 4.6 4.6.1 Parameter Condition Max. Unit 3 16 MHz VLPR and VLPS mode 3 8 MHz VLPR and VLPS mode 3 12 MHz fLPTMR-ERCLK LPTMR external reference clock VLPR and VLPS mode fTPM TPM asynchronous clock fLPUART0 LPUART0 asynchronous clock Interface Specification LPUART See also Section  4.8 General switching specification. Signal Name Description LPUART0_RX Receive Data I B4, E2, E6 LPUART0_TX Transmit Data I/O A8, E1, F7 LPUART0_CTS_b Clear To Send I B3, E5, F5 LPUART0_RTS_b Request To Send O B5, C6, F8 Description 4.6.2 I/O Range Pad Default. Baud rate Programmable baud rates (13-bit modulo divider) 115200 Data bits Programmable 8-bit or 9-bit data format 8 data bits Parity bits Hardware parity generation and checking No parity Stop bit 1-2 One stop bit Inter-Integrated Circuit (I2C) 2 Two I C channels. See also Section  4.8 General switching specification. Signal Name Module Description Pad 2 I/O B3, D1, E5 2 I/O B5, C6, D2 2 I/O B4, E2, E6 2 I/O A8, E1, F7 I2C0_SCL I2C0 I C serial clock line I2C0_SDA I2C0 I C serial data line I2C1_SCL I2C1 I C serial clock line I2C1_SDA I2C1 I C serial data line Product Specification Rev. 0.1 I/O Page 25  PAN4620 802.15.4 and BLE Module 4 Specification I2C timing (compare Figure 1): Symbol Description Standard Mode Fast Mode Min. Min. Max. Unit Max. fSCL SCL clock frequency 0 100 0 400 kHz tHD; STA Hold time (repeated) START condition. After this period, the first clock pulse is generated. 4 - 0.6 - µs tLOW LOW period of the SCL clock 4.7 - 1.3 - µs tHIGH HIGH period of the SCL clock 4 - 0.6 - µs tSU; STA Set-up time for a repeated START condition 4.7 - 0.6 - µs tHD; DAT Data hold time for I C bus devices 0 tSU; DAT Data set-up time 250 tr Rise time of SDA and SCL signals tf 2 5 3.45 8 6 7 6 0 0.9 µs - ns 10 300 ns 9 6,9 - 100 - 1000 20+0.1Cb Fall time of SDA and SCL signals - 300 20+0.1Cb 300 ns tSU; STO Set-up time for STOP condition 4 - 0.6 - µs tBUF Bus free time between STOP and START condition 4.7 - 1.3 - µs tSP Width of spikes that must be suppressed by the input filter N/A N/A 0 50 µs 5 The master mode I C deasserts ACK of an address byte simultaneously with the falling edge of SCL. If no slaves acknowledge this address byte, then a negative hold time can result, depending on the edge rates of the SDA and SCL lines. 2 6 The maximum tHD; DAT must be met only if the device does not stretch the LOW period (tLOW ) of the SCL signal. 7 Input signal Slew = 10 ns and Output Load = 50 pF. 8 Set-up time in slave-transmitter mode is 1 IPBus clock period, if the TX FIFO is empty. 9 A Fast mode I C bus device can be used in a Standard mode I C bus system, but the requirement tSU; DAT ≥ 250 ns must then be met. This is automatically the case, if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal then it must output the next data bit to the 2 SDA line trmax + tSU; DAT = 1000 + 250 = 1250 ns (according to the Standard mode I C bus specification), before the SCL line is released. 10 2 2 Cb = total capacitance of the one bus line in pF. Product Specification Rev. 0.1 Page 26  PAN4620 802.15.4 and BLE Module 4 Specification 2 Figure 1 - Timing definition for fast and standard mode devices on the I C bus. 4.6.3 DMA Serial Peripheral Interface (DSPI) Two independent SPI channels Master/Slave. Signal Name 4.6.3.1 Module Description I/O Pad SPI0_PCS0 SPI0 Chip Select/Slave Select I/O B3 SPI0_PCS1 SPI0 Chip Select O C4 SPI0_PCS2 SPI0 Chip Select O F7 SPI0_SCK SPI0 Serial Clock I/O B5 SPI0_SIN SPI0 Data In I A8 SPI0_SOUT SPI0 Data Out O B4 SPI1_PCS0 SPI1 Chip Select/Slave Select I/O B3 SPI1_SCK SPI1 Serial Clock I/O C3 SPI1_SIN SPI1 Data In I B2 SPI1_SOUT SPI1 Data Out O B6 DSPI switching specifications (limited voltage range) Master mode DSPI timing (compare Figure 2): Symbol Description Min. Max. Unit Operating voltage 2.7 3.6 V Frequency of operation - 12 MHz DS1 DSPI_SCK output cycle time 2 x tBUS - ns DS2 DSPI_SCK output high/low time (tSCK/2)-2 (tSCK/2)+2 ns DS3 DSPI_PCSn valid to DSPI_SCK delay (tBUS x 2)-2 - ns 11 11 The delay is programmable in SPIx_CTARn[PSSCK] and SPIx_CTARn[CSSCK]. Product Specification Rev. 0.1 Page 27  PAN4620 802.15.4 and BLE Module 4 Specification Symbol Description Min. DS4 DSPI_SCK to DSPI_PCSn invalid delay DS5 12 Max. Unit (tBUS x 2)-2 - ns DSPI_SCK to DSPI_SOUT valid - 8.5 ns DS6 DSPI_SCK to DSPI_SOUT invalid -2 - ns DS7 DSPI_SIN to DSPI_SCK input setup 16.2 - ns DS8 DSPI_SCK to DSPI_SIN input hold 0 - ns Figure 2 - Master mode DSPI timing. Slave mode DSPI timing (compare Figure 3): Symbol Description Min. Max. Unit Operating voltage 2.7 3.6 V Frequency of operation - 6 MHz DS9 DSPI_SCK output cycle time 4 x tBUS - ns DS10 DSPI_SCK output high/low time (tSCK/2)-2 (tSCK/2)+2 ns DS11 DSPI_SCK to DSPI_SOUT valid - 21.4 ns DS12 DSPI_SCK to DSPI_SOUT invalid 0 - ns DS13 DSPI_SIN to DSPI_SCK input setup 2.6 - ns DS14 DSPI_SCK to DSPI_SIN input hold 7.0 - ns DS15 DSPI_SS active to DSPI_SOUT driven - 14 ns DS16 DSPI_SS inactive to DSPI_SOUT not driven - 14 ns 12 The delay is programmable in SPIx_CTARn[PASC] and SPIx_CTARn[ASC]. Product Specification Rev. 0.1 Page 28  PAN4620 802.15.4 and BLE Module 4 Specification Figure 3 - Slave mode DSPI timing. 4.6.3.2 DSPI switching specifications (full voltage range) Master mode DSPI timing (compare Figure 4): Symbol Description Operating voltage Min. 13 Max. Unit 1.71 3.6 V Frequency of operation - 12 MHz DS1 DSPI_SCK output cycle time 2 x tBUS - ns DS2 DSPI_SCK output high/low time (tSCK/2)-4 (tSCK/2)+4 ns (tBUS x 2)-4 - ns (tBUS x 2)-4 - ns DS3 DSPI_PCSn valid to DSPI_SCK delay 14 15 DS4 DSPI_SCK to DSPI_PCSn invalid delay DS5 DSPI_SCK to DSPI_SOUT valid - 10 ns DS6 DSPI_SCK to DSPI_SOUT invalid -1.2 - ns DS7 DSPI_SIN to DSPI_SCK input setup 23.3 - ns DS8 DSPI_SCK to DSPI_SIN input hold 0 - ns 13 The DSPI module can operate across the entire operating voltage for the processor, but to run across the full voltage range the maximum frequency of operation is reduced. 14 The delay is programmable in SPIx_CTARn[PSSCK] and SPIx_CTARn[CSSCK]. 15 The delay is programmable in SPIx_CTARn[PASC] and SPIx_CTARn[ASC]. Product Specification Rev. 0.1 Page 29  PAN4620 802.15.4 and BLE Module 4 Specification Figure 4 - Master mode DSPI timing. Slave mode DSPI timing (compare Figure 5): Symbol Description Min. Max. Unit Operating voltage 1.71 3.6 V Frequency of operation - 6 MHz DS9 DSPI_SCK output cycle time 4 x tBUS - ns DS10 DSPI_SCK output high/low time (tSCK/2)-4 (tSCK/2)+4 ns DS11 DSPI_SCK to DSPI_SOUT valid - 29.1 ns DS12 DSPI_SCK to DSPI_SOUT invalid 0 - ns DS13 DSPI_SIN to DSPI_SCK input setup 3.2 - ns DS14 DSPI_SCK to DSPI_SIN input hold 7.0 - ns DS15 DSPI_SS active to DSPI_SOUT driven - 25 ns DS16 DSPI_SS inactive to DSPI_SOUT not driven - 25 ns Figure 5 - Slave mode DSPI timing. Product Specification Rev. 0.1 Page 30  PAN4620 802.15.4 and BLE Module 4 Specification 4.6.4 Carrier Modulator Timer (CMT) Please see also Section  4.8 General switching specification. Signal Name Description CMT_IRO 4.6.5 I/O Carrier Modulator Transmitter Infrared Output Pad O D2, E2 Touch Sensing Input (TSI) Signal Name Description TSI0_CH[15:0] I/O Touch sensing input capacitive pins Pad TSI0_CH0 → F5 I/O TSI0_CH1 → F8 TSI0_CH2 → E6 TSI0_CH3 → F7 TSI0_CH4 → B5 TSI0_CH5 → B4 TSI0_CH6 → A8 TSI0_CH7 → B3 TSI0_CH8 → C4 TSI0_CH9 → C5 TSI0_CH10 → B6 TSI0_CH11 → B2 TSI0_CH12 → C3 TSI0_CH13 → C2 TSI0_CH14 → E2 TSI0_CH15 → E1 TSI electrical specifications: Symbol Description Min. Typ Max. Unit Ta Ambient temperature -30 - 85 °C TSI_RUNF Fixed power consumption in run mode - 100 - µA TSI_RUNV Variable power consumption in run mode (depends on oscillator's current selection) 1.0 - 128 µA TSI_EN Power consumption in enable mode - 100 - µA TSI_DIS Power consumption in disable mode - 1.2 - µA TSI_TEN TSI analog enable time - 66 - µs Product Specification Rev. 0.1 Page 31  PAN4620 802.15.4 and BLE Module 4 Specification Symbol 4.6.6 Description Min. Typ Max. Unit TSI_CREF TSI reference capacitor - 1.0 - pF TSI_DVOLT Voltage variation of VP & VM around nominal values 0.19 - 1.03 V General Purpose Input/Output (GPIO) Signal Name PTA[19:16][2:0] Description General Purpose Input/Output I/O I/O Pad PTA0 → C4 PTA1 → C5 PTA2 → A3 PTA16 → B6 PTA17 → B2 PTA18 → C3 PTA19 → C2 PTB[18][3:0] General Purpose Input/Output I/O PTB0 → D1 PTB1 → D2 PTB2 → D3 PTB3 → D4 PTB18 → F3 PTC[19:16][7:0] General Purpose Input/Output I/O PTC0 → E5 PTC1 → A8 PTC2 → E2 PTC3 → E1 PTC4 → F5 PTC5 → F8 PTC6 → E6 PTC7 → F7 PTC16 → B5 PTC17 → B4 PTC18 → A8 PTC19 → B3 The maximum input voltage on PTC0/1/2/3 is VDD+0.3V. Please see also  4.8 General switching specification. Product Specification Rev. 0.1 Page 32  PAN4620 802.15.4 and BLE Module 4 Specification 4.6.7 Low-Leakage Wakeup (LLWU) Signal Name LLWU_P[15:0] Description Wakeup inputs I/O I Pad LLWU_P0 → B5 LLWU_P1 → B4 LLWU_P2 → A8 LLWU_P3 → B3 LLWU_P4 → B6 LLWU_P5 → B2 LLWU_P6 → C3 LLWU_P7 → C2 LLWU_P8 → D1 LLWU_P9 → E5 LLWU_P10 → E2 LLWU_P11 → E1 LLWU_P12 → F5 LLWU_P13 → F8 LLWU_P14 → E6 LLWU_P15 → F7 4.6.8 Radio Module Signals Signal Name Description I/O Pad DTM_RX Direct test mode receive I B4, D2, E2 DTM_TX Direct test mode transmit O A8, D3, E1 BSM_CLK Bit streaming mode (BSM) clock signal, 802.15.4 packet data stream clock line O B3, F8 BSM_FRAME Bit streaming mode frame signal, 802.15.4 packet data stream frame line O B4, E6 BSM_DATA Bit streaming mode data signal, 802.15.4 packet data stream data line I/O A8, F5, F7 RF_RESET Radio reset signal I B2 BLE_RF_ACTIVE Signal to indicate future BLE activity. O B3, C6 RF_NOT_ALLOWED Radio off signal, intended for Wi-Fi coexistence control I D3, F8 Product Specification Rev. 0.1 Page 33  PAN4620 802.15.4 and BLE Module 4 Specification Signal Name 4.6.9 Description I/O Pad RX_SWITCH Front end module receive mode signal O E1 TX_SWITCH Front end module transmit mode signal O E2 Analog-to-Digital Converter (ADC) Signal Name Description I/O Pad ADC0_DM0 ADC channel 0 differential input negative I F4 ADC0_DP0 ADC channel 0 differential input positive I F3 ADC0_SE[5:1] ADC channel 0 single-ended input I ADC0_SE1 → D2 ADC0_SE2 → D4 ADC0_SE3 → D3 ADC0_SE4 → F6 ADC0_SE5 → C2 16-bit ADC operating conditions: Symbol Description Min. Typ 16 Max. Unit VDDA Supply voltage absolute 1.71 - 3.6 V VREFH ADC reference voltage high, internally sourced and factory trimmed - 1.2 - V VREFL ADC reference voltage low - GND - VADIN Input voltage: 16-bit differential mode VREFL - 31/32∙VREFH V All other modes VREFL - VREFH V 16-bit mode - 8 10 pF 8-bit / 10-bit / 12-bit modes - 4 5 pF RADIN Input series resistance - 2 5 kΩ RAS Analog source resistance (external) 13-bit / 12-bit modes - - 5 kΩ CADIN Input capacitance: fADCK < 4 MHz fADCK ADC conversion clock frequency 17 16 Typical values assume VDDA = 3.0 V, Temp = 25 °C, fADCK = 1.0 MHz, unless otherwise stated. Typical values are for reference only, and are not tested in production. Product Specification Rev. 0.1 Page 34  PAN4620 802.15.4 and BLE Module 4 Specification Symbol Description Crate Min. Typ 16 Max. Unit ≤ 13-bit mode 1.0 - 18.0 MHz 16-bit mode 2.0 - 12.0 MHz ≤ 13-bit modes 20.000 - 818.330 ksps 16-bit mode 37.037 - 461.467 ksps ADC conversion rate: No ADC hardware averaging, continuous conversions enabled, subsequent conversion time 4.6.10 12-bit Digital-to-analog converter (DAC) Signal Name Description DAC0_OUT I/O DAC output O Pad F6 12-bit DAC operating requirements: Symbol VDDA Description Min. Supply voltage VDACR Reference voltage 18 CL Output load capacitance IL Output load current 19 Max. Unit 1.71 3.6 V 1.2 3.6 V - 100 pF - 1 mA 12-bit DAC operating behaviors: Symbol Description Min. Typ Max. Unit IDDA_DACLP Supply current - low-power mode - - 250 µA IDDA_DACHP Supply current – high speed mode - - 900 µA tDACLP Full-scale settling time (0x080 to 20 0xF7F) - low-power mode - 100 200 µs tDACHP Full-scale settling time (0x080 to 20 0xF7F) - high-speed mode - 15 30 µs 17 To use the maximum ADC conversion clock frequency, CFG2[ADHSC] must be set and CFG1[ADLPC] must be clear. 18 The DAC reference can be selected to be VDDA or VREFH=1.2 V. 19 A small load capacitance (47 pF) can improve the bandwidth performance of the DAC. 20 Settling within ±1 LSB. Product Specification Rev. 0.1 Page 35  PAN4620 802.15.4 and BLE Module 4 Specification Symbol Description Min. Typ Max. Unit tCCDACLP Code-to-code settling time (0xBF8 to 0xC08) - low-power mode and 20 high-speed mode - 0.7 1 µs Vdacoutl DAC output voltage range low high-speed mode, no load, DAC set to 0x000 - - 100 mV Vdacouth DAC output voltage range high – high-speed mode, no load, DAC set to 0xFFF VDACR-100 - VDACR mV INL Integral non-linearity error – high21 speed mode - - ±8 LSB DNL Differential non-linearity error 22 VDACR > 2 V - - ±1 LSB DNL Differential non-linearity error 23 VDACR = VREF_OUT - - ±1 LSB VOFFSET Offset error - ±0.4 ±0.8 %FSR EG Gain error 24 - ±0.1 ±0.6 %FSR PSRR Power supply rejection ratio, VDDA ≥ 2.4 V 60 - 90 dB TCO Temperature coefficient offset 25 voltage - 3.7 - µV/C TGE Temperature coefficient gain error - 0.00042 1 - %FSR/ C ROP Output resistance (load = 3 kΩ) - - 250 Ω SR Slew rate: High-power 1.2 1.7 - V/µs Low-power 0.05 0.12 - V/µs High-power 550 - - kHz Low-power 40 - - kHz 24 3 dB bandwidth: BW 21 The INL is measured for 0 + 100 mV to VDACR −100 mV. 22 The DNL is measured for 0 + 100 mV to VDACR −100 mV. 23 The DNL is measured for 0 + 100 mV to VDACR −100 mV with VDDA > 2.4 V. 24 Calculated by a best fit curve from VSS + 100 mV to VDACR – 100 mV. 25 VDDA = 3.0 V, reference select set for VDDA (DACx_CO:DACRFS = 1), high-power mode (DACx_C0:LPEN = 0), DAC set to 0x800, temperature range is across the full range of the device. Product Specification Rev. 0.1 Page 36  PAN4620 802.15.4 and BLE Module 4 Specification 4.6.11 Analog Comparator (CMP) Signal Name Description CMP0_IN[5:0] I/O Analog voltage inputs I Pad CMP0_IN0 → F3 CMP0_IN1 → F4 CMP0_IN2 → F6 CMP0_IN3 → D3 CMP0_IN4 → D4 CMP0_IN5 → D2 CMP0_OUT Comparator output O D1 CMP and 6-bit DAC electrical specifications: Symbol Description Min. Typ Max. Unit VDD Supply voltage 1.71 - 3.6 IDDHS Supply current, high-speed mode (EN=1, PMODE=1) - - 200 µA IDDLS Supply current, low-speed mode (EN=1, PMODE=0) - - 20 µA VAIN Analog input voltage VSS-0.3 - VDD V VAIO Analog input offset voltage - - 20 mV CR0[HYSTCTR] = 00 - 5 - mV CR0[HYSTCTR] = 01 - 10 - mV CR0[HYSTCTR] = 10 - 20 - mV CR0[HYSTCTR] = 11 - 30 - mV VCMPOh Output high VDD-0.5 - - V VCMPOl Output low - - 0.5 V tDHS Propagation delay, high-speed mode (EN=1, PMODE=1) 20 50 200 ns tDLS Propagation delay, low-speed mode (EN=1, PMODE=0) 80 250 600 ns Analog comparator initialization 27 delay - - 40 µs VH Analog comparator hysteresis 26 26 Typical hysteresis is measured with input voltage range limited to 0.6 to VDD–0.6 V. Product Specification Rev. 0.1 Page 37  PAN4620 802.15.4 and BLE Module 4 Specification Symbol 4.6.12 Description Min. Typ Max. Unit IDAC6b 6-bit DAC current adder (enabled) - 7 - µA INL 6-bit DAC integral non-linearity -0.5 - 0.5 LSB DNL 6-bit DAC differential non-linearity -0.3 - 0.3 LSB 28 Timer Signal Name TPM_CLKIN[1:0] Module TPM0 Description External clock I/O I Pad TPM_CLKIN0 → F6 TPM_CLKIN1 → B2 TPM0_CH[3:0] TPM0 TPM channel I/O TPM0_CH0 → F6, B6 TPM0_CH1 → D1, E1 TPM0_CH2 → C6, D2 TPM0_CH3 → A3, B5 TPM_CLKIN[1:0] TPM1 External clock I TPM_CLKIN0 → F6 TPM_CLKIN1 → B2 TPM1_CH[1:0] TPM1 TPM channel I/O TPM1_CH0 → C4, C5, F5 TPM1_CH1 → D3, D4, F8 TPM_CLKIN[1:0] TPM2 External clock I TPM_CLKIN0 → F6 TPM_CLKIN1 → B2 TPM2_CH[1:0] TPM2 TPM channel I/O TPM2_CH0 → C3, E6 TPM2_CH1 → C2, F7 LPTMR0_ALT[2:1] RTC_CLKOUT LPTMR0 RTC Module Pulse counter input pin I 1 Hz square-wave output O LPTMR0_ALT1 → D2 LPTMR0_ALT2 → F8 D4 27 Comparator initialization delay is defined as the time between software writes to change control inputs (Writes to CMP_DACCR[DACEN], CMP_DACCR[VRSEL], CMP_DACCR[VOSEL], CMP_MUXCR[PSEL], and CMP_MUXCR[MSEL]) and the comparator output settling to a stable level. 28 1 LSB = Vreference/64 Product Specification Rev. 0.1 Page 38  PAN4620 802.15.4 and BLE Module 4 Specification 4.6.13 Clocks Signal Name 4.6.14 Description I/O Pad CLKOUT Internal clocks monitor O D1, D4 XTAL_OUT_EN 32 MHz clock output enable I D1, E6 Serial Wire Debug (SWD) Signal Name Description Comment I/O Pad SWD_DIO Serial wire debug data Input/Output Pulled up internally by default I/O C4 SWD_CLK Serial wire clock Pulled down internally by default I C5 SWD full voltage range electricals as shown in Figure 6 and Figure 7: Symbol Description Min. Max. Unit Operating voltage 1.71 3.6 V J1 SWD_CLK frequency of operation - 25 MHz J2 SWD_CLK cycle period 1/J1 - ns J3 SWD_CLK clock pulse width 20 - ns J4 SWD_CLK rise and fall times - 3 ns J9 SWD_DIO input data setup time to SWD_CLK rise 10 - ns J10 SWD_DIO input data hold time after SWD_CLK rise 0 - ns J11 SWD_CLK high to SWD_DIO data valid - 32 ns J12 SWD_CLK high to SWD_DIO high-Z 5 - ns Figure 6 - SWD clock input timing. Product Specification Rev. 0.1 Page 39  PAN4620 802.15.4 and BLE Module 4 Specification Figure 7 - SWD data timing. 4.7 Flash electrical specifications The following specifications represent the amount of time the internal charge pumps are active and do not include command overhead. Flash timing specifications - program and erase: Symbol Description Min. thvpgm4 Longword program high-voltage time thversscr Sector erase high-voltage time thversblk256k Erase block high-voltage time for 256 KB 29 29 Typ Max. Unit - 7.5 18 µs - 13 113 ms - 104 904 ms Flash timing specifications - commands: Symbol trd1blk256k Description Min. 30 Read 1s block execution time Typ Max. Unit - - 1.7 ms 256 KB program flash trd1sec2k tpgmchk trdrsrc Read 1s section execution time (flash sector) - - 60 µs 30 - - 45 µs 30 - - 30 µs Program check execution time Read resource execution time 30 29 Maximum time based on expectations at cycling end-of-life. 30 Assumes 25 MHz flash clock frequency. Product Specification Rev. 0.1 Page 40  PAN4620 802.15.4 and BLE Module 4 Specification Symbol Description Min. Typ Max. Unit tpgm4 Program longword execution time - 65 145 µs tersblk256k Erase flash block execution time 31 - 250 1500 ms 31 - 14 114 ms 30 - - 1.8 ms - - 30 µs - 100 - µs - 500 3000 ms - - 30 µs - 500 3000 ms Typ Max. 256 KB program flash tersscr Erase flash sector execution time trd1all Read 1s all blocks execution time 30 trdonce Read once execution time tpgmonce Program once execution time tersall Erase all blocks execution time tvfykey Verify backdoor access key execution time tersallu Erase all blocks unsecure execution time 31 30 31 Flash high voltage current behaviors: Symbol 4.8 Description Min. Unit IDD_PGM Average current adder during high voltage flash programming operation - 2.5 6.0 mA IDD_ERS Average current adder during high voltage flash erase operation - 1.5 4.0 mA General switching specification These specifications apply to GPIO, LPUART, CMT, and I2C signals. Description Min. Max. Unit GPIO pin interrupt pulse width (digital glitch filter disabled) 32 33 Synchronous path , 1.5 - Bus clock cycles Reset pin interrupt pulse width (analog filter enabled) 34 Asynchronous path 200 - ns GPIO pin interrupt pulse width (digital glitch filter disabled, analog 5 filter disabled) - Asynchronous path 20 - ns External RESET_b input pulse width (digital glitch filter disabled) 100 - ns 31 Maximum times for erase parameters based on expectations at cycling end-of-life. 32 This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry in run modes. 33 The greater of synchronous and asynchronous timing must be met. 34 This is the minimum pulse width that is guaranteed to be recognized. Product Specification Rev. 0.1 Page 41  PAN4620 802.15.4 and BLE Module 4 Specification Description Min. Port rise and fall time(low drive strength) Max. Unit 35,36 Slew enabled: 1.71 ≤ VDD ≤ 2.7 V - 25 ns 2.7 ≤ VDD ≤ 3.6 V - 16 ns 1.71 ≤ VDD ≤ 2.7 V - 8 ns 2.7 ≤ VDD ≤ 3.6 V - 6 ns 1.71 ≤ VDD ≤ 2.7 V - 24 ns 2.7 ≤ VDD ≤ 3.6 V - 16 ns 1.71 ≤ VDD ≤ 2.7 V - 10 ns 2.7 ≤ VDD ≤ 3.6 V - 6 ns Slew disabled: Port rise and fall time(low drive strength) 37,38 Slew enabled: Slew disabled: 4.9 Transceiver Feature Summary ® ® The PAN4620 module meets or exceeds all Bluetooth Low Energy v4.2 and IEEE 802.15.4 performance specifications applicable to 2.4 GHz ISM and MBAN (Medical Band Area Network) bands. 4.9.1 Channel Plan ® Channel Plan for Bluetooth Low Energy: Band Carrier frequency [MHz] ISM 2402 + k ∙ 2 39 Channel number k k = [0,1,…,38,39] ® Channel Plan for IEEE 802.15.4: Band Carrier frequency [MHz] 40 Channel number k 2405 + (k-11) ∙ 5 ISM k = [11,12,…,25,26] 35 PTB0, PTB1, PTC0, PTC1, PTC2, PTC3, PTC6, PTC7, PTC17, PTC18. 36 75 pF load. 37 Ports A, B, and C. 38 25 pF load. 39 All the RX parameters are measured at the PAN4620 RF bottom pad. 40 All the RX parameters are measured at the PAN4620 RF bottom pad. Product Specification Rev. 0.1 Page 42  PAN4620 802.15.4 and BLE Module 4 Specification Band Carrier frequency [MHz] 40 Channel number k 2363 + k ∙ 5 MBAN k = [0,1,2,3,4,5,6] 2367 + (k-7) ∙ 5 4.9.2 k = [7,8,9,10,11,12,14] Receiver Feature Summary The current consumption and sensitivity depend on the user scenario. Assume VDD = 3.6 V, Tamb = 25 °C, if nothing else is stated. 40 Symbol Description IRXon Supply current Rx On (VDD = 3.6 V) fIN Input RF frequency SENSGFSK GFSK Rx sensitivity (250 kbps GFSK-BT=0.5, h=0.5) SENSBLE BLE Rx sensitivity SENS15.4 Min. Typ. 41 Max. Units - 8.4 2.36 - - -98 - -93 - dBm - -98 - dBm tbd - tbd dBm - 1 - dBm Typical RSSI variation over frequency tbd - tbd dB Typical RSSI variation over temperature tbd - tbd dB -3 - - tbd - dB - tbd - dB 42 ® 43 IEEE 802.15.4 Rx sensitivity 44 RSSIRange Receiver signal strength indicator range RSSIRes Receiver signal strength indicator resolution 45 RSSIACC Narrowband RSSI accuracy BLEco-channel BLE Co-channel Interference (Wanted signal at -67 dBm, BER