MTM78E2B0LBF

Doc No. TT4-EA-12408 Revision. 2 Product Standards MOS FET MTM78E2B0LBF MTM78E2B0LBF Gate Resistor installed Dual N-Channel MOS Type Unit: mm 2.0 For lithium-ion secondary battery protection circuit 0.2 8 7 6 5 1 2 3 4 1.7 2.1  Features 0.13  Low drain-source On-state Resistance RDS(on) typ. = 21.5 m (VGS =4.0 V)  Halogen-free / RoHS compliant (EU RoHS / UL-94 V-0 / MSL:Level 1 compliant) 0.7 0.5  Marking Symbol: 5A 1. 2. 3. 4. Source 1 Gate 1 Source 2 Gate 2 5. 6. 7. 8. Drain Drain Drain Drain  Packaging Embossed type (Thermo-compression sealing) : 3 000 pcs / reel (standard)  Absolute Maximum Ratings Ta = 25 C Parameter Symbol Drain-source Voltage FET1 Gate-source Voltage FET2 Drain current *1 Peak drain current Total power dissipation Overall Channel temperature Operating ambient temperature Storage temperature Note) *1 t = 10 μs, Duty Cycle < 1 % Ceramic substrate (70 70 t 1.0 mm) *2 Dual operating *3 Stand-alone (without the substrate) VDS VGS ID IDp PD1*2 PD2*3 Tch Topr Tstg Panasonic JEITA Code WSMini8-F1-B SC-113E ― Internal Connection Rating Unit 20 12 4.0 40 700 150 150 -40 to +85 -55 to +150 V V A A (D) 8 (D) 7 mW (D) 6 (D) 5 Rg = 1 kΩ Rg = 1 kΩ °C °C °C 1 2 3 4 (S1) (G1) (S2) (G2) Pin Name 1. 2. 3. 4. Source 1 Gate 1 Source 2 Gate 2 5. 6. 7. 8. Drain Drain Drain Drain Page 1 of 6 Established : 2010-03-03 Revised : 2013-10-15 Doc No. TT4-EA-12408 Revision. 2 Product Standards MOS FET MTM78E2B0LBF  Electrical Characteristics Ta = 25C  3C Parameter Drain-source surrender voltage Drain-source cutoff current Gate-source cutoff current Gate threshold voltage Symbol Conditions ID = 1.0 mA, VGS = 0 VDS = 20 V, VGS = 0 VGS = 12 V, VDS = 0 ID = 1.0 mA, VDS = 10 V RDS(ON)1 ID = 2.0 A, VGS = 4.0 V Drain-source ON resistance RDS(ON)2 ID = 1.5 A, VGS = 3.0 V RDS(ON)3 ID = 1.0 A, VGS = 2.5 V Forward transfer admittance ID = 1.0 A, VDS = 10 V |Yfs| Short-circuit input capacitance (Common source) Ciss Short-circuit output capacitance (Common source) VDS = 10 V, VGS = 0, f = 1 MHz Coss Reverse transfer capacitance (Common source) Crss td(on) Turn-on delay time *1, *2 VDD = 10 V, VGS = 4 V, tr Rise time *1, *2 *1, *2 ID = 1.0 A, RL = 10  td(off) Turn-off delay time *1, *2 tf Fall time Note) VDSS IDSS IGSS Vth Min Typ Max 0.85 21.5 26.0 30.0 1.0 10 1.30 25.0 30.0 36.0 20 0.40 1.0 1100 75 70 0.2 0.5 2.0 1.5 Unit V μA μA V m m m S pF pF pF μs μs μs μs 1. Measuring methods are based on JAPANESE INDUSTRIAL STANDARD JIS C 7030 Measuring methods for transistors. 2. *1 t = 10 μs, Duty Cycle < 1 % *2 Measurement circuit for Turn-on Delay Time/Rise Time/Turn-off Delay Time/Fall Time Page 2 of 6 Established : 2010-03-03 Revised : 2013-10-15 Doc No. TT4-EA-12408 Revision. 2 Product Standards MOS FET MTM78E2B0LBF *2 Measurement circuit for Turn-on Delay Time/Rise Time/Turn-off Delay Time/Fall Time ID 4V PW = 10μs D.C.  1 % 0V D RL G Pulse Generator RG VDD 50  S 90 % VGS VGS 10 % 0 90 % VDD VDS 10 % 0 td(on) tr td(off) tf Page 3 of 6 Established : 2010-03-03 Revised : 2013-10-15 Doc No. TT4-EA-12408 Revision. 2 Product Standards MOS FET MTM78E2B0LBF Technical Data ( reference ) ID - VDS ID - VGS 0.1 4 VGS = 4.0 V 3 Drain current ID (A) Drain Current ID (A) 2.5 V 3.0 V 2.0 V 2 1.5 V 1 0.075 Ta = 85 ℃ 0.05 25 ℃ 0.025 - 40 ℃ 0 0 0 0.1 0.2 0 0.3 0.5 1.5 2 Gate-source voltage VGS (V) Drain-source Voltage VDS (V) VDS - VGS RDS(on) - ID 100 Drain-source On-state Resistance RDS(on) (m) 0.3 Drain-source Voltage VDS (V) 1 0.25 0.2 2.0 A 0.15 ID = 4.0 A 0.1 0.05 1.0 A 0 0 1 2 3 4 5 6 2.5 V 3.0 V VGS = 4.0 V 10 0.1 1 Gate-source Voltage VGS (V) 10 Drain Current ID (A) Dynamic Input/Output Characteristics Gate-source Voltage VGS (V) 5 4 VDD = 10V 3 2 1 0 0 2 4 6 8 10 Total Gate Charge Qg (nC) Page 4 of 6 Established : 2010-03-03 Revised : 2013-10-15 Doc No. TT4-EA-12408 Revision. 2 Product Standards MOS FET MTM78E2B0LBF Technical Data ( reference ) Vth - Ta RDS(on) - Ta 50 Drain-source On-resistance RDS(on) (m) Gate-source Threshold Voltage Vth (V) 1.5 1 0.5 VGS = 2.5 V 40 3.0 V 30 4.0 V 20 10 0 0 -50 0 50 100 150 -50 0 Temperature (℃) 50 100 150 Temperature (℃) PD - Ta Total Power Dissipation PD (W) 1 Ceramic substrate (70  70  t 1.0 mm), Dual operating 0.8 0.6 0.4 Non-heat sink 0.2 0 0 50 100 150 Temperature Ta (C) Rth - tsw Safe Operating Area 100 IDp = 40 A Drain Current ID (A) Thermal resistance Rth (C/W) 1000 100 10 1 0.01 0.1 1 10 Pulse Width tsw (s) 100 1000 10 Operation in this area is limited by RDS(on) 1 0.1 0.01 0.01 1 ms 10 ms Ta = 25 C, Glass epoxy board (25.4 × 25.4 × t0.8 mm) coated with copper foil, which has more than 100 ms 1s DC 300 mm2. 0.1 1 10 100 Drain-source Voltage VDS (V) Page 5 of 6 Established : 2010-03-03 Revised : 2013-10-15 Doc No. TT4-EA-12408 Revision. 2 Product Standards MOS FET MTM78E2B0LBF WSMini8-F1-B Unit : mm 2.0±0.1 +0.05 0.13-0.03 7 6 5 1 2 3 4 (0.2) (7°) 1.7±0.1 8 2.1±0.1 +0.05 0.20-0.02 0 to 0.1 (7°) (0.15) 0.70±0.05 0.5  Land Pattern (Reference) (Unit : mm) 0.7 1.8 0.5 0.5 0.5 0.3 Page 6 of 6 Established : 2010-03-03 Revised : 2013-10-15 Request for your special attention and precautions in using the technical information and semiconductors described in this book (1) If any of the products or technical information described in this book is to be exported or provided to non-residents, the laws and regulations of the exporting country, especially, those with regard to security export control, must be observed. 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