N32T1630C1C

NanoAmp Solutions, Inc. 670 North McCarthy Blvd. Suite 220, Milpitas, CA 95035 ph: 408-935-7777, FAX: 408-935-7770 www.nanoamp.com N32T1630C1C 32Mb Ultra-Low Power Asynchronous CMOS Pseudo SRAM w/ Page Mode Operation (2M x 16 bit) Overview The N32T1630C1C is an integrated memory device containing a 32 Mbit SRAM built using a self-refresh DRAM array organized as 2,097,152 words by 16 bits. The device is designed and fabricated using NanoAmp’s advanced CMOS technology to provide both high-speed performance and ultra-low power. It is designed to be identical in operation and interface to standard 6T SRAMS. Byte controls (UB and LB) allow the upper and lower bytes to be accessed independently and can also be used to deselect the device. The N32T1630C1C offers a very high speed page mode operation for improved performance and operating power savings. The device is optimal for various applications where low-power is critical such as battery backup and hand-held devices. Also included are several power savings modes: a deep sleep mode and partial array refresh mode where data is retained in a portion of the array. The device can operate over a very wide temperature range of -25oC to +85oC and is available in a JEDEC standard VFRBGA package compatible with other standard 2Mb x 16 SRAMs. Features • Dual voltage for Optimum Performance: VccQ - 2.7 to 3.6 Volts Vcc - 2.7 to 3.6 Volts (Vcc ≤ VccQ) • Fast random access time 70ns at 2.7V • Very fast page mode access time 25ns page cycle and access • Very low standby current 80µA V (Typical) • Very low operating current 1.0mA at 1µs (Typical) • Simple memory control Byte control for independent byte operation Output Enable (OE) for memory expansion • Automatic power down to standby mode • PAR and RMS power saving modes • Deep sleep option • TTL compatible three-state output driver Product Family Part Number Package Type Operating Temperature Power Supply 2.7V - 3.6V (VCC) Speed 70ns Standby Current (ISB), Max Operating Current (Icc), Max N32T1630C1CZ 48-VFRBGA -25oC to +85oC 135 µA @ 3.3V 3 mA @ 1MHz Pin Configuration (Top View) 1 A B C D E F G H LB I/O8 I/O9 Pin Descriptions Pin Name A0-A20 WE CE OE UB,LB ZZ I/O0-I/O15 VCC VCCQ VSS VSSQ DNU Pin Function Address Inputs Write Enable Input Chip Enable Input Output Enable Input Byte Enable Inputs Deep Sleep Input Data Inputs/Outputs Core Power I/O Power Ground I/O Ground Do Not Use 2 OE UB I/O10 3 A0 A3 A5 A17 DNU/ VSS A14 A12 A9 4 A1 A4 A6 A7 A16 A15 A13 A10 5 A2 CE I/O1 I/O3 I/O4 I/O5 WE A11 6 ZZ I/O0 I/O2 VCC VSS I/O6 I/O7 A20 VSSQ I/O11 VCCQ I/O12 I/O14 I/O13 I/O15 A18 A19 A8 48 Ball VFRBGA 6 x 8 mm (DOC# 14-02-005 Rev C ECN 01-0918) The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com. 1 NanoAmp Solutions, Inc. Functional Block Diagram N32T1630C1C Word Address Inputs A0 - A3 Page Address Inputs A4 - A20 Word Address Decode Logic Page Address Decode Logic 128K page x 16 word x 16 bit RAM Array Input/ Output Mux and Buffers I/O0 - I/O7 I/O8 - I/O15 CE ZZ WE OE UB LB Control Logic Functional Description CE H X L L L X ZZ H H H H H L WE X X L H H X OE X X X3 L H X UB X H L1 L1 L X LB X H L1 L1 L X I/O0 - I/O151 High Z High Z Data In Data Out High Z High Z MODE Standby2 Standby2 Write Read Active Deep Sleep POWER Standby Standby Active Active Active Deep Sleep 1. When UB and LB are in select mode (low), I/O0 - I/O15 are affected as shown. When LB only is in the select mode only I/O0 - I/O7 are affected as shown. When UB is in the select mode only I/O8 - I/O15 are affected as shown. 2. When the device is in standby mode, control inputs (WE, OE, UB, and LB), address inputs and data input/outputs are internally isolated from any external influence and disabled from exerting any influence externally. 3. When WE is invoked, the OE input is internally disabled and has no effect on the circuit. Capacitance1 Item Input Capacitance I/O Capacitance Symbol CIN CI/O Test Condition VIN = 0V, f = 1 MHz, TA = 25oC VIN = 0V, f = 1 MHz, TA = 25oC Min Max 6 8 Unit pF pF 1. These parameters are verified in device characterization and are not 100% tested (DOC# 14-02-005 Rev C ECN 01-0918) The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com. 2 NanoAmp Solutions, Inc. Absolute Maximum Ratings1 Item Voltage on any pin relative to VSS Voltage on VCC Supply Relative to VSS Power Dissipation Storage Temperature Operating Temperature Soldering Temperature and Time Symbol VIN,OUT VCC PD TSTG TA TSOLDER 240oC, N32T1630C1C Rating –0.2 to VCCQ+0.3 –0.2 to 4.0 500 –55 to 125 -25 to +85 10sec(Lead Only) Unit V V mW o C oC oC 1. Stresses greater than those listed above may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operating section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Operating Characteristics (Over Specified Temperature Range) Item Supply Voltage Supply Voltage for I/O Input High Voltage Input Low Voltage Output High Voltage Output Low Voltage Input Leakage Current Output Leakage Current Read/Write Operating Supply Current @ 1 µs Cycle Time2 Read/Write Operating Supply Current @ 70 ns Cycle Time2 Maximum Standby Current3 Symbol VCC VCCQ VIH VIL VOH VOL ILI ILO ICC1 ICC2 ISB1 IOH = 0.2mA IOL = -0.2mA VIN = 0 to VCC OE = VIH or Chip Disabled VCC= 3.3V, VIN=CMOS levelsChip Enabled, IOUT = 0 VCC= 3.3V, VIN=CMOS levels Chip Enabled, IOUT = 0 VCC= 3.3V, VIN=CMOS levels Chip Disabled 80 VCC = VCCQ (Note 4) Test Conditions Min. 2.7 2.7 0.8VCCQ –0.2 0.8VccQ 0.2 0.5 0.5 3.0 25.0 135.0 Typ1 3.0 3.0 Max 3.6 3.6 VCCQ+0.2 0.4 Unit V V V V V V µA µA mA mA µA 1. Typical values are measured at Vcc=Vcc Typ., TA=25°C and not 100% tested. 2. This parameter is specified with the outputs disabled to avoid external loading effects. The user must add current required to drive output capacitance expected in the actual system. 3. This device assumes a standby mode if the chip is disabled (either CE high or both UB and LB high). In order to achieve low standby current all inputs must be within 0.2V of either VCC or VSS 4. During testing, Vcc = VccQ. (DOC# 14-02-005 Rev C ECN 01-0918) The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com. 3 NanoAmp Solutions, Inc. Power Up Initialization Timing 2.7V Device Initialization 100µs N32T1630C1C VCC VCCQ Device Ready for Normal Operation The device will require 100 µs to complete its self-initialization process. During the initialization period, CE# pin should remain HIGH. FIGURE 1: Output Load Circuit VCCQ 14.5K I/O 14.5K 30 pF (DOC# 14-02-005 Rev C ECN 01-0918) The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com. 4 NanoAmp Solutions, Inc. N32T1630C1C Timing Item Read Cycle Time Address Access Time Page Mode Read Cycle Time Page Mode Access Time Chip Enable to Valid Output Output Enable to Valid Output Byte Select to Valid Output Chip Enable to Low-Z output Output Enable to Low-Z Output Byte Select to Low-Z Output Chip Disable to High-Z Output Output Disable to High-Z Output Byte Select Disable to High-Z Output Output Hold from Address Change Write Cycle Time Page Mode Write Cycle Time Chip Enable to End of Write Address Valid to End of Write Byte Select to End of Write Write Pulse Width Address Setup Time Write Recovery Time Write to High-Z Output Data to Write Time Overlap Page Mode Data to Write Time Overlap Data Hold from Write Time Page Mode Data Hold from Write Time End Write to Low-Z Output CE Precharge Maximum Page Mode Cycle Symbol tRC tAA tPC tPA tCO tOE tLB, tUB tLZ tOLZ tLBZ, tUBZ tHZ tOHZ tLBHZ, tUBHZ tOH tWC tPWC tCW tAW tLBW, tUBW tWP tAS tWR tWHZ tDW tPDW tDH tPDH tOW tCP tPGMAX 25 20 0 0 5 10 20000 10 5 10 0 0 0 5 70 25 60 60 60 55 0 0 20 20000 20000 20 20 20 25 70ns Min. 70 70 20000 25 70 20 70 Max. Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns (DOC# 14-02-005 Rev C ECN 01-0918) The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com. 5 NanoAmp Solutions, Inc. Timing of Read Cycle (CE = OE = VIL, WE = VIH) tRC Address tAA tOH N32T1630C1C Data Out Previous Data Valid Data Valid Timing Waveform of Read Cycle (WE=VIH) tRC Address tAA CE tCO tLZ tOE OE tOLZ tLB, tUB LB, UB tLBLZ, tUBLZ Data Out High-Z tLBHZ, tUBHZ Data Valid tHZ tOHZ (DOC# 14-02-005 Rev C ECN 01-0918) The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com. 6 NanoAmp Solutions, Inc. Timing Waveform of Page Mode Read Cycle (WE = VIH) tPGMAX Page Address (A4 - A20) tRC tPC N32T1630C1C Word Address (A0 - A3) tAA CE tCO tOE OE tOLZ LB, UB tLB, tUB tOHZ tPA tHZ tLBHZ, tUBHZ Data Out High-Z tLBLZ, tUBLZ tPGMAX means any page address (A4-A20) must be changed at least once in a 20us period (DOC# 14-02-005 Rev C ECN 01-0918) The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com. 7 NanoAmp Solutions, Inc. Timing Waveform of Write Cycle (WE Control) tWC Address Address tAW N32T1630C1C tWR CE tCW tLBW, tUBW LB, UB tAS WE tDW High-Z Data In tWHZ Data Out High-Z tDH tWP Data Valid tOW Timing Waveform of Write Cycle (CE Control) tWC Address tAW CE tAS tLBW, tUBW LB, UB tWP WE tDW Data In tLZ Data Out tWHZ tDH tCW tWR Data Valid High-Z (DOC# 14-02-005 Rev C ECN 01-0918) The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com. 8 NanoAmp Solutions, Inc. Timing Waveform of Page Mode Write Cycle tPGMAX Page Address (A4 - A20) tWC Word Address (A0 - A3) tAS tPWC N32T1630C1C tCP tCW CE tWP WE tLBW, tUBW LB, UB tDW High-Z tDH tPDW tPDH tPDW tPDH Data Out tPGMAX means any page address (A4-A20) must be changed at least once in a 20us period (DOC# 14-02-005 Rev C ECN 01-0918) The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com. 9 NanoAmp Solutions, Inc. N32T1630C1C Power Savings Modes The N32T1630C1C has several power savings modes and the three modes are: Reduced Memory Size Partial Array Refresh Deep Sleep Mode The operation of the power saving modes is controlled by setting the Variable Address Register (VAR). This VAR is shown in Figure 8 and is used to enable/disable the various low power modes. The VAR is set by using the timings defined in figure 9. The register must be set in less then 1us after ZZ is enabled low. 1) Reduced Memory Size (RMS) In this mode of operation, the 32Mb PSRAM can be operated as a 8Mb or 16Mb device. The mode and array size are determined by the settings in the VA register. The VA register is set according to the timings of Figure 9 and the bit setting of Table 12. The RMS mode is enabled at the time of ZZ transitioning high and the mode remains active until the register is updated. To return to the full 32Mb address space, the VA register must be reset using the previously defined procedures. 2) Partial Array Refresh (PAR) In this mode of operation, the internal refresh operation can be restricted to a 8Mb or 16Mb portion of the array. The mode and array partition to be refreshed are determined by the settings in the VAR register. The VAR register is set according to the timings of Figure 9 and the bit settings of Table 11. In this mode, when ZZ is taken low, only the portion of the array that is set in the register is refreshed. The operating mode is only available during standby time and once ZZ is returned high, the device resumes full array refresh. All future PAR cycles will use the contents of the VA register. To change the address space of the PAR mode, the VA register must be reset using the previously defined procedures. There are two different device versions that have different default settings for the PAR mode. In the first version, the default state for the ZZ enable/disable register will be ZZ enabled where ZZ low will initiate a deep sleep mode after 1us. This device is referred to as Deep Sleep Active, or DSA device. In the second version, the default state for the ZZ register will be such that ZZ low will put the device into PAR mode after 1us and never initiate a deep sleep mode unless appropriate register is updated. This device is referred to as Deep Sleep Inactive, or DSI device. In either device, once the SRAM enters Deep Sleep Mode, the VAR contents are destroyed and the default register settings are reset. 3) Deep Sleep Mode In this mode of operation, the internal refresh is turned off and all data integrity of the array is lost. Deep Sleep is entered by bringing ZZ low. After 1 us, if the VAR register corresponding to A4 is not set to Deep Sleep Disabled, the device will enter Deep Sleep Mode. The device will remain in this mode as long as ZZ remains low. (DOC# 14-02-005 Rev C ECN 01-0918) The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com. 10 NanoAmp Solutions, Inc. FIGURE 2: Variable Address Register N32T1630C1C A20 - A5 A4 A3 A2 A1 A0 Array mode for ZZ Reserved for future Preferably set to all 0 0 = PAR mode (default) 1 = RMS mode 1 1 0 0 Array section 1 = 1/4 array 0 = 1/2 array 1 = Reserved 0 = Full array (default) ZZ Enable/Disable 0 = Deep Sleep Enabled (default for DSA device) 1 = Deep Sleep Disabled (default for DSI device) Array half 0 = Bottom array (default) 1 = Top array FIGURE 3: Variable Address Register (VAR) Update Timings tWC A0-A4 CE WE ZZ LB, UB tCDZZ tZZWE tLBW, UBW tAW tAS tWP tWR FIGURE 4: Deep Sleep Mode - Entry/Exit Timings tZZMIN ZZ CE or LB, UB tCDZZ tR (DOC# 14-02-005 Rev C ECN 01-0918) The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com. 11 NanoAmp Solutions, Inc. N32T1630C1C Table 1: VAR Update and Deep Sleep Timings Item PAR and RMS ZZ low to WE low Chip (CE, UB/LB) deselect to ZZ low Deep Sleep Mode Deep Sleep Recovery Symbol tzzwe tcdzz tzzmin tr 0 10 200 Min Max 1000 Unit ns ns us us TABLE 2: Address Patterns for PAR (A3 = 0, A4 = 1) A2 A1 A0 Active Section Address space Size Density 0 0 1 1 1 1 1 1 1 0 1 0 One-quarter of die One-half of die One-quarter of die One-half of die 000000h - 07FFFFh 000000h - 0FFFFFh 180000h - 1FFFFFh 100000h - 1FFFFFh 512Kb x 16 1Mb x 16 512Kb x 16 1Mb x 16 8Mb 16Mb 8Mb 16Mb TABLE 3: Address patterns for RMS (A3 = 1, A4 = 1) A2 A1 A0 Active Section Address space Size Density 0 0 0 1 1 1 1 1 0 1 1 0 1 0 0 1 0 0 One-quarter of die One-half of die Full die One-quarter of die One-half of die Full die 000000h - 07FFFFh 000000h - 0FFFFFh 000000h - 1FFFFFh 180000h - 1FFFFFh 100000h - 1FFFFFh 000000h - 1FFFFFh 512Kb x 16 1Mb x 16 2Mb x 16 512Kb x 16 1Mb x 16 2Mb x 16 8Mb 16Mb 32Mb 8Mb 16Mb 32Mb (DOC# 14-02-005 Rev C ECN 01-0918) The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com. 12 NanoAmp Solutions, Inc. N32T1630C1C TABLE 4: Low Power ICC Characteristics for N32T1630C1C Item PAR Mode Standby Current RMS Mode Standby Current Deep Sleep Current Symbol IPAR IRMSSB IZZ Test VIN = VCC or 0V, Chip Disabled, tA= 85oC VIN = VCC or 0V, Chip Disabled, tA= 85oC o Array Partition 1/4 Array 1/2 Array 8Mb Device 16Mb Device Typ Max tbd tbd tbd tbd 10 Unit uA uA uA VIN = VCC or 0V, Chip in ZZ mode, tA= 85 C (DOC# 14-02-005 Rev C ECN 01-0918) The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com. 13 NanoAmp Solutions, Inc. VFRBGA Package Dimension A1 BALL PAD CORNER (3) D 0.23±0.05 0.90±0.10 N32T1630C1C 1. 0.30±0.05 DIA. E 2. SEATING PLANE - Z 0.15 Z 0.05 TOP VIEW SIDE VIEW 1. DIMENSION IS MEASURED AT THE A1 BALL PAD MAXIMUM SOLDER BALL DIAMETER. CORNER PARALLEL TO PRIMARY Z. 2. PRIMARY DATUM Z AND SEATING PLANE ARE DEFINED BY THE SPHERICAL CROWNS OF THE SOLDER BALLS. 3. A1 BALL PAD CORNER I.D. TO BE MARKED BY INK. K TYP J TYP e Z SD e SE BOTTOM VIEW Dimensions (mm) e = 0.75 D 6±0.10 E SD 8±0.10 0.375 SE 0.375 J 1.125 K 1.375 BALL MATRIX TYPE FULL (DOC# 14-02-005 Rev C ECN 01-0918) The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com. 14 NanoAmp Solutions, Inc. Ordering Information N32T1630C1C N32T1630C1CZ-XX I Performance 70 = 70ns Note: Add -T&R following the part number for Tape and Reel. Orders will be considered in tray if not noted. Revision History Revision A B C Date July 2004 July 2004 August 2004 Change Description Initial Release General Update Changed Ball (E3) from Vss to DNU/VSS Changed Max Vcc/VccQ from 3.3V to 3.6V © 2003 Nanoamp Solutions, Inc. All rights reserved. NanoAmp Solutions, Inc. ("NanoAmp") reserves the right to change or modify the information contained in this data sheet and the products described therein, without prior notice. NanoAmp does not convey any license under its patent rights nor the rights of others. Charts, drawings and schedules contained in this data sheet are provided for illustration purposes only and they vary depending upon specific applications. NanoAmp makes no warranty or guarantee regarding suitability of these products for any particular purpose, nor does NanoAmp assume any liability arising out of the application or use of any product or circuit described herein. NanoAmp does not authorize use of its products as critical components in any application in which the failure of the NanoAmp product may be expected to result in significant injury or death, including life support systems and critical medical instruments. (DOC# 14-02-005 Rev C ECN 01-0918) The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com. 15