NT5DS32M8CS-6K

NanoAmp Solutions, Inc. 670 N. McCarthy Blvd. Ste.#220, Milpitas, CA 95035 ph: 408-935-7777 www.nanoamp.com NT5DS64M4CT, NT5DS32M8CT, NT5DS16M16CT NT5DS64M4CS, NT5DS32M8CS, NT5DS16M16CS 256Mb DDR Synchronous DRAM Features CAS Latency and Frequency CAS Latency 2 2.5 3 Maximum Operating Frequency (MHz) DDR400 DDR333 (5T) (6K) 133 166 166 200 - • • • • • • • • • • • • • • • DDR 256M bit, die C, based on 110nm design rules • Double data rate architecture: two data transfers per clock cycle • Bidirectional data strobe (DQS) is transmitted and received with data, to be used in capturing data at the receiver • DQS is edge-aligned with data for reads and is centeraligned with data for writes Differential clock inputs (CK and CK) Four internal banks for concurrent operation Data mask (DM) for write data DLL aligns DQ and DQS transitions with CK transitions Commands entered on each positive CK edge; data and data mask referenced to both edges of DQS Burst lengths: 2, 4, or 8 CAS Latency: 2/2.5(DDR333) , 2.5/3(DDR400) Auto Precharge option for each burst access Auto Refresh and Self Refresh Modes 7.8µs Maximum Average Periodic Refresh Interval 2.5V (SSTL_2 compatible) I/O VDD = VDDQ = 2.5V ± 0.2V (DDR333) VDD = VDDQ = 2.6V ± 0.1V (DDR400) Available in Halogen and Lead Free packaging Description NT5DS64M4CT, NT5DS32M8CT and NT5DS16M16CT, NT5DS64M4CS, NT5DS32M8CS and NT5DS16M16CS are 256Mb SDRAM devices based using a DDR interface. They are all based on Nanya’s 110 nm design process. The 256Mb DDR SDRAM uses a double-data-rate architecture to achieve high-speed operation. The double data rate architecture is essentially a 2n prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write access for the 256Mb DDR SDRAM effectively consists of a single 2n-bit wide, one clock cycle data transfer at the internal DRAM core and two corresponding n-bit wide, one-half-clock-cycle data transfers at the I/O pins. A bidirectional data strobe (DQS) is transmitted externally, along with data, for use in data capture at the receiver. DQS is a strobe transmitted by the DDR SDRAM during Reads and by the memory controller during Writes. DQS is edgealigned with data for Reads and center-aligned with data for Writes. The 256Mb DDR SDRAM operates from a differential clock (CK and CK; the crossing of CK going high and CK going LOW is referred to as the positive edge of CK). Commands (address and control signals) are registered at every positive edge of CK. Input data is registered on both edges of DQS, and output data is referenced to both edges of DQS, as well as to both edges of CK. Read and write accesses to the DDR SDRAM are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an Active command, which is then followed by a Read or Write command. The address bits registered coincident with the Active command are used to select the bank and row to be accessed. The address bits registered coincident with the Read or Write command are used to select the bank and the starting column location for the burst access. The DDR SDRAM provides for programmable Read or Write burst lengths of 2, 4, or 8 locations. An Auto Precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst access. As with standard SDRAMs, the pipelined, multibank architecture of DDR SDRAMs allows for concurrent operation, thereby providing high effective bandwidth by hiding row precharge and activation time. An auto refresh mode is provided along with a power-saving Power Down mode. All inputs are compatible with the JEDEC Standard for SSTL_2. All outputs are SSTL_2, Class II compatible. The functionality described and the timing specifications included in this data sheet are for the DLL Enabled mode of operation. This synchronous DDR SDRAM device is manufactured using the advanced process and fab of Nanya Tehcnology Cor oration. p DOC # 14-02-044 Rev A ECN # 01-1116 The specifications of this device are subject to change without notice. For latest documentation, see http://www.nanoamp.com 1 NanoAmp Solutions, Inc. Ordering Information Speed Org. Part Number NT5DS64M4CT-5T 64M x 4 NT5DS64M4CT-6K NT5DS32M8CT-5T 32M x 8 NT5DS32M8CT-6K NT5DS16M16CT-5T 16M x 16 NT5DS16M16CT-6K NT5DS64M4CS-5T 64M x 4 NT5DS64M4CS-6K NT5DS32M8CS-5T 32M x 8 NT5DS32M8CS-6K NT5DS16M16CS-5T 16M x 16 NT5DS16M16CS-6K TSOP2 Green Packing NT5DS64M4CT, NT5DS32M8CT, NT5DS16M16CT NT5DS64M4CS, NT5DS32M8CS, NT5DS16M16CS Package Clock (MHz) CL-tRCD-tRP 200 TSOP2 166 200 TSOP2 166 200 TSOP2 166 200 166 200 166 200 166 2.5-3-3 3-3-3 2.5-3-3 3-3-3 2.5-3-3 3-3-3 2.5-3-3 2.5-3-3 3-3-3 2.5-3-3 3-3-3 3-3-3 Comments DDR400 DDR333 DDR400 DDR333 DDR400 DDR333 DDR400 DDR333 DDR400 DDR333 DDR400 DDR333 TSOP2 Green Packing TSOP2 Green Packing Note: 1. At the present time, there are no plans to support DDR SDRAMs with the QFC function. All reference to QFC are for information only Green Packing are Lead and Halogen free products DOC # 14-02-044 Rev A ECN # 01-1116 The specifications of this device are subject to change without notice. For latest documentation, see http://www.nanoamp.com 2 NanoAmp Solutions, Inc. Pin Configuration - 400mil TSOP II (x4 / x8 / x16) VDD NC VDDQ NC DQ0 VSSQ NC NC VDDQ NC DQ1 VSSQ NC NC VDDQ NC NC VDD NU NC WE CAS RAS CS NC BA0 BA1 A10/AP A0 A1 A2 A3 VDD VDD DQ0 VDDQ NC DQ1 VSSQ NC DQ2 VDDQ NC DQ3 VSSQ NC NC VDDQ NC NC VDD NU NC WE CAS RAS CS NC BA0 BA1 A10/AP A0 A1 A2 A3 VDD VDD DQ0 VDDQ DQ1 DQ2 VSSQ DQ3 DQ4 VDDQ DQ5 DQ6 VSSQ DQ7 NC VDDQ LDQS NC VDD NU LDM* WE CAS RAS CS NC BA0 BA1 A10/AP A0 A1 A2 A3 VDD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 NT5DS64M4CT, NT5DS32M8CT, NT5DS16M16CT NT5DS64M4CS, NT5DS32M8CS, NT5DS16M16CS 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 VSS DQ15 VSSQ DQ14 DQ13 VDDQ DQ12 DQ11 VSSQ DQ10 DQ9 VDDQ DQ8 NC VSSQ UDQS NC VREF VSS UDM* CK CK CKE NC A12 A11 A9 A8 A7 A6 A5 A4 VSS VSS DQ7 VSSQ NC DQ6 VDDQ NC DQ5 VSSQ NC DQ4 VDDQ NC NC VSSQ DQS NC VREF VSS DM* CK CK CKE NC A12 A11 A9 A8 A7 A6 A5 A4 VSS VSS NC VSSQ NC DQ3 VDDQ NC NC VSSQ NC DQ2 VDDQ NC NC VSSQ DQS NC VREF VSS DM* CK CK CKE NC A12 A11 A9 A8 A7 A6 A5 A4 VSS 66-pin Plastic TSOP-II 400mil 16Mb x 16 32Mb x 8 64Mb x 4 Column Address Table Organization 64Mb x 4 32Mb x 8 16Mb x 16 Column Address A0-A9, A11 A0-A9 A0-A8 *DM is internally loaded to match DQ and DQS identically. DOC # 14-02-044 Rev A ECN # 01-1116 The specifications of this device are subject to change without notice. For latest documentation, see http://www.nanoamp.com 3 NanoAmp Solutions, Inc. Input/Output Functional Description Symbol CK, CK Type Input NT5DS64M4CT, NT5DS32M8CT, NT5DS16M16CT NT5DS64M4CS, NT5DS32M8CS, NT5DS16M16CS Function Clock: CK and CK are differential clock inputs. All address and control input signals are sampled on the crossing of the positive edge of CK and negative edge of CK. Output (read) data is referenced to the crossings of CK and CK (both directions of crossing). Clock Enable: CKE HIGH activates, and CKE Low deactivates, internal clock signals and device input buffers and output drivers. Taking CKE Low provides Precharge Power Down and Self Refresh operation (all banks idle), or Active Power Down (row Active in any bank). CKE is synchronous for power down entry and exit, and for self refresh entry. CKE is asynchronous for self refresh exit. CKE must be maintained high throughout read and write accesses. Input buffers, excluding CK, CK and CKE are disabled during Power Down. Input buffers, excluding CKE, are disabled during self refresh. The standard pinout includes one CKE pin. Optional pinouts might include CKE1 on a different pin, in addition to CKE0, to facilitate independent power down control of stacked devices. Chip Select: All commands are masked when CS is registered high. CS provides for external bank selection on systems with multiple banks. CS is considered part of the command code. The standard pinout includes one CS pin. Optional pinouts might include CS1 on a different pin, in addition to CS0, to allow upper or lower deck selection on stacked devices. Command Inputs: RAS, CAS and WE (along with CS) define the command being entered. Input Data Mask: DM is an input mask signal for write data. Input data is masked when DM is sampled high coincident with that input data during a Write access. DM is sampled on both edges of DQS. Although DM pins are input only, the DM loading matches the DQ and DQS loading. During a Read, DM can be driven high, low, or floated. Bank Address Inputs: BA0 and BA1 define to which bank an Active, Read, Write or Precharge command is being applied. BA0 and BA1 also determines if the mode register or extended mode register is to be accessed during a MRS or EMRS cycle. Address Inputs: Provide the row address for Active commands, and the column address and Auto Precharge bit for Read/Write commands, to select one location out of the memory array in the respective bank. A10 is sampled during a Precharge command to determine whether the Precharge applies to one bank (A10 low) or all banks (A10 high). If only one bank is to be precharged, the bank is selected by BA0, BA1. The address inputs also provide the op-code during a Mode Register Set command. Data Input/Output: Data bus. Data Strobe: Output with read data, input with write data. Edge-aligned with read data, centered in write data. Used to capture write data. For the x16, LDQS corresponds to the data on DQ0DQ7; UDQS corresponds to the data on DQ8-DQ15 No Connect: No internal electrical connection is present. Electrical connection is present. Should not be connected at second level of assembly. CKE, CKE0, CKE1 Input CS, CS0, CS1 Input RAS, CAS, WE Input DM Input BA0, BA1 Input A0 - A12 Input DQ DQS, LDQS, UDQS NC NU VDDQ VSSQ VDD VSS VREF Input/Output Input/Output Supply Supply Supply Supply Supply DQ Power Supply: 2.5V ± 0.2V. DQ Ground Power Supply: 2.5V ± 0.2V. Ground SSTL_2 reference voltage: (VDDQ / 2) ± 1%. DOC # 14-02-044 Rev A ECN # 01-1116 The specifications of this device are subject to change without notice. For latest documentation, see http://www.nanoamp.com 4 NanoAmp Solutions, Inc. Block Diagram (64Mb x 4) NT5DS64M4CT, NT5DS32M8CT, NT5DS16M16CT NT5DS64M4CS, NT5DS32M8CS, NT5DS16M16CS Control Logic CKE CK CK CS WE CAS RAS Command Decode Bank1 Row-Address MUX Bank0 Row-Address Latch & Decoder Bank2 Bank3 CK, CK DLL Mode Registers 13 8192 Read Latch Refresh Counter 13 4 4 MUX 4 DQS Generator 1 Sense Amplifiers Bank Control Logic 8192 8 Drivers 15 13 Bank0 Memory Array (8192 x 1024 x 8) Data Address Register COL0 I/O Gating DM Mask Logic 1024 (x8) Column Decoder 10 8 8 Write FIFO & Drivers 2 2 8 4 4 4 4 clk clk out in Data CK, CK COL0 4 11 Column-Address Counter/Latch 1 COL0 1 Note: This Functional Block Diagram is intended to facilitate user understanding of the operation of the device; it does not represent an actual circuit implementation. Note: DM is a unidirectional signal (input only), but is internally loaded to match the load of the bidirectional DQ and DQS signals. Receivers A0-A12, BA0, BA1 2 15 Input Register 1 Mask 1 1 1 1 DQS DQ0-DQ3, DM DQS DOC # 14-02-044 Rev A ECN # 01-1116 The specifications of this device are subject to change without notice. For latest documentation, see http://www.nanoamp.com 5 NanoAmp Solutions, Inc. Block Diagram (32Mb x 8) NT5DS64M4CT, NT5DS32M8CT, NT5DS16M16CT NT5DS64M4CS, NT5DS32M8CS, NT5DS16M16CS Control Logic CKE CK CK CS WE CAS RAS Command Decode Bank1 Row-Address MUX Bank0 Row-Address Latch & Decoder Bank2 Bank3 CK, CK DLL Mode Registers 13 8192 Read Latch Refresh Counter 13 8 8 MUX 8 DQS Generator 1 Sense Amplifiers Bank Control Logic 8192 16 Drivers 15 13 Bank0 Memory Array (8192 x 512 x 16) Data Address Register COL0 I/O Gating DM Mask Logic 512 (x16) 2 16 2 16 8 8 8 Column Decoder 9 10 Column-Address Counter/Latch 1 COL0 8 clk clk out in Data CK, CK COL0 8 1 Note: This Functional Block Diagram is intended to facilitate user understanding of the operation of the device; it does not represent an actual circuit implementation. Note: DM is a unidirectional signal (input only), but is internally loaded to match the load of the bidirectional DQ and DQS signals. Receivers A0-A12, BA0, BA1 2 16 Write FIFO & Drivers 15 Input Register 1 Mask 1 1 1 1 DQS DQ0-DQ7, DM DQS DOC # 14-02-044 Rev A ECN # 01-1116 The specifications of this device are subject to change without notice. For latest documentation, see http://www.nanoamp.com 6 NanoAmp Solutions, Inc. Block Diagram (16Mb x 16) NT5DS64M4CT, NT5DS32M8CT, NT5DS16M16CT NT5DS64M4CS, NT5DS32M8CS, NT5DS16M16CS Control Logic CKE CK CK CS WE CAS RAS Command Decode Bank1 Row-Address MUX Bank0 Row-Address Latch & Decoder Bank2 Bank3 CK, CK DLL Mode Registers 13 8192 Read Latch Refresh Counter 13 16 16 MUX 16 DQS Generator 1 Sense Amplifiers Bank Control Logic 8192 32 Drivers 15 13 Bank0 Memory Array (8192 x 256 x 32) Data Address Register COL0 I/O Gating DM Mask Logic 256 (x32) 2 32 2 32 16 16 16 Column Decoder 8 9 Column-Address Counter/Latch 1 COL0 16 clk clk out in Data CK, CK COL0 16 1 Note: This Functional Block Diagram is intended to facilitate user understanding of the operation of the device; it does not represent an actual circuit implementation. Note: DM is a unidirectional signal (input only), but is internally loaded to match the load of the bidirectional DQ and DQS signals. Receivers A0-A12, BA0, BA1 2 32 Write FIFO & Drivers 15 Input Register 1 Mask 1 1 1 1 DQS DQ0-DQ15, LDM, UDM LDQS,UDQS DOC # 14-02-044 Rev A ECN # 01-1116 The specifications of this device are subject to change without notice. For latest documentation, see http://www.nanoamp.com 7 NanoAmp Solutions, Inc. Functional Description NT5DS64M4CT, NT5DS32M8CT, NT5DS16M16CT NT5DS64M4CS, NT5DS32M8CS, NT5DS16M16CS The 256Mb DDR SDRAM is a high-speed CMOS, dynamic random-access memory containing 268, 435, 456 bits. The 256Mb DDR SDRAM is internally configured as a quad-bank DRAM. The 256Mb DDR SDRAM uses a double-data-rate architecture to achieve high-speed operation. The double-data-rate architecture is essentially a 2n prefetch architecture, with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write access for the 256Mb DDR SDRAM consists of a single 2n-bit wide, one clock cycle data transfer at the internal DRAM core and two corresponding n-bit wide, one-half clock cycle data transfers at the I/O pins. Read and write accesses to the DDR SDRAM are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an Active command, which is then followed by a Read or Write command. The address bits registered coincident with the Active command are used to select the bank and row to be accessed (BA0, BA1 select the bank; A0-A12 select the row). The address bits registered coincident with the Read or Write command are used to select the starting column location for the burst access. Prior to normal operation, the DDR SDRAM must be initialized. The following sections provide detailed information covering device initialization, register definition, command descriptions and device operation. Initialization Only one of the following two conditions must be met. • No power sequencing is specified during power up or power down given the following criteria: VDD and VDDQ are driven from a single power converter output VTT meets the specification A minimum resistance of 42 ohms limits the input current from the VTT supply into any pin and VREF tracks VDDQ /2 or • The following relationships must be followed: VDDQ is driven after or with VDD such that VDDQ < VDD + 0.3V VTT is driven after or with VDDQ such that VTT < VDDQ + 0.3V VREF is driven after or with VDDQ such that VREF < VDDQ + 0.3V The DQ and DQS outputs are in the High-Z state, where they remain until driven in normal operation (by a read access). After all power supply and reference voltages are stable, and the clock is stable, the DDR SDRAM requires a 200µs delay prior to applying an executable command. Once the 200µs delay has been satisfied, a Deselect or NOP command should be applied, and CKE must be brought HIGH. Following the NOP command, a Precharge ALL command must be applied. Next a Mode Register Set command must be issued for the Extended Mode Register, to enable the DLL, then a Mode Register Set command must be issued for the Mode Register, to reset the DLL, and to program the operating parameters. 200 clock cycles are required between the DLL reset and any read command. A Precharge ALL command should be applied, placing the device in the “all banks idle” state Once in the idle state, two auto refresh cycles must be performed. Additionally, a Mode Register Set command for the Mode Register, with the reset DLL bit deactivated (i.e. to program operating parameters without resetting the DLL) must be performed. Following these cycles, the DDR SDRAM is ready for normal operation. DDR SDRAM’s may be reinitialized at any time during normal operation by asserting a valid MRS command to either the base or extended mode registers without affecting the contents of the memory array. The contents of either the mode register or extended mode register can be modified at any valid time during device operation without affecting the state of the internal address refresh counters used for device refresh. DOC # 14-02-044 Rev A ECN # 01-1116 The specifications of this device are subject to change without notice. For latest documentation, see http://www.nanoamp.com 8 NanoAmp Solutions, Inc. Register Definition Mode Register NT5DS64M4CT, NT5DS32M8CT, NT5DS16M16CT NT5DS64M4CS, NT5DS32M8CS, NT5DS16M16CS The Mode Register is used to define the specific mode of operation of the DDR SDRAM. This definition includes the selection of a burst length, a burst type, a CAS latency, and an operating mode. The Mode Register is programmed via the Mode Register Set command (with BA0 = 0 and BA1 = 0) and retains the stored information until it is programmed again or the device loses power (except for bit A8, which is self-clearing). Mode Register bits A0-A2 specify the burst length, A3 specifies the type of burst (sequential or interleaved), A4-A6 specify the CAS latency, and A7-A12 specify the operating mode. The Mode Register must be loaded when all banks are idle, and the controller must wait the specified time before initiating the subsequent operation. Violating either of these requirements results in unspecified operation. Burst Length Read and write accesses to the DDR SDRAM are burst oriented, with the burst length being programmable. The burst length determines the maximum number of column locations that can be accessed for a given Read or Write command. Burst lengths of 2, 4, or 8 locations are available for both the sequential and the interleaved burst types. Reserved states should not be used, as unknown operation or incompatibility with future versions may result. When a Read or Write command is issued, a block of columns equal to the burst length is effectively selected. All accesses for that burst take place within this block, meaning that the burst wraps within the block if a boundary is reached. The block is uniquely selected by A1-Ai when the burst length is set to two, by A2-Ai when the burst length is set to four and by A3-Ai when the burst length is set to eight (where Ai is the most significant column address bit for a given configuration). The remaining (least significant) address bit(s) is (are) used to select the starting location within the block. The programmed burst length applies to both Read and Write bursts. DOC # 14-02-044 Rev A ECN # 01-1116 The specifications of this device are subject to change without notice. For latest documentation, see http://www.nanoamp.com 9 NanoAmp Solutions, Inc. Mode Register Operation BA1 0* BA0 0* A12 A11 A10 A9 A8 A7 A6 A5 NT5DS64M4CT, NT5DS32M8CT, NT5DS16M16CT NT5DS64M4CS, NT5DS32M8CS, NT5DS16M16CS A4 A3 BT A2 A1 A0 Address Bus Mode Register Operating Mode CAS Latency Burst Length A12 - A9 0 0 0 A8 0 1 0 A7 0 0 1 A6 - A0 Valid Valid VS** Operating Mode Normal operation Do not reset DLL Normal operation in DLL Reset Vendor-Specific Test Mode Reserved A3 0 1 Burst Type Sequential Interleave − − − CAS Latency A6 0 0 0 0 1 1 1 1 A5 0 0 1 1 0 0 1 1 A4 0 1 0 1 0 1 0 1 Latency Reserved Reserved 2 3 (Option) Reserved 1.5 (Option) 2.5 Reserved A2 0 0 0 0 1 1 1 1 A1 0 0 1 1 0 0 1 1 Burst Length A0 0 1 0 1 0 1 0 1 Burst Length Reserved 2 4 8 Reserved Reserved Reserved Reserved VS** Vendor Specific * BA0 and BA1 must be 0, 0 to select the Mode Register (vs. the Extended Mode Register). DOC # 14-02-044 Rev A ECN # 01-1116 The specifications of this device are subject to change without notice. For latest documentation, see http://www.nanoamp.com 10 NanoAmp Solutions, Inc. Burst Definition Starting Column Address Burst Length A2 2 0 0 4 1 1 0 0 0 0 8 1 1 1 1 0 0 1 1 0 0 1 1 A1 A0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 NT5DS64M4CT, NT5DS32M8CT, NT5DS16M16CT NT5DS64M4CS, NT5DS32M8CS, NT5DS16M16CS Order of Accesses Within a Burst Type = Sequential 0-1 1-0 0-1-2-3 1-2-3-0 2-3-0-1 3-0-1-2 0-1-2-3-4-5-6-7 1-2-3-4-5-6-7-0 2-3-4-5-6-7-0-1 3-4-5-6-7-0-1-2 4-5-6-7-0-1-2-3 5-6-7-0-1-2-3-4 6-7-0-1-2-3-4-5 7-0-1-2-3-4-5-6 Type = Interleaved 0-1 1-0 0-1-2-3 1-0-3-2 2-3-0-1 3-2-1-0 0-1-2-3-4-5-6-7 1-0-3-2-5-4-7-6 2-3-0-1-6-7-4-5 3-2-1-0-7-6-5-4 4-5-6-7-0-1-2-3 5-4-7-6-1-0-3-2 6-7-4-5-2-3-0-1 7-6-5-4-3-2-1-0 Notes: 1. For a burst length of two, A1-A i selects the two-data-element block; A0 selects the first access within the block. 2. For a burst length of four, A2-A i selects the four-data-element block; A0-A1 selects the first access within the block. 3. For a burst length of eight, A3-A i selects the eight-data- element block; A0-A2 selects the first access within the block. 4. Whenever a boundary of the block is reached within a given sequence above, the following access wraps within the block. Burst Type Accesses within a given burst may be programmed to be either sequential or interleaved; this is referred to as the burst type and is selected via bit A3. The ordering of accesses within a burst is determined by the burst length, the burst type and the starting column address, as shown in Burst Definition on page 11. Read Latency The Read latency, or CAS latency, is the delay, in clock cycles, between the registration of a Read command and the availability of the first burst of output data. The latency can be programmed 2 or 2.5 clocks. If a Read command is registered at clock edge n, and the latency is m clocks, the data is available nominally coincident with clock edge n + m. Reserved states should not be used as unknown operation or incompatibility with future versions may result. DOC # 14-02-044 Rev A ECN # 01-1116 The specifications of this device are subject to change without notice. For latest documentation, see http://www.nanoamp.com 11 NanoAmp Solutions, Inc. Operating Mode NT5DS64M4CT, NT5DS32M8CT, NT5DS16M16CT NT5DS64M4CS, NT5DS32M8CS, NT5DS16M16CS The normal operating mode is selected by issuing a Mode Register Set Command with bits A7-A12 to zero, and bits A0-A6 set to the desired values. A DLL reset is initiated by issuing a Mode Register Set command with bits A7 and A9-A12 each set to zero, bit A8 set to one, and bits A0-A6 set to the desired values. A Mode Register Set command issued to reset the DLL should always be followed by a Mode Register Set command to select normal operating mode. All other combinations of values for A7-A12 are reserved for future use and/or test modes. Test modes and reserved states should not be used as unknown operation or incompatibility with future versions may result. CAS Latencies CAS Latency = 2, BL = 4 CK CK Command Read NOP CL=2 DQS DQ NOP NOP NOP NOP CAS Latency = 2.5, BL = 4 CK CK Command Read NOP CL=2.5 DQS DQ NOP NOP NOP NOP Shown with nominal tAC, tDQSCK, and tDQSQ. Don’t Care DOC # 14-02-044 Rev A ECN # 01-1116 The specifications of this device are subject to change without notice. For latest documentation, see http://www.nanoamp.com 12 NanoAmp Solutions, Inc. Extended Mode Register NT5DS64M4CT, NT5DS32M8CT, NT5DS16M16CT NT5DS64M4CS, NT5DS32M8CS, NT5DS16M16CS The Extended Mode Register controls functions beyond those controlled by the Mode Register; these additional functions include DLL enable/disable, bit A0; output drive strength selection, bit A1; and QFC output enable/disable, bit A2 (optional). These functions are controlled via the bit settings shown in the Extended Mode Register Definition. The Extended Mode Register is programmed via the Mode Register Set command (with BA0 = 1 and BA1 = 0) and retains the stored information until it is programmed again or the device loses power. The Extended Mode Register must be loaded when all banks are idle, and the controller must wait the specified time before initiating any subsequent operation. Violating either of these requirements result in unspecified operation. DLL Enable/Disable The DLL must be enabled for normal operation. DLL enable is required during power up initialization, and upon returning to normal operation after having disabled the DLL for the purpose of debug or evaluation. The DLL is automatically disabled when entering self refresh operation and is automatically re-enabled upon exit of self refresh operation. Any time the DLL is enabled, 200 clock cycles must occur to allow time for the internal clock to lock to the externally applied clock before a Read command can be issued. This is the reason for introducing timing parameter tXSRD for DDR SDRAM’s (Exit Self Refresh to Read Command). Non- Read commands can be issued 2 clocks after the DLL is enabled via the EMRS command (tMRD) or 10 clocks after the DLL is enabled via self refresh exit command (tXSNR, Exit Self Refresh to Non-Read Command). Output Drive Strength The normal drive strength for all outputs is specified to be SSTL_2, Class II. QFC Enable/Disable The QFC signal is an optional DRAM output control used to isolate module loads (DIMMs) from the system memory bus by means of external FET switches when the given module (DIMM) is not being accessed. The QFC function is an optional feature and is not included on all DDR SDRAM devices. DOC # 14-02-044 Rev A ECN # 01-1116 The specifications of this device are subject to change without notice. For latest documentation, see http://www.nanoamp.com 13 NanoAmp Solutions, Inc. Extended Mode Register Definition BA1 0* BA0 1* A12 A11 A10 A9 A8 A7 A6 A5 NT5DS64M4CT, NT5DS32M8CT, NT5DS16M16CT NT5DS64M4CS, NT5DS32M8CS, NT5DS16M16CS A4 A3 A2 QFC A1 DS A0 DLL Address Bus Extended Mode Register Operating Mode Drive Strength A12 - A3 0 A2 - A0 Valid Operating Mode Normal Operation All other states Reserved 0 1 Normal Reserved A1 Drive Strength − − A2 0 1 QFC Disable Enable (Optional) A0 0 DLL Enable Disable * BA0 and BA1 must be 1, 0 to select the Extended Mode Register (vs. the base Mode Register) 1 DOC # 14-02-044 Rev A ECN # 01-1116 The specifications of this device are subject to change without notice. For latest documentation, see http://www.nanoamp.com 14 NanoAmp Solutions, Inc. Commands NT5DS64M4CT, NT5DS32M8CT, NT5DS16M16CT NT5DS64M4CS, NT5DS32M8CS, NT5DS16M16CS Truth Tables 1a and 1b provide a reference of the commands supported by DDR SDRAM devices. A verbal description of each commands follows. Truth Table 1a: Commands Name (Function) Deselect (Nop) No Operation (Nop) Active (Select Bank And Activate Row) Read (Select Bank And Column, And Start Read Burst) Write (Select Bank And Column, And Start Write Burst) Burst Terminate Precharge (Deactivate Row In Bank Or Banks) Auto Refresh Or Self Refresh (Enter Self Refresh Mode) Mode Register Set CS H L L L L L L L L RAS X H L H H H L L L CAS X H H L L H H L L WE X H H H L L L H L Address X X Bank/Row Bank/Col Bank/Col X Code X Op-Code MNE NOP NOP ACT Read Write BST PRE AR / SR MRS Notes 1, 9 1, 9 1, 3 1, 4 1, 4 1, 8 1, 5 1, 6, 7 1, 2 1. CKE is high for all commands shown except Self Refresh. 2. BA0, BA1 select either the Base or the Extended Mode Register (BA0 = 0, BA1 = 0 selects Mode Register; BA0 = 1, BA1 = 0 selects Extended Mode Register; other combinations of BA0-BA1 are reserved; A0-A12 provide the op-code to be written to the selected Mode Register.) 3. BA0-BA1 provide bank address and A0-A12 provide row address. 4. BA0, BA1 provide bank address; A0-Ai provide column address (where i = 9 for x8 and 9, 11 for x4); A10 high enables the Auto Precharge feature (non-persistent), A10 low disables the Auto Precharge feature. 5. A10 LOW: BA0, BA1 determine which bank is precharged. A10 HIGH: all banks are precharged and BA0, BA1 are “Don’t Care.” 6. This command is auto refresh if CKE is high; Self Refresh if CKE is low. 7. Internal refresh counter controls row and bank addressing; all inputs and I/Os are “Don’t Care” except for CKE. 8. Applies only to read bursts with Auto Precharge disabled; this command is undefined (and should not be used) for read bursts with Auto Precharge enabled or for write bursts 9. Deselect and NOP are functionally interchangeable. Truth Table 1b: DM Operation Name (Function) Write Enable Write Inhibit 1. Used to mask write data; provided coincident with the corresponding data. DM L H DQs Valid X Notes 1 1 DOC # 14-02-044 Rev A ECN # 01-1116 The specifications of this device are subject to change without notice. For latest documentation, see http://www.nanoamp.com 15 NanoAmp Solutions, Inc. Deselect NT5DS64M4CT, NT5DS32M8CT, NT5DS16M16CT NT5DS64M4CS, NT5DS32M8CS, NT5DS16M16CS The Deselect function prevents new commands from being executed by the DDR SDRAM. The DDR SDRAM is effectively deselected. Operations already in progress are not affected. No Operation (NOP) The No Operation (NOP) command is used to perform a NOP to a DDR SDRAM. This prevents unwanted commands from being registered during idle or wait states. Operations already in progress are not affected. Mode Register Set The mode registers are loaded via inputs A0-A12, BA0 and BA1 while issuing the Mode Register Set Command. See mode register descriptions in the Register Definition section. The Mode Register Set command can only be issued when all banks are idle and no bursts are in progress. A subsequent executable command cannot be issued until tMRD is met. Active The Active command is used to open (or activate) a row in a particular bank for a subsequent access. The value on the BA0, BA1 inputs selects the bank, and the address provided on inputs A0-A12 selects the row. This row remains active (or open) for accesses until a Precharge (or Read or Write with Auto Precharge) is issued to that bank. A Precharge (or Read or Write with Auto Precharge) command must be issued and completed before opening a different row in the same bank. Read The Read command is used to initiate a burst read access to an active (open) row. The value on the BA0, BA1 inputs selects the bank, and the address provided on inputs A0-Ai, Aj (where [i = 9, j = don’t care] for x8; where [i = 9, j = 11] for x4) selects the starting column location. The value on input A10 determines whether or not Auto Precharge is used. If Auto Precharge is selected, the row being accessed is precharged at the end of the Read burst; if Auto Precharge is not selected, the row remains open for subsequent accesses. Write The Write command is used to initiate a burst write access to an active (open) row. The value on the BA0, BA1 inputs selects the bank, and the address provided on inputs A0-Ai, Aj (where [i = 9, j = don’t care] for x8; where [i = 9, j = 11] for x4) selects the starting column location. The value on input A10 determines whether or not Auto Precharge is used. If Auto Precharge is selected, the row being accessed is precharged at the end of the Write burst; if Auto Precharge is not selected, the row remains open for subsequent accesses. Input data appearing on the DQs is written to the memory array subject to the DM input logic level appearing coincident with the data. If a given DM signal is registered low, the corresponding data is written to memory; if the DM signal is registered high, the corresponding data inputs are ignored, and a Write is not executed to that byte/column location. Precharge The Precharge command is used to deactivate (close) the open row in a particular bank or the open row(s) in all banks. The bank(s) will be available for a subsequent row access a specified time (tRP) after the Precharge command is issued. Input A10 determines whether one or all banks are to be precharged, and in the case where only one bank is to be precharged, inputs BA0, BA1 select the bank. Otherwise BA0, BA1 are treated as “Don’t Care.” Once a bank has been precharged, it is in the idle state and must be activated prior to any Read or Write commands being issued to that bank. A precharge command is treated as a NOP if there is no open row in that bank, or if the previously open row is already in the process of precharging. DOC # 14-02-044 Rev A ECN # 01-1116 The specifications of this device are subject to change without notice. For latest documentation, see http://www.nanoamp.com 16 NanoAmp Solutions, Inc. Auto Precharge NT5DS64M4CT, NT5DS32M8CT, NT5DS16M16CT NT5DS64M4CS, NT5DS32M8CS, NT5DS16M16CS Auto Precharge is a feature which performs the same individual-bank precharge function described above, but without requiring an explicit command. This is accomplished by using A10 to enable Auto Precharge in conjunction with a specific Read or Write command. A precharge of the bank/row that is addressed with the Read or Write command is automatically performed upon completion of the Read or Write burst. Auto Precharge is non-persistent in that it is either enabled or disabled for each individual Read or Write command. Auto Precharge ensures that the precharge is initiated at the earliest valid stage within a burst. This is determined as if an explicit Precharge command was issued at the earliest possible time without violating tRAS(min). The user must not issue another command to the same bank until the precharge (tRP) is completed. The DDR SDRAM devices supports the optional t RAS lockout feature. This feature allows a Read command with Auto Precharge to be issued to a bank that has been activated (opened) but has not yet satisfied the tRAS(min) specification. The tRAS lockout feature essentially delays the onset of the auto precharge operation until two conditions occur. One, the entire burst length of data has been successfully prefetched from the memory array; and two, tRAS(min) has been satisfied. As a means to specify whether a DDR SDRAM device supports the tRAS lockout feature, a new parameter has been defined, tRAP (RAS Command to Read Command with Auto Precharge or better stated Bank Activate to Read Command with Auto Precharge). For devices that support the tRAS lockout feature, tRAP = tRCD(min). This allows any Read Command (with or without Auto Precharge) to be issued to an open bank once tRCD(min) is satisfied. tRAP Definition CL=2, tCK=10ns CK CK Command DQ (BL=2) tRASmin Command DQ (BL=4) NOP ACT NOP RD A NOP NOP DQ0 NOP ACT NOP RD A NOP NOP DQ0 NOP DQ1 NOP ACT NOP NOP * DQ1 tRPmin NOP DQ3 ACT NOP NOP NOP DQ2 Command DQ (BL=8) NOP ACT NOP RD A NOP NOP DQ0 * DQ1 tRPmin NOP DQ3 DQ4 NOP DQ5 DQ6 ACT DQ7 NOP NOP DQ2 tRCDmin tRAPmin The above timing diagrams show the effects of tRAP for devices that support tRAS lockout. In these cases, the Read with Auto Precharge command (RDA) is issued with tRCD(min) and dataout is available with the shortest latency from the Bank Activate command (ACT). The internal precharge operation, however, does not begin until after tRAS(min) is satisfied. * * tRPmin Indicates Auto Precharge begins here Burst Terminate The Burst Terminate command is used to truncate read bursts (with Auto Precharge disabled). The most re-cently registered Read command prior to the Burst Terminate command is truncated, as shown in the Operation section of this data sheet. Write burst cycles are not to be terminated with the Burst Terminate command. DOC # 14-02-044 Rev A ECN # 01-1116 The specifications of this device are subject to change without notice. For latest documentation, see http://www.nanoamp.com 17 NanoAmp Solutions, Inc. Auto Refresh NT5DS64M4CT, NT5DS32M8CT, NT5DS16M16CT NT5DS64M4CS, NT5DS32M8CS, NT5DS16M16CS Auto Refresh is used during normal operation of the DDR SDRAM and is analogous to CAS Before RAS (CBR) Refresh in previous DRAM types. This command is nonpersistent, so it must be issued each time a refresh is required. The refresh addressing is generated by the internal refresh controller. This makes the address bits “Don’t Care” during an Auto Refresh command. The 256Mb DDR SDRAM requires Auto Refresh cycles at an average periodic interval of 7.8µs (maximum). Self Refresh The Self Refresh command can be used to retain data in the DDR SDRAM, even if the rest of the system is powered down. When in the self refresh mode, the DDR SDRAM retains data without external clocking. The Self Refresh command is initiated as an Auto Refresh command coincident with CKE transitioning low. The DLL is automatically disabled upon entering Self Refresh, and is automatically enabled upon exiting Self Refresh (200 clock cycles must then occur before a Read command can be issued). Input signals except CKE (low) are “Don’t Care” during Self Refresh operation. The procedure for exiting self refresh requires a sequence of commands. CK (and CK) must be stable prior to CKE returning high. Once CKE is high, the SDRAM must have NOP commands issued for tXSNR because time is required for the completion of any internal refresh in progress. A simple algorithm for meeting both refresh and DLL requirements is to apply NOPs for 200 clock cycles before applying any other command. DOC # 14-02-044 Rev A ECN # 01-1116 The specifications of this device are subject to change without notice. For latest documentation, see http://www.nanoamp.com 18 NanoAmp Solutions, Inc. Operations Bank/Row Activation NT5DS64M4CT, NT5DS32M8CT, NT5DS16M16CT NT5DS64M4CS, NT5DS32M8CS, NT5DS16M16CS Before any Read or Write commands can be issued to a bank within the DDR SDRAM, a row in that bank must be “opened” (activated). This is accomplished via the Active command and addresses A0-A12, BA0 and BA1 (see Activating a Specific Row in a Specific Bank), which decode and select both the bank and the row to be activated. After opening a row (issuing an Active command), a Read or Write command may be issued to that row, subject to the tRCD specification. A subsequent Active command to a different row in the same bank can only be issued after the previous active row has been “closed” (precharged). The minimum time interval between successive Active commands to the same bank is defined by tRC. A subsequent Active command to another bank can be issued while the first bank is being accessed, which results in a reduction of total row-access overhead. The minimum time interval between successive Active commands to different banks is defined by tRRD. Activating a Specific Row in a Specific Bank CK CK CKE CS RAS CAS WE A0-A12 BA0, BA1 RA BA RA = row address. BA = bank address. Don’t Care HIGH DOC # 14-02-044 Rev A ECN # 01-1116 The specifications of this device are subject to change without notice. For latest documentation, see http://www.nanoamp.com 19 NanoAmp Solutions, Inc. tRCD and tRRD Definition CK CK Command A0-A12 BA0, BA1 ACT ROW BA x NOP ACT ROW BA y NOP NT5DS64M4CT, NT5DS32M8CT, NT5DS16M16CT NT5DS64M4CS, NT5DS32M8CS, NT5DS16M16CS NOP RD/WR COL BA y NOP NOP tRRD tRCD Don’t Care Reads Subsequent to programming the mode register with CAS latency, burst type, and burst length, Read bursts are initiated with a Read command. The starting column and bank addresses are provided with the Read command and Auto Precharge is either enabled or disabled for that burst access. If Auto Precharge is enabled, the row that is accessed starts precharge at the completion of the burst, provided tRAS has been satisfied. For the generic Read commands used in the following illustrations, Auto Precharge is disabled. During Read bursts, the valid data-out element from the starting column address is available following the CAS latency after the Read command. Each subsequent data-out element is valid nominally at the next positive or negative clock edge (i.e. at the next crossing of CK and CK). The following timing figure entitled “Read Burst: CAS Latencies (Burst Length=4)” illustrates the general timing for each supported CAS latency setting. DQS is driven by the DDR SDRAM along with output data. The initial low state on DQS is known as the read preamble; the low state coincident with the last data-out element is known as the read postamble. Upon completion of a burst, assuming no other commands have been initiated, the DQs and DQS goes High-Z. Data from any Read burst may be concatenated with or truncated with data from a subsequent Read command. In either case, a continuous flow of data can be maintained. The first data element from the new burst follows either the last element of a completed burst or the last desired data element of a longer burst which is being truncated. The new Read command should be issued x cycles after the first Read command, where x equals the number of desired data element pairs (pairs are required by the 2n prefetch architecture). This is shown in timing figure entitled “Consecutive Read Bursts: CAS Latencies (Burst Length =4 or 8)”. A Read command can be initiated on any positive clock cycle following a previous Read command. Nonconsecutive Read data is shown in timing figure entitled “Non-Consecutive Read Bursts: CAS Latencies (Burst Length = 4)”. Full-speed Random Read Accesses: CAS Latencies (Burst Length = 2, 4 or 8) within a page (or pages) can be performed as shown on page 25. DOC # 14-02-044 Rev A ECN # 01-1116 The specifications of this device are subject to change without notice. For latest documentation, see http://www.nanoamp.com 20 NanoAmp Solutions, Inc. Read Command NT5DS64M4CT, NT5DS32M8CT, NT5DS16M16CT NT5DS64M4CS, NT5DS32M8CS, NT5DS16M16CS CK CK CKE CS RAS CAS WE x4: A0-A9, A11 x8: A0-A9 A10 DIS AP BA0, BA1 BA CA = column address BA = bank address EN AP = enable Auto Precharge DIS AP = disable Auto Precharge Don’t Care HIGH CA EN AP DOC # 14-02-044 Rev A ECN # 01-1116 The specifications of this device are subject to change without notice. For latest documentation, see http://www.nanoamp.com 21 NanoAmp Solutions, Inc. Read Burst: CAS Latencies (Burst Length = 4) NT5DS64M4CT, NT5DS32M8CT, NT5DS16M16CT NT5DS64M4CS, NT5DS32M8CS, NT5DS16M16CS CAS Latency = 2 CK CK Command Address Read BA a,COL n NOP NOP NOP NOP NOP CL=2 DQS DQ tQCS QFC (Optional) DOa-n tQCH CAS Latency = 2.5 CK CK Command Address Read BA a,COL n NOP NOP NOP NOP NOP CL=2.5 DQS DQ DOa-n QFC (Optional) tQCS tQCH Don’t Care DO a-n = data out from bank a, column n. 3 subsequent elements of data out appear in the programmed order following DO a-n. Shown with nominal tAC, tDQSCK, and tDQSQ. QFC is an open drain driver. The output high level is achieved through an external pull up resistor connected to VDDQ. DOC # 14-02-044 Rev A ECN # 01-1116 The specifications of this device are subject to change without notice. For latest documentation, see http://www.nanoamp.com 22 NanoAmp Solutions, Inc. NT5DS64M4CT, NT5DS32M8CT, NT5DS16M16CT NT5DS64M4CS, NT5DS32M8CS, NT5DS16M16CS Consecutive Read Bursts: CAS Latencies (Burst Length = 4 or 8) CAS Latency = 2 CK CK Command Address Read NOP Read NOP NOP NOP BAa, COL n BAa, COL b CL=2 DQS DQ DOa-n DOa-b CAS Latency = 2.5 CK CK Command Address Read BAa, COL n NOP Read BAa,COL b NOP NOP NOP CL=2.5 DQS DQ DOa- n DOa- b DO a-n (or a-b) = data out from bank a, column n (or bank a, column b). When burst length = 4, the bursts are concatenated. When burst length = 8, the second burst interrupts the first. 3 subsequent elements of data out appear in the programmed order following DO a-n. 3 (or 7) subsequent elements of data out appear in the programmed order following DO a-b. Shown with nominal tAC, tDQSCK, and tDQSQ. Don’t Care DOC # 14-02-044 Rev A ECN # 01-1116 The specifications of this device are subject to change without notice. For latest documentation, see http://www.nanoamp.com 23 NanoAmp Solutions, Inc. NT5DS64M4CT, NT5DS32M8CT, NT5DS16M16CT NT5DS64M4CS, NT5DS32M8CS, NT5DS16M16CS Non-Consecutive Read Bursts: CAS Latencies (Burst Length = 4) CAS Latency = 2 CK CK Command Address Read BAa, COL n NOP NOP Read BAa, COL b NOP NOP CL=2 DQS DQ DO a-n DOa- b CAS Latency = 2.5 CK CK Command Address Read BAa, COL n NOP NOP Read BAa, COL b NOP NOP NOP CL=2.5 DQS DQ DO a-n DOa- b DO a-n (or a-b) = data out from bank a, column n (or bank a, column b). 3 subsequent elements of data out appear in the programmed order following DO a-n (and following DO a-b). Shown with nominal tAC, tDQSCK, and tDQSQ. Don’t Care DOC # 14-02-044 Rev A ECN # 01-1116 The specifications of this device are subject to change without notice. For latest documentation, see http://www.nanoamp.com 24 NanoAmp Solutions, Inc. NT5DS64M4CT, NT5DS32M8CT, NT5DS16M16CT NT5DS64M4CS, NT5DS32M8CS, NT5DS16M16CS Random Read Accesses: CAS Latencies (Burst Length = 2, 4 or 8) CAS Latency = 2 CK CK Command Address Read BAa, COL n Read BAa, COL x Read BAa, COL b Read BAa, COL g NOP NOP CL=2 DQS DQ DOa-n DOa-n' DOa-x DOa-x' DOa-b DOa-b’ DOa-g CAS Latency = 2.5 CK CK Command Address Read Read Read Read NOP NOP BAa, COL n BAa, COL x BAa, COL b BAa, COL g CL=2.5 DQS DQ DOa-n DOa-n' DOa-x DOa-x' DOa-b DOa-b’ DO a-n, etc. = data out from bank a, column n etc. n' etc. = odd or even complement of n, etc. (i.e., column address LSB inverted). Reads are to active rows in any banks. Shown with nominal tAC, tDQSCK, and tDQSQ. Don’t Care DOC # 14-02-044 Rev A ECN # 01-1116 The specifications of this device are subject to change without notice. For latest documentation, see http://www.nanoamp.com 25 NanoAmp Solutions, Inc. NT5DS64M4CT, NT5DS32M8CT, NT5DS16M16CT NT5DS64M4CS, NT5DS32M8CS, NT5DS16M16CS Data from any Read burst may be truncated with a Burst Terminate command, as shown in timing figure entitled Terminating a Read Burst: CAS Latencies (Burst Length = 8) on page 27. The Burst Terminate latency is equal to the read (CAS) latency, i.e. the Burst Terminate command should be issued x cycles after the Read command, where x equals the number of desired data element pairs. Data from any Read burst must be completed or truncated before a subsequent Write command can be issued. If truncation is necessary, the Burst Terminate command must be used, as shown in timing figure entitled Read to Write: CAS Latencies (Burst Length = 4 or 8) on page 28. The example is shown for tDQSS(min). The tDQSS(max) case, not shown here, has a longer bus idle time. tDQSS(min) and tDQSS(max) are defined in the section on Writes. A Read burst may be followed by, or truncated with, a Precharge command to the same bank (provided that Auto Precharge was not activated). The Precharge command should be issued x cycles after the Read command, where x equals the number of desired data element pairs (pairs are required by the 2n prefetch architecture). This is shown in timing figure Read to Precharge: CAS Latencies (Burst Length = 4 or 8) on page 29 for Read latencies of 2 and 2.5. Following the Precharge command, a subsequent command to the same bank cannot be issued until tRP is met. Note that part of the row precharge time is hidden during the access of the last data elements. In the case of a Read being executed to completion, a Precharge command issued at the optimum time (as described above) provides the same operation that would result from the same Read burst with Auto Precharge enabled. The disadvantage of the Precharge command is that it requires that the command and address busses be available at the appropriate time to issue the command. The advantage of the Precharge command is that it can be used to truncate bursts. DOC # 14-02-044 Rev A ECN # 01-1116 The specifications of this device are subject to change without notice. For latest documentation, see http://www.nanoamp.com 26 NanoAmp Solutions, Inc. NT5DS64M4CT, NT5DS32M8CT, NT5DS16M16CT NT5DS64M4CS, NT5DS32M8CS, NT5DS16M16CS Terminating a Read Burst: CAS Latencies (Burst Length = 8) CAS Latency = 2 CK CK Command Address Read BAa, COL n NOP BST NOP NOP NOP CL=2 DQS DQ DOa-n No further output data after this point. DQS tristated. CAS Latency = 2.5 CK CK Command Address Read BAa, COL n NOP BST NOP NOP NOP CL=2.5 DQS DQ DOa-n No further output data after this point. DQS tristated. DO a-n = data out from bank a, column n. Cases shown are bursts of 8 terminated after 4 data elements. 3 subsequent elements of data out appear in the programmed order following DO a-n. Shown with nominal tAC, tDQSCK, and tDQSQ. Don’t Care DOC # 14-02-044 Rev A ECN # 01-1116 The specifications of this device are subject to change without notice. For latest documentation, see http://www.nanoamp.com 27 NanoAmp Solutions, Inc. NT5DS64M4CT, NT5DS32M8CT, NT5DS16M16CT NT5DS64M4CS, NT5DS32M8CS, NT5DS16M16CS Read to Write: CAS Latencies (Burst Length = 4 or 8) CAS Latency = 2 CK CK Command Address Read BAa, COL n BST NOP Write BAa, COL b NOP NOP CL=2 DQS DQ DM DOa-n tDQSS (min) DI a-b CAS Latency = 2.5 CK CK Command Address Read BAa, COL n BST NOP NOP Write BAa, COL b NOP CL=2.5 DQS DQ DM DOa-n tDQSS (min) Dla-b DO a-n = data out from bank a, column n . a-b = data in to bank a, column b DI 1 subsequent elements of data out appear in the programmed order following DO a-n. Data In elements are applied following Dl a-b in the programmed order, according to burst length. Shown with nominal tAC, tDQSCK, and tDQSQ. Don’t Care DOC # 14-02-044 Rev A ECN # 01-1116 The specifications of this device are subject to change without notice. For latest documentation, see http://www.nanoamp.com 28 NanoAmp Solutions, Inc. NT5DS64M4CT, NT5DS32M8CT, NT5DS16M16CT NT5DS64M4CS, NT5DS32M8CS, NT5DS16M16CS Read to Precharge: CAS Latencies (Burst Length = 4 or 8) CAS Latency = 2 CK CK Command Read NOP PRE NOP NOP ACT tRP Address BA a, COL n BA a or all BA a, ROW CL=2 DQS DQ DOa-n CAS Latency = 2.5 CK CK Command Read NOP PRE NOP NOP ACT tRP Address BA a, COL n BA a or all BA a, ROW CL=2.5 DQS DQ DOa-n DO a-n = data out from bank a, column n. Cases shown are either uninterrupted bursts of 4 or interrupted bursts of 8. 3 subsequent elements of data out appear in the programmed order following DO a-n. Shown with nominal tAC, tDQSCK, and tDQSQ. Don’t Care DOC # 14-02-044 Rev A ECN # 01-1116 The specifications of this device are subject to change without notice. For latest documentation, see http://www.nanoamp.com 29 NanoAmp Solutions, Inc. NT5DS64M4CT, NT5DS32M8CT, NT5DS16M16CT NT5DS64M4CS, NT5DS32M8CS, NT5DS16M16CS Read with Auto Precharge: CAS Latencies (Burst Length = 4) CAS Latency = 2 CK CK Command NOP Read with Auto Precharge NOP NOP NOP Address tRP CL=2 DQS DQ DOa-n CAS Latency = 2.5 CK CK Command Read NOP PRE NOP NOP ACT tRP Address BA a, COL n BA a or all BA a, ROW CL=2.5 DQS DQ DOa-n DO a-n = data out from bank a, column n. Cases shown are either uninterrupted bursts of 4 or interrupted bursts of 8. 3 subsequent elements of data out appear in the programmed order following DO a-n. Shown with nominal tAC, tDQSCK, and tDQSQ. Don’t Care DOC # 14-02-044 Rev A ECN # 01-1116 The specifications of this device are subject to change without notice. For latest documentation, see http://www.nanoamp.com 30 NanoAmp Solutions, Inc. Writes NT5DS64M4CT, NT5DS32M8CT, NT5DS16M16CT NT5DS64M4CS, NT5DS32M8CS, NT5DS16M16CS Write bursts are initiated with a Write command, as shown in timing figure Write Command on page 32. The starting column and bank addresses are provided with the Write command, and Auto Precharge is either enabled or disabled for that access. If Auto Precharge is enabled, the row being accessed is precharged at the completion of the burst. For the generic Write commands used in the following illustrations, Auto Precharge is disabled. During Write bursts, the first valid data-in element is registered on the first rising edge of DQS following the write command, and subsequent data elements are registered on successive edges of DQS. The Low state on DQS between the Write command and the first rising edge is known as the write preamble; the Low state on DQS following the last data-in element is known as the write postamble. The time between the Write command and the first corresponding rising edge of DQS (tDQSS) is specified with a relatively wide range (from 75% to 125% of one clock cycle), so most of the Write diagrams that follow are drawn for the two extreme cases (i.e. tDQSS(min) and tDQSS(max)). Timing figure Write Burst (Burst Length = 4) on page 33 shows the two extremes of tDQSS for a burst of four. Upon completion of a burst, assuming no other commands have been initiated, the DQs and DQS enters High-Z and any additional input data is ignored. Data for any Write burst may be concatenated with or truncated with a subsequent Write command. In either case, a continuous flow of input data can be maintained. The new Write command can be issued on any positive edge of clock following the previous Write command. The first data element from the new burst is applied after either the last element of a completed burst or the last desired data element of a longer burst which is being truncated. The new Write command should be issued x cycles after the first Write command, where x equals the number of desired data element pairs (pairs are required by the 2n prefetch architecture). Timing figure Write to Write (Burst Length = 4) on page 34 shows concatenated bursts of 4. An example of nonconsecutive Writes is shown in timing figure Write to Write: Max DQSS, Non-Consecutive (Burst Length = 4) on page 35. Fullspeed random write accesses within a page or pages can be performed as shown in timing figure Random Write Cycles (Burst Length = 2, 4 or 8) on page 36. Data for any Write burst may be followed by a subsequent Read command. To follow a Write without truncating the write burst, tWTR (Write to Read) should be met as shown in timing figure Write to Read: Non-Interrupting (CAS Latency = 2; Burst Length = 4) on page 37. Data for any Write burst may be truncated by a subsequent (interrupting) Read command. This is illustrated in timing figures “Write to Read: Interrupting (CAS Latency =2; Burst Length = 8)”, “Write to Read: Minimum DQSS, Odd Number of Data (3 bit Write), Interrupting (CAS Latency = 2; Burst Length = 8)”, and “Write to Read: Nominal DQSS, Interrupting (CAS Latency = 2; Burst Length = 8)”. Note that only the data-in pairs that are registered prior to the tWTR period are written to the internal array, and any subsequent data-in must be masked with DM, as shown in the diagrams noted previously. Data for any Write burst may be followed by a subsequent Precharge command. To follow a Write without truncating the write burst, tWR should be met as shown in timing figure Write to Precharge: Non-Interrupting (Burst Length = 4) on page 41. Data for any Write burst may be truncated by a subsequent Precharge command, as shown in timing figures Write to Precharge: Interrupting (Burst Length = 4 or 8) on page 42 to Write to Precharge: Nominal DQSS (2 bit Write), Interrupting (Burst Length = 4 or 8) on page 44. Note that only the data-in pairs that are registered prior to the tWR period are written to the internal array, and any subsequent data in should be masked with DM. Following the Precharge command, a subsequent command to the same bank cannot be issued until tRP is met. In the case of a Write burst being executed to completion, a Precharge command issued at the optimum time (as described above) provides the same operation that would result from the same burst with Auto Precharge. The disadvantage of the Precharge command is that it requires that the command and address busses be available at the appropriate time to issue the command. The advantage of the Precharge command is that it can be used to truncate bursts. DOC # 14-02-044 Rev A ECN # 01-1116 The specifications of this device are subject to change without notice. For latest documentation, see http://www.nanoamp.com 31 NanoAmp Solutions, Inc. Write Command NT5DS64M4CT, NT5DS32M8CT, NT5DS16M16CT NT5DS64M4CS, NT5DS32M8CS, NT5DS16M16CS CK CK CKE CS RAS CAS WE x4: A0-A9, A11 x8: A0-A9 HIGH CA EN AP A10 DIS AP BA0, BA1 BA CA = column address BA = bank address EN AP = enable Auto Precharge DIS AP = disable Auto Precharge Don’t Care DOC # 14-02-044 Rev A ECN # 01-1116 The specifications of this device are subject to change without notice. For latest documentation, see http://www.nanoamp.com 32 NanoAmp Solutions, Inc. Write Burst (Burst Length = 4) NT5DS64M4CT, NT5DS32M8CT, NT5DS16M16CT NT5DS64M4CS, NT5DS32M8CS, NT5DS16M16CS Maximum DQSS T1 CK CK Command Address Write BA a, COL b T2 T3 T4 NOP NOP NOP tDQSS (max) DQS DQ DM tQCSW(max) QFC (Optional) tQCHW(min) Dla-b Minimum DQSS T1 CK CK Command Address Write BA a, COL b NOP NOP NOP T2 T3 T4 tDQSS (min) DQS DQ DM tQCSW(max) QFC tQCHW(max) Dla-b DI a-b = data in for bank a, column b. 3 subsequent elements of data in are applied in the programmed order following DI a-b. A non-interrupted burst is shown. A10 is Low with the Write command (Auto Precharge is disabled). QFC is an open drain driver. Its output high level is achieved through an externally connected pull up resistor connected to VDDQ. Don’t Care DOC # 14-02-044 Rev A ECN # 01-1116 The specifications of this device are subject to change without notice. For latest documentation, see http://www.nanoamp.com 33 NanoAmp Solutions, Inc. Write to Write (Burst Length = 4) NT5DS64M4CT, NT5DS32M8CT, NT5DS16M16CT NT5DS64M4CS, NT5DS32M8CS, NT5DS16M16CS Maximum DQSS T1 CK CK Command Address Write NOP Write NOP NOP NOP T2 T3 T4 T5 T6 BAa, COL b BAa, COL n tDQSS (max) DQS DQ DM DI a-b DI a-n Minimum DQSS T1 CK CK Command Address Write BA, COL b T2 T3 T4 T5 T6 NOP Write BA, COL n NOP NOP NOP tDQSS (min) DQS DQ DM DI a-b DI a-n DI a-b = data in for bank a, column b, etc. 3 subsequent elements of data in are applied in the programmed order following DI a-b. 3 subsequent elements of data in are applied in the programmed order following DI a-n. A non-interrupted burst is shown. Each Write command may be to any bank. Don’t Care DOC # 14-02-044 Rev A ECN # 01-1116 The specifications of this device are subject to change without notice. For latest documentation, see http://www.nanoamp.com 34 NanoAmp Solutions, Inc. NT5DS64M4CT, NT5DS32M8CT, NT5DS16M16CT NT5DS64M4CS, NT5DS32M8CS, NT5DS16M16CS Write to Write: Max DQSS, Non-Consecutive (Burst Length = 4) T1 CK CK Command Address Write T2 T3 T4 T5 NOP NOP Write NOP BAa, COL b BAa, COL n tDQSS (max) DQS DQ DM DI a-b DI a-n DI a-b, etc. = data in for bank a, column b, etc. 3 subsequent elements of data in are applied in the programmed order following DI a-b. 3 subsequent elements of data in are applied in the programmed order following DI a-n. A non-interrupted burst is shown. Each Write command may be to any bank. Don’t Care DOC # 14-02-044 Rev A ECN # 01-1116 The specifications of this device are subject to change without notice. For latest documentation, see http://www.nanoamp.com 35 NanoAmp Solutions, Inc. Random Write Cycles (Burst Length = 2, 4 or 8) NT5DS64M4CT, NT5DS32M8CT, NT5DS16M16CT NT5DS64M4CS, NT5DS32M8CS, NT5DS16M16CS Maximum DQSS T1 CK CK Command Address Write BAa, COL b T2 T3 T4 T5 Write BAa, COL x Write BAa, COL n Write BAa, COL a Write BAa, COL g tDQSS (max) DQS DQ DM DI a-b DI a-b’ DI a-x DI a-x’ DI a-n DI a-n’ DI a-a DI a-a’ Minimum DQSS T1 CK CK Command Address Write BAa, COL b T2 T3 T4 T5 Write BAa, COL x Write BAa, COL n Write BAa, COL a Write BAa, COL g tDQSS (min) DQS DQ DM DI a-b DI a-b’ DI a-x DI a-x’ DI a-n DI a-n’ DI a-a DI a-a’ DI a-g DI a-b, etc. = data in for bank a, column b, etc. b', etc. = odd or even complement of b, etc. (i.e., column address LSB inverted). Each Write command may be to any bank. Don’t Care DOC # 14-02-044 Rev A ECN # 01-1116 The specifications of this device are subject to change without notice. For latest documentation, see http://www.nanoamp.com 36 NanoAmp Solutions, Inc. NT5DS64M4CT, NT5DS32M8CT, NT5DS16M16CT NT5DS64M4CS, NT5DS32M8CS, NT5DS16M16CS Write to Read: Non-Interrupting (CAS Latency = 2; Burst Length = 4) Maximum DQSS T1 CK CK Command Write NOP NOP NOP Read NOP T2 T3 T4 T5 T6 tWTR Address BAa, COL b BAa, COL n tDQSS (max) DQS DQ DM DI a-b CL = 2 Minimum DQSS T1 CK CK Command Write NOP NOP NOP Read NOP T2 T3 T4 T5 T6 tWTR Address BAa, COL b BAa, COL n tDQSS (min) DQS DQ DM DI a-b CL = 2 DI a-b = data in for bank a, column b. 3 subsequent elements of data in are applied in the programmed order following DI a-b. A non-interrupted burst is shown. tWTR is referenced from the first positive CK edge after the last data in pair. A10 is Low with the Write command (Auto Precharge is disabled). The Read and Write commands may be to any bank. Don’t Care DOC # 14-02-044 Rev A ECN # 01-1116 The specifications of this device are subject to change without notice. For latest documentation, see http://www.nanoamp.com 37 NanoAmp Solutions, Inc. NT5DS64M4CT, NT5DS32M8CT, NT5DS16M16CT NT5DS64M4CS, NT5DS32M8CS, NT5DS16M16CS Write to Read: Interrupting (CAS Latency = 2; Burst Length = 8) Maximum DQSS T1 CK CK Command Write NOP NOP NOP Read NOP T2 T3 T4 T5 T6 tWTR Address BAa, COL b BAa, COL n tDQSS (max) DQS DQ DM DIa- b CL = 2 1 1 Minimum DQSS T1 CK CK Command Write NOP NOP NOP Read NOP T2 T3 T4 T5 T6 tWTR Address BAa, COL b BAa, COL n tDQSS (min) DQS DQ DM DI a-b CL = 2 1 1 DI a-b = data in for bank a, column b. An interrupted burst is shown, 4 data elements are written. 3 subsequent elements of data in are applied in the programmed order following DI a-b. tWTR is referenced from the first positive CK edge after the last data in pair. The Read command masks the last 2 data elements in the burst. A10 is Low with the Write command (Auto Precharge is disabled). The Read and Write commands are not necessarily to the same bank. 1 = These bits are incorrectly written into the memory array if DM is low. Don’t Care DOC # 14-02-044 Rev A ECN # 01-1116 The specifications of this device are subject to change without notice. For latest documentation, see http://www.nanoamp.com 38 NanoAmp Solutions, Inc. NT5DS64M4CT, NT5DS32M8CT, NT5DS16M16CT NT5DS64M4CS, NT5DS32M8CS, NT5DS16M16CS Write to Read: Minimum DQSS, Odd Number of Data (3 bit Write), Interrupting (CAS Latency = 2; Burst Length = 8) T1 CK CK Command Write T2 T3 T4 T5 T6 NOP NOP NOP Read NOP tWTR Address BAa, COL b BAa, COL n tDQSS (min) DQS DQ DM DI a-b CL = 2 1 2 2 DI a-b = data in for bank a, column b. An interrupted burst is shown, 3 data elements are written. 2 subsequent elements of data in are applied in the programmed order following DI a-b. tWTR is referenced from the first positive CK edge after the last desired data in pair (not the last desired data in element) The Read command masks the last 2 data elements in the burst. A10 is Low with the Write command (Auto Precharge is disabled). The Read and Write commands are not necessarily to the same bank. 1 = This bit is correctly written into the memory array if DM is low. Don’t Care 2 = These bits are incorrectly written into the memory array if DM is low. DOC # 14-02-044 Rev A ECN # 01-1116 The specifications of this device are subject to change without notice. For latest documentation, see http://www.nanoamp.com 39 NanoAmp Solutions, Inc. NT5DS64M4CT, NT5DS32M8CT, NT5DS16M16CT NT5DS64M4CS, NT5DS32M8CS, NT5DS16M16CS Write to Read: Nominal DQSS, Interrupting (CAS Latency = 2; Burst Length = 8) T1 CK CK Command Write T2 T3 T4 T5 T6 NOP NOP NOP Read NOP tWTR Address BAa, COL b BAa, COL n tDQSS (nom) DQS DQ DM DI a-b CL = 2 1 1 DI a-b = data in for bank a, column b. An interrupted burst is shown, 4 data elements are written. 3 subsequent elements of data in are applied in the programmed order following DI a-b. tWTR is referenced from the first positive CK edge after the last desired data in pair. The Read command masks the last 2 data elements in the burst. A10 is Low with the Write command (Auto Precharge is disabled). The Read and Write commands are not necessarily to the same bank. 1 = These bits are incorrectly written into the memory array if DM is low. Don’t Care DOC # 14-02-044 Rev A ECN # 01-1116 The specifications of this device are subject to change without notice. For latest documentation, see http://www.nanoamp.com 40 NanoAmp Solutions, Inc. NT5DS64M4CT, NT5DS32M8CT, NT5DS16M16CT NT5DS64M4CS, NT5DS32M8CS, NT5DS16M16CS Write to Precharge: Non-Interrupting (Burst Length = 4) Maximum DQSS T1 CK CK Command Write NOP NOP NOP NOP PRE T2 T3 T4 T5 T6 tWR Address BA a, COL b BA (a or all) tDQSS (max) DQS DQ DM DI a-b tRP Minimum DQSS T1 CK CK Command Write NOP NOP NOP NOP PRE T2 T3 T4 T5 T6 tWR Address BA a, COL b BA (a or all) tDQSS (min) DQS DQ DM DI a-b tRP DI a-b = data in for bank a, column b. 3 subsequent elements of data in are applied in the programmed order following DI a-b. A non-interrupted burst is shown. tWR is referenced from the first positive CK edge after the last data in pair. A10 is Low with the Write command (Auto Precharge is disabled). Don’t Care DOC # 14-02-044 Rev A ECN # 01-1116 The specifications of this device are subject to change without notice. For latest documentation, see http://www.nanoamp.com 41 NanoAmp Solutions, Inc. NT5DS64M4CT, NT5DS32M8CT, NT5DS16M16CT NT5DS64M4CS, NT5DS32M8CS, NT5DS16M16CS Write to Precharge: Interrupting (Burst Length = 4 or 8) Maximum DQSS T1 CK CK Command Write NOP NOP NOP PRE NOP T2 T3 T4 T5 T6 tWR Address BA a, COL b BA (a or all) tDQSS (max) DQS DQ DM DI a-b 2 tRP 3 3 1 1 Minimum DQSS T1 CK CK Command Write NOP NOP NOP PRE NOP T2 T3 T4 T5 T6 tWR Address BA a, COL b BA (a or all) tDQSS (min) DQS DQ DM DI a-b 2 tRP 3 3 1 1 DI a-b = data in for bank a, column b. An interrupted burst is shown, 2 data elements are written. 1 subsequent element of data in is applied in the programmed order following DI a-b. tWR is referenced from the first positive CK edge after the last desired data in pair. The Precharge command masks the last 2 data elements in the burst, for burst length = 8. A10 is Low with the Write command (Auto Precharge is disabled). 1 = Can be don't care for programmed burst length of 4. 2 = For programmed burst length of 4, DQS becomes don't care at this point. 3 = These bits are incorrectly written into the memory array if DM is low. Don’t Care DOC # 14-02-044 Rev A ECN # 01-1116 The specifications of this device are subject to change without notice. For latest documentation, see http://www.nanoamp.com 42 NanoAmp Solutions, Inc. NT5DS64M4CT, NT5DS32M8CT, NT5DS16M16CT NT5DS64M4CS, NT5DS32M8CS, NT5DS16M16CS Write to Precharge: Minimum DQSS, Odd Number of Data (1 bit Write), Interrupting (Burst Length = 4 or 8) T1 CK CK Command Write T2 T3 T4 T5 T6 NOP NOP NOP PRE NOP tWR Address BA a, COL b BA (a or all) tDQSS (min) DQS DQ DM DI a-b 2 tRP 3 4 4 1 1 DI a-b = data in for bank a, column b. An interrupted burst is shown, 1 data element is written. tWR is referenced from the first positive CK edge after the last desired data in pair. The Precharge command masks the last 2 data elements in the burst. A10 is Low with the Write command (Auto Precharge is disabled). 1 = Can be don't care for programmed burst length of 4. 2 = For programmed burst length of 4, DQS becomes don't care at this point. 3 = This bit is correctly written into the memory array if DM is low. 4 = These bits are incorrectly written into the memory array if DM is low. Don’t Care DOC # 14-02-044 Rev A ECN # 01-1116 The specifications of this device are subject to change without notice. For latest documentation, see http://www.nanoamp.com 43 NanoAmp Solutions, Inc. NT5DS64M4CT, NT5DS32M8CT, NT5DS16M16CT NT5DS64M4CS, NT5DS32M8CS, NT5DS16M16CS Write to Precharge: Nominal DQSS (2 bit Write), Interrupting (Burst Length = 4 or 8) T1 CK CK Command Write T2 T3 T4 T5 T6 NOP NOP NOP PRE NOP tWR Address BA a, COL b BA (a or all) tDQSS (nom) DQS DQ DM DI a-b 2 tRP 3 3 1 1 DI a-b = Data In for bank a, column b. An interrupted burst is shown, 2 data elements are written. 1 subsequent element of data in is applied in the programmed order following DI a-b. tWR is referenced from the first positive CK edge after the last desired data in pair. The Precharge command masks the last 2 data elements in the burst. A10 is Low with the Write command (Auto Precharge is disabled). 1 = Can be don't care for programmed burst length of 4. 2 = For programmed burst length of 4, DQS becomes don't care at this point. 3 = These bits are incorrectly written into the memory array if DM is low. Don’t Care DOC # 14-02-044 Rev A ECN # 01-1116 The specifications of this device are subject to change without notice. For latest documentation, see http://www.nanoamp.com 44 NanoAmp Solutions, Inc. Precharge Command CK CK CKE CS RAS CAS WE A0-A9, A11, A12 All Banks A10 BA0, BA1 One Bank BA HIGH NT5DS64M4CT, NT5DS32M8CT, NT5DS16M16CT NT5DS64M4CS, NT5DS32M8CS, NT5DS16M16CS BA = bank address (if A10 is Low, otherwise Don’t Care). Don’t Care Precharge The Precharge command is used to deactivate the open row in a particular bank or the open row in all banks. The bank(s) is available for a subsequent row access some specified time (tRP) after the Precharge command is issued. Input A10 determines whether one or all banks are to be precharged, and in the case where only one bank is to be precharged, inputs BA0, BA1 select the bank. When all banks are to be precharged, inputs BA0, BA1 are treated as “Don’t Care.” Once a bank has been precharged, it is in the idle state and must be activated prior to any Read or Write commands being issued to that bank. DOC # 14-02-044 Rev A ECN # 01-1116 The specifications of this device are subject to change without notice. For latest documentation, see http://www.nanoamp.com 45 NanoAmp Solutions, Inc. Power Down NT5DS64M4CT, NT5DS32M8CT, NT5DS16M16CT NT5DS64M4CS, NT5DS32M8CS, NT5DS16M16CS Power Down is entered when CKE is registered low (no accesses can be in progress). If Power Down occurs when all banks are idle, this mode is referred to as Precharge Power Down; if Power Down occurs when there is a row active in any bank, this mode is referred to as Active Power Down. Entering Power Down deactivates the input and output buffers, excluding CK, CK and CKE. The DLL is still running in Power Down mode, so for maximum power savings, the user has the option of disabling the DLL prior to entering Power Down. In that case, the DLL must be enabled after exiting Power Down, and 200 clock cycles must occur before a Read command can be issued. In Power Down mode, CKE Low and a stable clock signal must be maintained at the inputs of the DDR SDRAM, and all other input signals are “Don’t Care”. However, Power Down duration is limited by the refresh requirements of the device, so in most applications, the self refresh mode is preferred over the DLL-disabled Power Down mode. The Power Down state is synchronously exited when CKE is registered high (along with a Nop or Deselect command). A valid, executable command may be applied one clock cycle later. Power Down CK CK CKE tIS tIS Command VALID No column access in progress NOP NOP Exit power down mode tPDEX VALID Enter Power Down mode (Burst Read or Write operation must not be in progress) Don’t Care DOC # 14-02-044 Rev A ECN # 01-1116 The specifications of this device are subject to change without notice. For latest documentation, see http://www.nanoamp.com 46 NanoAmp Solutions, Inc. Truth Table 2: Clock Enable (CKE) 1. 2. 3. 4. NT5DS64M4CT, NT5DS32M8CT, NT5DS16M16CT NT5DS64M4CS, NT5DS32M8CS, NT5DS16M16CS CKE n is the logic state of CKE at clock edge n: CKE n-1 was the state of CKE at the previous clock edge. Current state is the state of the DDR SDRAM immediately prior to clock edge n. Command n is the command registered at clock edge n, and action n is a result of command n. All states and sequences not shown are illegal or reserved. CKE n-1 Current State Previous Cycle L L L L H H H H CKEn Current Cycle L H L H L L L H Command n Action n Notes Self Refresh Self Refresh Power Down Power Down All Banks Idle All Banks Idle Bank(s) Active X Deselect or NOP X Deselect or NOP Deselect or NOP Auto Refresh Deselect or NOP See “Truth Table 3: Current State Bank n - Command to Bank n (Same Bank)” on page 48 Maintain Self-Refresh Exit Self-Refresh Maintain Power Down Exit Power Down Precharge Power Down Entry Self Refresh Entry Active Power Down Entry 1 1. Deselect or NOP commands should be issued on any clock edges occurring during the Self Refresh Exit (tXSNR) period. A minimum of 200 clock cycles are needed before applying a read command to allow the DLL to lock to the input clock. DOC # 14-02-044 Rev A ECN # 01-1116 The specifications of this device are subject to change without notice. For latest documentation, see http://www.nanoamp.com 47 NanoAmp Solutions, Inc. NT5DS64M4CT, NT5DS32M8CT, NT5DS16M16CT NT5DS64M4CS, NT5DS32M8CS, NT5DS16M16CS Truth Table 3: Current State Bank n - Command to Bank n (Same Bank) Current State Any L L Idle L L L Row Active L L Read (Auto Precharge Disabled) L L L L L L H L L L H H L H L H H H L H H L L L L H L H H L L H H H H L H L L H L L H L L No Operation Active Auto Refresh Mode Register Set Read Write Precharge Read Precharge Burst Terminate Read Write Precharge Select column and start Read burst Select column and start Write burst Deactivate row in bank(s) Select column and start new Read burst Truncate Read burst, start Precharge Burst Terminate Select column and start Read burst Select column and start Write burst Truncate Write burst, start Precharge NOP. Continue previous operation Select and activate row 1-6 1-6 1-7 1-7 1-6, 10 1-6, 10 1-6, 8 1-6, 10 1-6, 8 1-6, 9 1-6, 10, 11 1-6, 10 1-6, 8, 11 CS H RAS X CAS X WE X Command Deselect Action NOP. Continue previous operation Notes 1-6 Write (Auto Precharge Disabled) 1. This table applies when CKE n-1 was high and CKE n is high (see Truth Table 2: Clock Enable (CKE) and after tXSNR / tXSRD has been met (if the previous state was self refresh). 2. This table is bank-specific, except where noted, i.e., the current state is for a specific bank and the commands shown are those allowed to be issued to that bank when in that state. Exceptions are covered in the notes below. 3. Current state definitions: Idle: The bank has been precharged, and tRP has been met. Row Active: A row in the bank has been activated, and tRCD has been met. No data bursts/accesses and no register accesses are in progress. Read: A Read burst has been initiated, with Auto Precharge disabled, and has not yet terminated or been terminated. Write: A Write burst has been initiated, with Auto Precharge disabled, and has not yet terminated or been terminated. 4. The following states must not be interrupted by a command issued to the same bank. Precharging: Starts with registration of a Precharge command and ends when tRP is met. Once tRP is met, the bank is in the idle state. Row Activating: Starts with registration of an Active command and ends when tRCD is met. Once tRCD is met, the bank is in the “row active” state. Read w/Auto Precharge Enabled: Starts with registration of a Read command with Auto Precharge enabled and ends when tRP has been met. Once tRP is met, the bank is in the idle state. Write w/Auto Precharge Enabled: Starts with registration of a Write command with Auto Precharge enabled and ends when tRP has been met. Once tRP is met, the bank is in the idle state. Deselect or NOP commands, or allowable commands to the other bank should be issued on any clock edge occurring during these states. Allowable commands to the other bank are determined by its current state and according to Truth Table 4. 5. The following states must not be interrupted by any executable command; Deselect or NOP commands must be applied on each positive clock edge during these states. Refreshing: Starts with registration of an Auto Refresh command and ends when tRFC is met. Once tRFC is met, the DDR SDRAM is in the “all banks idle” state. Accessing Mode Register: Starts with registration of a Mode Register Set command and ends when tMRD has been met. Once tMRD is met, the DDR SDRAM is in the “all banks idle” state. Precharging All: Starts with registration of a Precharge All command and ends when tRP is met. Once tRP is met, all banks is in the idle state. 6. All states and sequences not shown are illegal or reserved. 7. Not bank-specific; requires that all banks are idle. 8. May or may not be bank-specific; if all/any banks are to be precharged, all/any must be in a valid state for precharging. 9. Not bank-specific; Burst terminate affects the most recent Read burst, regardless of bank. 10. Reads or Writes listed in the Command/Action column include Reads or Writes with Auto Precharge enabled and Reads or Writes with Auto Precharge disabled. 11. Requires appropriate DM masking. DOC # 14-02-044 Rev A ECN # 01-1116 The specifications of this device are subject to change without notice. For latest documentation, see http://www.nanoamp.com 48 NanoAmp Solutions, Inc. NT5DS64M4CT, NT5DS32M8CT, NT5DS16M16CT NT5DS64M4CS, NT5DS32M8CS, NT5DS16M16CS Truth Table 4: Current State Bank n - Command to Bank m (Different bank) (Part 1 of 2) Current State Any L Idle X L Row Activating, Active, or Precharging L L L Read (Auto Precharge Disabled) L L L L Write (Auto Precharge Disabled) L L L H X L H H L L H L L H H L H X H L L H H L H H L L H H X H H L L H H L H H L L No Operation Any Command Otherwise Allowed to Bank m Active Read Write Precharge Active Read Precharge Active Read Write Precharge Select and activate row Select column and start Read burst Select column and start new Write burst Select and activate row Select column and start new Read burst Select and activate row Select column and start Read burst Select column and start Write burst NOP/continue previous operation 1-6 1-6 1-6 1-7 1-7 1-6 1-6 1-7 1-6 1-6 1-8 1-7 1-6 CS H RAS X CAS X WE X Command Deselect Action NOP/continue previous operation Notes 1-6 1. This table applies when CKE n-1 was high and CKE n is high (see Truth Table 2: Clock Enable (CKE) and after tXSNR / tXSRD has been met (if the previous state was self refresh). 2. This table describes alternate bank operation, except where noted, i.e., the current state is for bank n and the commands shown are those allowed to be issued to bank m (assuming that bank m is in such a state that the given command is allowable). Exceptions are covered in the notes below. 3. Current state definitions: Idle: The bank has been precharged, and tRP has been met. Row Active: A row in the bank has been activated, and tRCD has been met. No data bursts/accesses and no register accesses are in progress. Read: A Read burst has been initiated, with Auto Precharge disabled, and has not yet terminated or been terminated. Write: A Write burst has been initiated, with Auto Precharge disabled, and has not yet terminated or been terminated. Read with Auto Precharge Enabled: See note 10. Write with Auto Precharge Enabled: See note 10. 4. Auto Refresh and Mode Register Set commands may only be issued when all banks are idle. 5. A Burst Terminate command cannot be issued to another bank; it applies to the bank represented by the current state only. 6. All states and sequences not shown are illegal or reserved. 7. Reads or Writes listed in the Command/Action column include Reads or Writes with Auto Precharge enabled and Reads or Writes with Auto Precharge disabled. 8. Requires appropriate DM masking. 9. A Write command may be applied after the completion of data output. 10. The Read with Auto Precharge enabled or Write with Auto Precharge enabled states can each be broken into two parts: the access period and the precharge period. For Read with Auto Precharge, the precharge period is defined as if the same burst was executed with Auto Precharge disabled and then followed with the earliest possible Precharge command that still accesses all of the data in the burst. For Write with Auto Precharge, the precharge period begins when tWR ends, with tWR measured as if Auto Precharge was disabled. The access period starts with registration of the command and ends where the precharge period (or tRP) begins. During the precharge period of the Read with Auto Precharge Enabled or Write with Auto Precharge Enabled states, Active, Precharge, Read, and Write commands to the other bank may be applied; during the access period, only Active and Precharge commands to the other bank may be applied. In either case, all other related limitations apply (e.g. contention between Read data and Write data must be avoided). DOC # 14-02-044 Rev A ECN # 01-1116 The specifications of this device are subject to change without notice. For latest documentation, see http://www.nanoamp.com 49 NanoAmp Solutions, Inc. (Part 2 of 2) Current State CS L Read (With Auto Precharge) L L L L Write (With Auto Precharge) L L L RAS L H H L L H H L CAS H L L H H L L H WE H H L L H H L L Command Active Read Write Precharge Active Read Write Precharge NT5DS64M4CT, NT5DS32M8CT, NT5DS16M16CT NT5DS64M4CS, NT5DS32M8CS, NT5DS16M16CS Truth Table 4: Current State Bank n - Command to Bank m (Different bank) Action Select and activate row Select column and start new Read burst Select column and start Write burst Notes 1-6 1-7,10 1-7,9,10 1-6 Select and activate row Select column and start Read burst Select column and start new Write burst 1-6 1-7,10 1-7,10 1-6 1. This table applies when CKE n-1 was high and CKE n is high (see Truth Table 2: Clock Enable (CKE) and after tXSNR / tXSRD has been met (if the previous state was self refresh). 2. This table describes alternate bank operation, except where noted, i.e., the current state is for bank n and the commands shown are those allowed to be issued to bank m (assuming that bank m is in such a state that the given command is allowable). Exceptions are covered in the notes below. 3. Current state definitions: Idle: The bank has been precharged, and tRP has been met. Row Active: A row in the bank has been activated, and tRCD has been met. No data bursts/accesses and no register accesses are in progress. Read: A Read burst has been initiated, with Auto Precharge disabled, and has not yet terminated or been terminated. Write: A Write burst has been initiated, with Auto Precharge disabled, and has not yet terminated or been terminated. Read with Auto Precharge Enabled: See note 10. Write with Auto Precharge Enabled: See note 10. 4. Auto Refresh and Mode Register Set commands may only be issued when all banks are idle. 5. A Burst Terminate command cannot be issued to another bank; it applies to the bank represented by the current state only. 6. All states and sequences not shown are illegal or reserved. 7. Reads or Writes listed in the Command/Action column include Reads or Writes with Auto Precharge enabled and Reads or Writes with Auto Precharge disabled. 8. Requires appropriate DM masking. 9. A Write command may be applied after the completion of data output. 10. The Read with Auto Precharge enabled or Write with Auto Precharge enabled states can each be broken into two parts: the access period and the precharge period. For Read with Auto Precharge, the precharge period is defined as if the same burst was executed with Auto Precharge disabled and then followed with the earliest possible Precharge command that still accesses all of the data in the burst. For Write with Auto Precharge, the precharge period begins when tWR ends, with tWR measured as if Auto Precharge was disabled. The access period starts with registration of the command and ends where the precharge period (or tRP) begins. During the precharge period of the Read with Auto Precharge Enabled or Write with Auto Precharge Enabled states, Active, Precharge, Read, and Write commands to the other bank may be applied; during the access period, only Active and Precharge commands to the other bank may be applied. In either case, all other related limitations apply (e.g. contention between Read data and Write data must be avoided). DOC # 14-02-044 Rev A ECN # 01-1116 The specifications of this device are subject to change without notice. For latest documentation, see http://www.nanoamp.com 50 NanoAmp Solutions, Inc. Simplified State Diagram Power Applied Power On NT5DS64M4CT, NT5DS32M8CT, NT5DS16M16CT NT5DS64M4CS, NT5DS32M8CS, NT5DS16M16CS Precharge Preall Self Refresh REFS REFSX MRS EMRS MRS Idle REFA Auto Refresh CKEL CKEH Active Power Down CKEH CKEL ACT Precharge Power Down Write Write A Write Row Active Burst Stop Read Read A Read Read Write A Read A Write A PRE PRE PRE Read A Read A PRE Precharge Preall Automatic Sequence Command Sequence PREALL = Precharge All Banks MRS = Mode Register Set EMRS = Extended Mode Register Set REFS = Enter Self Refresh REFSX = Exit Self Refresh REFA = Auto Refresh CKEL = Enter Power Down CKEH = Exit Power Down ACT = Active Write A = Write with Autoprecharge Read A = Read with Autoprecharge PRE = Precharge DOC # 14-02-044 Rev A ECN # 01-1116 The specifications of this device are subject to change without notice. For latest documentation, see http://www.nanoamp.com 51 NanoAmp Solutions, Inc. Absolute Maximum Ratings Symbol VIN, VOUT VIN VDD VDDQ TA TSTG PD IOUT Parameter Voltage on I/O pins relative to VSS Voltage on Inputs relative to VSS Voltage on VDD supply relative to VSS Voltage on VDDQ supply relative to VSS Operating Temperature (Ambient) Storage Temperature (Plastic) Power Dissipation Short Circuit Output Current NT5DS64M4CT, NT5DS32M8CT, NT5DS16M16CT NT5DS64M4CS, NT5DS32M8CS, NT5DS16M16CS Rating Units V V V V −0.5 to VDDQ+ 0.5 −0.5 to +3.6 −0.5 to +3.6 −0.5 to +3.6 0 to +70 °C °C W mA −55 to +150 1.0 50 Note: Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. DQS/DQ/DM Slew Rate Parameter Symbol DDR400 (5T) Min DCS/DQ/DM input slew rate DCSLEW TBD Max TBD DDR333 (6K) Min TBD Max TBD V/ns 1, 2 Unit Notes 1. Measured between V IH (DC), V IL (DC), and V IL (DC), V IH (DC). 2. DQS, DQ, and DM input slew rate is specified to prevent double clocking of data and preserve setup and hold times. Signal transition through the DC region must be monotonic. DOC # 14-02-044 Rev A ECN # 01-1116 The specifications of this device are subject to change without notice. For latest documentation, see http://www.nanoamp.com 52 NanoAmp Solutions, Inc. Capacitance Parameter Input Capacitance: CK, CK Delta Input Capacitance: CK, CK Input Capacitance: All other input-only pins (except DM) Delta Input Capacitance: All other input-only pins (except DM) Input/Output Capacitance: DQ, DQS, DM Delta Input/Output Capacitance: DQ, DQS, DM NT5DS64M4CT, NT5DS32M8CT, NT5DS16M16CT NT5DS64M4CS, NT5DS32M8CS, NT5DS16M16CS Symbol CI1 delta CI1 CI2 delta CI2 CIO delta CIO Min. 2.0 Max. 3.0 0.25 Units pF pF pF pF pF pF Notes 1 1 1 1 1, 2 1 2.0 3.0 0.5 4.0 5.0 0.5 1. VDDQ = VDD = 2.5V ± 0.2V (minimum range to maximum range), f = 100MHz, TA = 25°C, VODC = VDDQ/2, VOPeak -Peak = 0.2V. 2. Although DM is an input-only pin, the input capacitance of this pin must model the input capacitance of the DQ and DQS pins. This is required to match input propagation times of DQ, DQS and DM in the system. DC Electrical Characteristics and Operating Conditions (0°C £ TA £ 70×C; VDDQ = 2.5V ± 0.2V, VDD = + 2.5V ± 0.2V, see AC Characteristics) Symbol VDD VDDQ VSS, VSSQ VREF VTT VIH(DC) VIL(DC) VIN(DC) VID(DC) VIX(DC) VIRatio II IOZ IOH IOL Supply Voltage I/O Supply Voltage Supply Voltage I/O Supply Voltage I/O Reference Voltage I/O Termination Voltage (System) Input High (Logic1) Voltage Input Low (Logic0) Voltage Input Voltage Level, CK and CK Inputs Input Differential Voltage, CK and CK Inputs Input Crossing Point Voltage, CK and CK Inputs V-I Matching Pullup Current to Pulldown Current Ratio Input Leakage Current Any input 0V ≤ VIN ≤ VDD; (All other pins not under test = 0V) Output Leakage Current (DQs are disabled; 0V ≤ Vout ≤ VDDQ Output Current: Nominal Strength Driver High current (VOUT= VDDQ -0.373V, min VREF, min VTT) Low current (VOUT= 0.373V, max VREF, max VTT) Parameter Min 2.3 2.3 0 0.49 x VDDQ VREF − 0.04 VREF + 0.15 − 0.3 − 0.3 0.30 0.30 0.71 −5 −5 − 16.8 mA 16.8 1 Max 2.7 2.7 0 0.51 x VDDQ VREF + 0.04 VDDQ + 0.3 VREF − 0.15 VDDQ + 0.3 VDDQ + 0.6 VDDQ + 0.6 1.4 5 5 µA µA Units V V V V V V V V V V 1, 2 1, 3 1 1 1 1, 4 1, 4 5 1 1 Notes 1 1 1. Inputs are not recognized as valid until VREF stabilizes. 2. VREF is expected to be equal to 0.5 VDDQ of the transmitting device, and to track variations in the DC level of the same. Peak-to-peak noise on VREF may not exceed ± 2% of the DC value. 3. VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF, and must track variations in the DC level of VREF. 4. VID is the magnitude of the difference between the input level on CK and the input level on CK. 5. The ratio of the pullup current to the pulldown current is specified for the same temperature and voltage, over the entire temperature and voltage range, for device drain to source voltages for 0.25 volts to 1.0 volts. For a given output, it represents the maximum difference between pullup and pulldown drivers due to process variation. DOC # 14-02-044 Rev A ECN # 01-1116 The specifications of this device are subject to change without notice. For latest documentation, see http://www.nanoamp.com 53 NanoAmp Solutions, Inc. NT5DS64M4CT, NT5DS32M8CT, NT5DS16M16CT NT5DS64M4CS, NT5DS32M8CS, NT5DS16M16CS DC Electrical Characteristics and Operating Conditions (0°C £ TA £ 70×C; VDDQ = 2.5V ± 0.2V, VDD = + 2.5V ± 0.2V, see AC Characteristics) Symbol IOHW IOLW Parameter Output Current: Half- Strength Driver High current (VOUT= VDDQ -0.763V, min VREF, min VTT) Low current (VOUT= 0.763V, max VREF, max VTT) Min − 9.0 mA 9.0 1 Max Units Notes 1. Inputs are not recognized as valid until VREF stabilizes. 2. VREF is expected to be equal to 0.5 VDDQ of the transmitting device, and to track variations in the DC level of the same. Peak-to-peak noise on VREF may not exceed ± 2% of the DC value. 3. VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF, and must track variations in the DC level of VREF. 4. VID is the magnitude of the difference between the input level on CK and the input level on CK. 5. The ratio of the pullup current to the pulldown current is specified for the same temperature and voltage, over the entire temperature and voltage range, for device drain to source voltages for 0.25 volts to 1.0 volts. For a given output, it represents the maximum difference between pullup and pulldown drivers due to process variation. Normal Strength Driver Pulldown and Pullup Characteristics 1. The full variation in driver pulldown current from minimum to maximum process, temperature and voltage will lie within the outer bounding lines of the V-I curve. 2. It is recommended that the “typical” IBIS pulldown V-I curve lie within the shaded region of the V-I curve. Normal Strength Driver Pulldown Characteristics 140 Maximum IOUT (mA) Typical High Typical Low Minimum 0 0 VOUT (V) 2.7 3. The full variation in driver pullup current from minimum to maximum process, temperature and voltage will lie within the outer bounding lines of the V-I curve. 4. It is recommended that the “typical” IBIS pullup V-I curve lie within the shaded region of the V-I curve. DOC # 14-02-044 Rev A ECN # 01-1116 The specifications of this device are subject to change without notice. For latest documentation, see http://www.nanoamp.com 54 NanoAmp Solutions, Inc. Normal Strength Driver Pullup Characteristics 0 NT5DS64M4CT, NT5DS32M8CT, NT5DS16M16CT NT5DS64M4CS, NT5DS32M8CS, NT5DS16M16CS Minimum IOUT (mA) Typical Low Typical High -200 0 VOUT (V) 5. The full variation in the ratio of the maximum to minimum pullup and pulldown current will not exceed 1.7, for device drain to source voltages from 0.1 to 1.0. 6. The full variation in the ratio of the “typical” IBIS pullup to “typical” IBIS pulldown current should be unity + 10%, for device drain to source voltages from 0.1 to 1.0. This specification is a design objective only. It is not guaranteed. 7. These characteristics are intended to obey the SSTL_2 class II standard. 8. This specification is intended for DDR SDRAM only. Maximum 2.7 DOC # 14-02-044 Rev A ECN # 01-1116 The specifications of this device are subject to change without notice. For latest documentation, see http://www.nanoamp.com 55 NanoAmp Solutions, Inc. NT5DS64M4CT, NT5DS32M8CT, NT5DS16M16CT NT5DS64M4CS, NT5DS32M8CS, NT5DS16M16CS Normal Strength Driver Pulldown and Pullup Currents Pulldown Current (mA) Voltage (V) 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2.0 2.1 2.2 2.3 2.4 2.5 2.6 2.7 Typical Low 6.0 12.2 18.1 24.1 29.8 34.6 39.4 43.7 47.5 51.3 54.1 56.2 57.9 59.3 60.1 60.5 61.0 61.5 62.0 62.5 62.9 63.3 63.8 64.1 64.6 64.8 65.0 Typical High 6.8 13.5 20.1 26.6 33.0 39.1 44.2 49.8 55.2 60.3 65.2 69.9 74.2 78.4 82.3 85.9 89.1 92.2 95.3 97.2 99.1 100.9 101.9 102.8 103.8 104.6 105.4 Min 4.6 9.2 13.8 18.4 23.0 27.7 32.2 36.8 39.6 42.6 44.8 46.2 47.1 47.4 47.7 48.0 48.4 48.9 49.1 49.4 49.6 49.8 49.9 50.0 50.2 50.4 50.5 Max 9.6 18.2 26.0 33.9 41.8 49.4 56.8 63.2 69.9 76.3 82.5 88.3 93.8 99.1 103.8 108.4 112.1 115.9 119.6 123.3 126.5 129.5 132.4 135.0 137.3 139.2 140.8 Typical Low -6.1 -12.2 -18.1 -24.0 -29.8 -34.3 -38.1 -41.1 -43.8 -46.0 -47.8 -49.2 -50.0 -50.5 -50.7 -51.0 -51.1 -51.3 -51.5 -51.6 -51.8 -52.0 -52.2 -52.3 -52.5 -52.7 -52.8 Pullup Current (mA) Typical High -7.6 -14.5 -21.2 -27.7 -34.1 -40.5 -46.9 -53.1 -59.4 -65.5 -71.6 -77.6 -83.6 -89.7 -95.5 -101.3 -107.1 -112.4 -118.7 -124.0 -129.3 -134.6 -139.9 -145.2 -150.5 -155.3 -160.1 Min -4.6 -9.2 -13.8 -18.4 -23.0 -27.7 -32.2 -36.0 -38.2 -38.7 -39.0 -39.2 -39.4 -39.6 -39.9 -40.1 -40.2 -40.3 -40.4 -40.5 -40.6 -40.7 -40.8 -40.9 -41.0 -41.1 -41.2 Max -10.0 -20.0 -29.8 -38.8 -46.8 -54.4 -61.8 -69.5 -77.3 -85.2 -93.0 -100.6 -108.1 -115.5 -123.0 -130.4 -136.7 -144.2 -150.5 -156.9 -163.2 -169.6 -176.0 -181.3 -187.6 -192.9 -198.2 Normal Strength Driver Evaluation Conditions Typical Temperature (Tambient) VDDQ Process conditions 25 °C 2.5V typical process Minimum 70 °C 2.3V slow-slow process Maximum 0 °C 2.7V fast-fast process DOC # 14-02-044 Rev A ECN # 01-1116 The specifications of this device are subject to change without notice. For latest documentation, see http://www.nanoamp.com 56 NanoAmp Solutions, Inc. AC Characteristics NT5DS64M4CT, NT5DS32M8CT, NT5DS16M16CT NT5DS64M4CS, NT5DS32M8CS, NT5DS16M16CS (Notes 1-5 apply to the following Tables; Electrical Characteristics and DC Operating Conditions, AC Operating Conditions, IDD Specifications and Conditions, and Electrical Characteristics and AC Timing.) 1. All voltages referenced to VSS. 2. Tests for AC timing, IDD, and electrical, AC and DC characteristics, may be conducted at nominal reference/supply voltage levels, but the related specifications and device operation are guaranteed for the full voltage range specified. 3. Outputs measured with equivalent load. Refer to the AC Output Load Circuit below. 4. AC timing and IDD tests may use a VIL to VIH swing of up to 1.5V in the test environment, but input timing is still referenced to VREF (or to the crossing point for CK, CK), and parameter specifications are guaranteed for the specified AC input levels under normal use conditions. The minimum slew rate for the input signals is 1V/ns in the range between VIL(AC) and VIH(AC). 5. The AC and DC input level specifications are as defined in the SSTL_2 Standard (i.e. the receiver effectively switches as a result of the signal crossing the AC input level, and remains in that state as long as the signal does not ring back above (below) the DC input low (high) level. AC Output Load Circuit Diagrams VTT 50 Ω Output (VOUT) Timing Reference Point 30pF DOC # 14-02-044 Rev A ECN # 01-1116 The specifications of this device are subject to change without notice. For latest documentation, see http://www.nanoamp.com 57 NanoAmp Solutions, Inc. AC Input Operating Conditions NT5DS64M4CT, NT5DS32M8CT, NT5DS16M16CT NT5DS64M4CS, NT5DS32M8CS, NT5DS16M16CS (0 °C ≤ TA ≤ 70 °C; VDDQ = VDD = 2.5V ± 0.2V (DDR333); VDDQ = VDD = 2.6V ± 0.1V (DDR400); See AC Characteristics) Symbol VIH(AC) VIL(AC) VID(AC) VIX(AC) 1. 2. 3. 4. Parameter/Condition Input High (Logic 1) Voltage, DQ, DQS, and DM Signals Input Low (Logic 0) Voltage, DQ, DQS, and DM Signals Input Differential Voltage, CK and CK Inputs Input Crossing Point Voltage, CK and CK Inputs Min VREF + 0.31 Max Unit V Notes 1, 2 1, 2 1, 2, 3 1, 2, 4 VREF − 0.31 0.62 0.5*VDDQ − 0.2 VDDQ + 0.6 0.5*VDDQ + 0.2 V V V Input slew rate = 1V/ns. Inputs are not recognized as valid until VREF stabilizes. VID is the magnitude of the difference between the input level on CK and the input level on CK. The value of VIX is expected to equal 0.5*VDDQ of the transmitting device and must track variations in the DC level of the same. IDD Specifications and Conditions Symbol (0 °C ≤ TA ≤ 70 °C; VDDQ = VDD = 2.5V ± 0.2V (DDR333); VDDQ = VDD = 2.6V ± 0.1V (DDR400); See AC Characteristics) Parameter/Condition Operating Current: one bank; active / precharge; tRC = tRC (min); DQ, DM, and DQS inputs changing twice per clock cycle; address and control inputs changing once per clock cycle Operating Current: one bank; active / read / precharge; Burst = 2; tRC = tRC (min); CL = 2.5; IOUT = 0mA; address and control inputs changing once per clock cycle Precharge Power Down Standby Current: all banks idle; Power Down mode; CKE ≤ VIL (max) Idle Standby Current: CS ≥ VIH (min); all banks idle; CKE ≥ VIH (min); address and control inputs changing once per clock cycle Active Power Down Standby Current: one bank active; Power Down mode; CKE ≤ VIL (max) Active Standby Current: one bank; active / precharge; CS ≥ VIH (min); CKE ≥ VIH (min); tRC = tRAS (max); DQ, DM, and DQS inputs changing twice per clock cycle; address and control inputs changing once per clock cycle Operating Current: one bank; Burst = 2; reads; continuous burst; address and control inputs changing once per clock cycle; DQ and DQS outputs changing twice per clock cycle; CL = 2.5; IOUT = 0mA Operating Current: one bank; Burst = 2; writes; continuous burst; address and control inputs changing once per clock cycle; DQ and DQS inputs changing twice per clock cycle; CL = 2.5 Auto-Refresh Current: tRC = tRFC (min) Self-Refresh Current: CKE ≤ 0.2V Operating current: four bank; four bank interleaving with BL = 4, address and control inputs randomly changing; 50% of data changing at every transfer; t RC = t RC (min); I OUT = 0mA. DDR400 DDR333 (5T) (6K) tCK=5ns tCK=6ns 76 68 Unit Notes IDD0 mA 1 IDD1 79 72 mA 1 IDD2P IDD2N 4 29 4 25 mA mA 1 1 IDD3P 11 10 mA 1 IDD3N 46 39 mA 1 IDD4R 105 87 mA 1 IDD4W IDD5 IDD6 119 124 2 98 118 2 mA mA mA 1 1 1, 2 IDD7 246 207 mA 1 1. IDD specifications are tested after the device is properly initialized. 2. Enables on-chip refresh and address counters. Device testing was performed with x16 wide devices. DOC # 14-02-044 Rev A ECN # 01-1116 The specifications of this device are subject to change without notice. For latest documentation, see http://www.nanoamp.com 58 NanoAmp Solutions, Inc. NT5DS64M4CT, NT5DS32M8CT, NT5DS16M16CT NT5DS64M4CS, NT5DS32M8CS, NT5DS16M16CS Electrical Characteristics & AC Timing - Absolute Specifications (0 °C ≤ TA ≤ 70 °C; VDDQ = VDD = 2.5V ± 0.2V (DDR333); VDDQ = VDD = 2.6V ± 0.1V (DDR400); See AC Characteristics) (Part 1 of 2) DDR333 (6K) Symbol Parameter DDR400 (5T) Min Max + 0.65 + 0.55 0.55 0.55 12 8 Unit Notes Min − 0.70 − 0.60 0.45 0.45 6 6 0.45 0.45 2.2 1.75 Max + 0.70 + 0.60 0.55 0.55 12 8 ns ns ns ns + 0.7 + 0.7 + 0.45 ns ns ns tCK tCK 0.55 tCK tCK tCK tCK tCK tCK ns ns 0.60 tCK tCK ns ns ns ns 1-4, 15, 16 1-4, 15, 16 2-4, 12 1-4 1-4, 5 1-4, 5 1-4 1-4 1-4 1-4 1-4 1-4 1-4 1-4 1-4 1-4 1-4, 7 1-4, 6 1-4 2-4, 9, 11, 12 2-4, 9, 11, 12 2-4, 10, 11, 12, 14 2-4, 10, 11, 12, 14 ns 1-4 ns ns tCK tCK 1-4 1-4 1-4 1-4 tAC tDQSCK tCH tCL DQ output access time from CK/CK DQS output access time from CK/CK CK high-level width CK low-level width CL = 2 − 0.65 − 0.55 0.45 0.45 5 5 0.40 0.40 2.2 1.75 − 0.65 − 0.65 tCK Clock cycle time CL = 2.5 CL=3 tDH tDS tIPW tDIPW tHZ tLZ tDQSQ tHP tQH tQHS tDQSS tDQSH tDQSL tDSS tDSH tMRD tWPRES tWPST tWPRE tIH tIS tIH tIS DQ and DM input hold time DQ and DM input setup time Input pulse width DQ and DM input pulse width (each input) Data-out high-impedance time from CK/CK Data-out low-impedance time from CK/CK DQS-DQ skew (DQS & associated DQ signals) Minimum half clk period for any given cycle; defined by clk high (tCH) or clk low (tCL) time Data output hold time from DQS Data hold Skew Factor Write command to 1st DQS latching transition DQS input high pulse width (write cycle) DQS input low pulse width (write cycle) DQS falling edge to CK setup time (write cycle) DQS falling edge hold time from CK (write cycle) Mode register set command cycle time Write preamble setup time Write postamble Write preamble Address and control input hold time (fast slew rate) Address and control input setup time (fast slew rate) Address and control input hold time (slow slew rate) Address and control input setup time (slow slew rate) + 0.65 + 0.65 + 0.40 − 0.7 − 0.7 min (tCL, tCH) tHP - tQHS 0.5 0.75 0.35 0.35 0.2 0.2 12 0 0.40 0.25 0.6 0.6 0.65 0.65 0.60 1.25 min (tCL, tCH) tHP - tQHS 0.75 0.35 0.35 0.2 0.2 12 0 0.40 0.25 0.75 0.75 0.8 0.8 1.25 DOC # 14-02-044 Rev A ECN # 01-1116 The specifications of this device are subject to change without notice. For latest documentation, see http://www.nanoamp.com 59 NanoAmp Solutions, Inc. NT5DS64M4CT, NT5DS32M8CT, NT5DS16M16CT NT5DS64M4CS, NT5DS32M8CS, NT5DS16M16CS Electrical Characteristics & AC Timing - Absolute Specifications (0 °C ≤ TA ≤ 70 °C; VDDQ = VDD = 2.5V ± 0.2V (DDR333); VDDQ = VDD = 2.6V ± 0.1V (DDR400); See AC Characteristics) (Part 2 of 2) DDR333 (6K) Symbol Parameter DDR400 (5T) Min Max 5.5 3.0 40 55 65 15 min (tRCD, tRAS) 15 12 15 (tWR/tCK) + (tRP/tCK) 12 6 75 200 7.8 60 72 18 Unit Notes Min 0.9 0.40 Max 1.1 0.60 42 ns ns ns ns ns ns ns ns ns ns tCK ns ns ns tCK 7.8 µs 1-4 1-4 1-4 1-4 1-4 1-4 1-4 1-4 1-4 1-4 1-4, 13 1-4 1-4 1-4 1-4 1-4, 8 tRPRE tRPST tRAS tRC tRFC tRCD tRAP tRP tRRD tWR tDAL tWTR tPDEX tXSNR tXSRD tREFI Read preamble Read postamble Active to Precharge Active to Active/Auto-refresh command period Auto-refresh to Active/Auto-refresh command period Active to Read or Write delay Active to Read Command with Autoprecharge Precharge command period Active bank A to Active bank B command Write recovery time Auto precharge write recovery + precharge time Internal write to read command delay Power down exit time Exit self-refresh to non-read command Exit self-refresh to read command Average Periodic Refresh Interval 4.5 2.0 min (tRCD, tRAS) 18 12 15 (tWR/tCK) + (tRP/tCK) 12 6 75 200 DOC # 14-02-044 Rev A ECN # 01-1116 The specifications of this device are subject to change without notice. For latest documentation, see http://www.nanoamp.com 60 NanoAmp Solutions, Inc. NT5DS64M4CT, NT5DS32M8CT, NT5DS16M16CT NT5DS64M4CS, NT5DS32M8CS, NT5DS16M16CS Electrical Characteristics & AC Timing - Absolute Specifications Notes 1. Input slew rate = 1V/ns. 2. The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross; the input reference level for signals other than CK/CK is VREF. 3. Inputs are not recognized as valid until VREF stabilizes. 4. The Output timing reference level, as measured at the timing reference point indicated in AC Characteristics (Note 3) is VTT. 5. tHZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not referred to a specific voltage level, but specify when the device is no longer driving (HZ), or begins driving (LZ). 6. The maximum limit for this parameter is not a device limit. The device operates with a greater value for this parameter, but system performance (bus turnaround) degrades accordingly. 7. The specific requirement is that DQS be valid (high, low, or some point on a valid transition) on or before this CK edge. A valid transition is defined as monotonic and meeting the input slew rate specifications of the device. When no writes were previously in progress on the bus, DQS will be transitioning from Hi-Z to logic LOW. If a previous write was in progress, DQS could be HIGH, LOW, or transitioning from high to low at this time, depending on tDQSS. 8. A maximum of eight Autorefresh commands can be posted to any given DDR SDRAM device. 9. For command/address input slew rate ≥ 1.0V/ns. Slew rate is measured between VOH (AC) and VOL (AC). 10. For command/address input slew rate ≥ 0.5V/ns and < 1.0V/ns. Slew rate is measured between VOH (AC) and VOL (AC). 11. CK/CK slew rates are ≥ 1.0V/ns. 12. These parameters guarantee device timing, but they are not necessarily tested on each device, and they may be guaranteed by design or tester characterization. 13. For each of the terms in parentheses, if not already an integer, round to the next highest integer. tCK is equal to the actual system clock cycle time. For example, for DDR266 at CL = 2.5, tDAL = (15ns/7.5ns) + (20ns/7.5ns) = 2 + 3 = 5. DOC # 14-02-044 Rev A ECN # 01-1116 The specifications of this device are subject to change without notice. For latest documentation, see http://www.nanoamp.com 61 NanoAmp Solutions, Inc. rate is below 0.5 V/ns. Input Slew Rate 0.5 V/ns 0.4 V/ns 0.3 V/ns delta (tIS) 0 +50 +100 NT5DS64M4CT, NT5DS32M8CT, NT5DS16M16CT NT5DS64M4CS, NT5DS32M8CS, NT5DS16M16CS 14. An input setup and hold time derating table is used to increase tIS and tIH in the case where the input slew delta (tIH) 0 0 0 Unit ps ps ps Notes 1,2 1,2 1,2 1. Input slew rate is based on the lesser of the slew rates determined by either V IH (AC) to V IL (AC) or V IH (DC) to V IL (DC), similarly for rising transitions. 2. These derating parameters may be guaranteed by design or tester characterization and are not necessarily tested on each device. 15. An input setup and hold time derating table is used to increase tDS and tDH in the case where the I/O slew rate is below 0.5 V/ns. Input Slew Rate 0.5 V/ns 0.4 V/ns 0.3 V/ns delta (tDS) 0 +75 +150 delta (tDH) 0 +75 +150 Unit ps ps ps Notes 1,2 1,2 1,2 1. I/O slew rate is based on the lesser of the slew rates determined by either V IH (AC) to V IL (AC) or V IH (DC) to V IL (DC), similarly for rising transitions. 2. These derating parameters may be guaranteed by design or tester characterization and are not necessarily tested on each device. 16. An I/O Delta Rise, Fall Derating table is used to increase tDS and tDH in the case where DQ, DM, and DQS slew rates differ. Input Slew Rate 0.0 V/ns 0.25 V/ns 0.5 V/ns delta (tDS) 0 +50 +100 delta (tDH) 0 +50 +100 Unit ps ps ps Notes 1,2,3,4 1,2,3,4 1,2,3,4 1. Input slew rate is based on the lesser of the slew rates determined by either V IH (AC) to V IL (AC) or V IH (DC) to V IL (DC), similarly for rising transitions. 2. Input slew rate is based on the larger of AC to AC delta rise, fall rate and DC to DC delta rise, fall rate. 3. The delta rise, fall rate is calculated as: [1/(slew rate 1)] - [1/(slew rate 2)] For example: slew rate 1 = 0.5 V/ns; slew rate 2 = 0.4 V/ns Delta rise, fall = (1/0.5) - (1/0.4) [ns/V] = -0.5 ns/V Using the table above, this would result in an increase in t DS and t DH of 100 ps. 4. These derating parameters may be guaranteed by design or tester characterization and are not necessarily tested on each device. DOC # 14-02-044 Rev A ECN # 01-1116 The specifications of this device are subject to change without notice. For latest documentation, see http://www.nanoamp.com 62 NanoAmp Solutions, Inc. Data Input (Write) (Timing Burst Length = 4) NT5DS64M4CT, NT5DS32M8CT, NT5DS16M16CT NT5DS64M4CS, NT5DS32M8CS, NT5DS16M16CS tDSL tDSH DQS tDH tDS DQ DI n tDH tDS DM DI n = Data In for column n. 3 subsequent elements of data in are applied in programmed order following DI n. Don’t Care Data Output (Read) CK CK DQS tHP (Timing Burst Length = 4) tHP tHP tHP1 tHP2 tHP3 tHP4 tDQSQ tQH1 DQ tDQSQ tQH2 tDQSQ tQH3 tQH4 tDQSQ tHP is the half cycle pulse width for each half cycle clock. tHP is referenced to the clock duty cycle only and not to the data strobe (DQS) duty cycle. Data Output hold time from Data Strobe is shown as tQH. tQH is a function of the clock high or low time (tHP) for that given clock cycle. Note correlation of tHP to tQH in the diagram above (tHP1 to tQH1, etc.). tDQSQ (max) occurs when DQS is the earliest among DQS and DQ signals to transition. DOC # 14-02-044 Rev A ECN # 01-1116 The specifications of this device are subject to change without notice. For latest documentation, see http://www.nanoamp.com 63 VDD * VTT is not applied directly to the device, however tVTD must be greater than or equal to zero to avoid device latchup. ** tMRD is required before any command can be applied and 200 cycles of CK are required before a Read command can be applied. The two Autorefresh commands may be moved to follow the first MRS, but precede the second Precharge All command. VDDQ tVTD VTT (System*) VREF tCK tCH tCL tMRD tMRD tRP tRFC tRFC tMRD NanoAmp Solutions, Inc. DOC # 14-02-044 Rev A ECN # 01-1116 200 cycles of CK** Initialize and Mode Register Sets CK CK tIH tIS 200µs CKE tIH tIS NOP PRE EMRS MRS PRE AR AR MRS LVCMOS LOW LEVEL Command ACT DM tIH tIS CODE tIH tIS CODE CODE tIS tIS CODE RA tIH tIH CODE CODE RA The specifications of this device are subject to change without notice. For latest documentation, see http://www.nanoamp.com A0-A9, A11 A10 ALL BANKS tIH tIS BA0=H BA1=L BA0=L BA1=L ALL BANKS BA0, BA1 BA0=L BA1=L BA High-Z DQS High-Z DQ NT5DS64M4CT, NT5DS32M8CT, NT5DS16M16CT NT5DS64M4CS, NT5DS32M8CS, NT5DS16M16CS Don’t Care Power-up: VDD and CK stable Extended Mode Register Set Load Mode Register, Reset DLL Load Mode Register (with A8 = L) 64 Power Down Mode CK tCK tCH tCL tPDEX CK tIH tIS tIS NanoAmp Solutions, Inc. DOC # 14-02-044 Rev A ECN # 01-1116 tIH NOP NOP VALID tIH VALID Enter Power Down Mode tIS CKE tIS Command VALID* tIS ADDR VALID DQS DQ The specifications of this device are subject to change without notice. For latest documentation, see http://www.nanoamp.com DM Exit Power Down Mode NT5DS64M4CT, NT5DS32M8CT, NT5DS16M16CT NT5DS64M4CS, NT5DS32M8CS, NT5DS16M16CS No column accesses are allowed to be in progress at the time power down is entered. * = If this command is a Precharge (or if the device is already in the idle state) then the power down mode shown is Precharge power down. If this command is an Active (or if at least one row is already active), then the power down mode shown is Active power down. Don’t Care 65 tRP tCH tCK tRFC tRFC tCL Auto Refresh Mode CK CK NanoAmp Solutions, Inc. tIH DOC # 14-02-044 Rev A ECN # 01-1116 VALID VALID PRE NOP NOP AR NOP AR NOP NOP ACT RA RA RA tIH tIS BA tIS CKE tIH tIS Command NOP A0-A8 A9, A11,A12 ALL BANKS A10 ONE BANK The specifications of this device are subject to change without notice. For latest documentation, see http://www.nanoamp.com BA0, BA1 BANK(S) DQS DQ DM PRE = Precharge; ACT = Active; RA = Row address; BA = Bank address; AR = Autorefresh. NOP commands are shown for ease of illustration; other valid commands may be possible at these times. DM, DQ, and DQS signals are all don't care/high-Z for operations shown. NT5DS64M4CT, NT5DS32M8CT, NT5DS16M16CT NT5DS64M4CS, NT5DS32M8CS, NT5DS16M16CS Don’t Care 66 Clock must be stable before exiting Self Refresh Mode tRP* tCK tCH tCL Self Refresh Mode 200 cycles NanoAmp Solutions, Inc. DOC # 14-02-044 Rev A ECN # 01-1116 tIH tIS tIS tIH tXSRD, tXSRN AR NOP VALID tIH tIS VALID CK CK tIS CKE tIS Command NOP ADDR DQS DQ The specifications of this device are subject to change without notice. For latest documentation, see http://www.nanoamp.com DM Enter Self Refresh Mode Exit Self Refresh Mode NT5DS64M4CT, NT5DS32M8CT, NT5DS16M16CT NT5DS64M4CS, NT5DS32M8CS, NT5DS16M16CS * = Device must be in the all banks idle state before entering Self Refresh Mode. ** = tXSNR is required before any non-read command can be applied, and tXSRD (200 cycles of CK). are required before a Read command can be applied. Don’t Care 67 tCK tCH tRP tCL CK CK tIH tIS VALID tIH tIS NOP NOP PRE NOP NOP ACT NOP NOP NOP tIH tIS Read VALID VALID tIH CKE NanoAmp Solutions, Inc. DOC # 14-02-044 Rev A ECN # 01-1116 COL n RA tIH tIS Command A0-A9, A11, A12 ALL BANKS RA A10 DIS AP ONE BANK tIH tIS BA x BA x* BA x BA0, BA1 Read without Auto Precharge (Burst Length = 4) DM tLZ (min) tRPRE DQS tAC (min) tRPST tDQSCK (min) tHZ (min) Case 1: tAC/tDQSCK = min CL=2 DO n tLZ (max) tRPRE The specifications of this device are subject to change without notice. For latest documentation, see http://www.nanoamp.com tAC (max) tLZ (max) tHZ (max) tRPST tDQSCK (max) DQ DQS Case 2: tAC/tDQSCK = max DQ DO n DO n = data out from column n. 3 subsequent elements of data out are provided in the programmed order following DO n. Don’t Care DIS AP = Disable Auto Precharge. * = Don't care if A10 is High at this point. PRE = Precharge; ACT = Active; RA = Row address; BA = Bank address. NT5DS64M4CT, NT5DS32M8CT, NT5DS16M16CT NT5DS64M4CS, NT5DS32M8CS, NT5DS16M16CS NOP commands are shown for ease of illustration; other commands may be valid at these times. 68 tCK tCH tRP tCL CK CK tIH tIS VALID tIH tIS VALID VALID tIH CKE NanoAmp Solutions, Inc. Command tIH tIS COL n tIH tIS RA RA DOC # 14-02-044 Rev A ECN # 01-1116 NOP Read NOP NOP NOP NOP ACT NOP NOP NOP A0-A9, A11, A12 A10 EN AP tIH tIS BA x BA x BA0, BA1 Read with Auto Precharge (Burst Length = 4) DM tLZ (min) tRPRE DQS tHZ (min) tAC (min) tRPST tDQSCK (min) tHZ (min) Case 1: tAC/tDQSCK = min CL=2 DO n tLZ (max) tRPRE The specifications of this device are subject to change without notice. For latest documentation, see http://www.nanoamp.com tAC (max) tLZ (max) tHZ (max) tRPST tDQSCK (max) DQ DQS Case 2: tAC/tDQSCK = max DQ DO n NT5DS64M4CT, NT5DS32M8CT, NT5DS16M16CT NT5DS64M4CS, NT5DS32M8CS, NT5DS16M16CS DO n = data out from column n. 3 subsequent elements of data out are provided in the programmed order following DO n. EN AP = enable Auto Precharge. ACT = active; RA = row address. NOP commands are shown for ease of illustration; other commands may be valid at these times. Don’t Care 69 tCK tCH tCL CK CK tIH tIS VALID tIH tIS NOP NOP Read NOP PRE NOP NOP ACT NOP tIH tIS RA COL n tIH tIS ALL BANKS RA ONE BANK RA ACT tRC CKE NanoAmp Solutions, Inc. DOC # 14-02-044 Rev A ECN # 01-1116 RA DIS AP tIH tIS BA x BA x BA x* BA x Command A0-A9, A11, A12 Bank Read Access (Burst Length = 4) A10 BA0, BA1 DM tLZ (min) tRPRE tRP DQS tRCD tRAS tLZ (min) tAC (min) tHZ (min) tRPST tDQSCK (min) Case 1: tAC/tDQSCK = min CL=2 DO n tLZ (max) tRPRE The specifications of this device are subject to change without notice. For latest documentation, see http://www.nanoamp.com tHZ (max) tAC (max) tLZ (max) tRPST tDQSCK (max) DQ DQS Case 2: tAC/tDQSCK = max DQ DO n NT5DS64M4CT, NT5DS32M8CT, NT5DS16M16CT NT5DS64M4CS, NT5DS32M8CS, NT5DS16M16CS DO n = data out from column n. 3 subsequent elements of data out are provided in the programmed order following DO n. DIS AP = disable Auto Precharge. * = Don't care if A10 is High at this point. PRE = Precharge; ACT = Active; RA = Row address; BA = Bank address. NOP commands are shown for ease of illustration; other commands may be valid at these times. Don’t Care 70 tCH tCK tCL tRP tWR CK CK tIH tIH VALID tIS CKE tIH NanoAmp Solutions, Inc. tIS Write NOP NOP NOP NOP PRE NOP NOP ACT DOC # 14-02-044 Rev A ECN # 01-1116 tIH tIS COL n RA tIH tIS Command NOP A0-A9, A11, A12 ALL BANKS RA A10 ONE BANK tIH tIS BA x tWPRE tWPRES tDQSH tDQSS tWPST tDQSL tDSH BA x* Write without Auto Precharge (Burst Length = 4) DIS AP The specifications of this device are subject to change without notice. For latest documentation, see http://www.nanoamp.com BA DIn BA0, BA1 DQS DQ DM NT5DS64M4CT, NT5DS32M8CT, NT5DS16M16CT NT5DS64M4CS, NT5DS32M8CS, NT5DS16M16CS tDQSS = min. DIn = Data in for column n. 3 subsequent elements of data in are applied in the programmed order following DIn. DIS AP = Disable Auto Precharge. * = Don't care if A10 is High at this point. PRE = Precharge; ACT = Active; RA = Row address; BA = Bank address. NOP commands are shown for ease of illustration; other valid commands may be possible at these times. Don’t Care 71 tCH tCK tCL tRP tWR CK CK tDAL tIH tIS VALID VALID VALID CKE tIH NanoAmp Solutions, Inc. DOC # 14-02-044 Rev A ECN # 01-1116 Write NOP NOP NOP NOP NOP NOP NOP ACT tIH tIS COL n tIH tIS RA tIS Command NOP A0-A9, A11, A12 Write with Auto Precharge (Burst Length = 4) A10 tIH tIS BA x EN AP RA BA0, BA1 BA tWPRES tDSH tDQSS tDQSL tDQSH tWPST The specifications of this device are subject to change without notice. For latest documentation, see http://www.nanoamp.com DIn tWPRE DQS DQ DM tDQSS = min. NT5DS64M4CT, NT5DS32M8CT, NT5DS16M16CT NT5DS64M4CS, NT5DS32M8CS, NT5DS16M16CS DIn = Data in for column n. 3 subsequent elements of data in are applied in the programmed order following DIn. EN AP = Enable Auto Precharge. ACT = Active; RA = Row address; BA = Bank address. NOP commands are shown for ease of illustration; other valid commands may be possible at these times. Don’t Care 72 tCH tCK tCL CK CK tIH tIS VALID CKE tRAS tIH NanoAmp Solutions, Inc. DOC # 14-02-044 Rev A ECN # 01-1116 ACT NOP Write NOP NOP NOP NOP PRE NOP tIH tIS RA Col n tIS Command NOP Bank Write Access (Burst Length = 4) A0-A9, A11, A12 tIH tIS RA ALL BANKS ONE BANK A10 tIH tIS BA x BA x tRCD tWPRES tDQSH tDQSS tDQSL tWPST tDSH DIS AP BA0, BA1 BA x The specifications of this device are subject to change without notice. For latest documentation, see http://www.nanoamp.com tWR DIn tWPRE DQS DQ DM NT5DS64M4CT, NT5DS32M8CT, NT5DS16M16CT NT5DS64M4CS, NT5DS32M8CS, NT5DS16M16CS tDQSS = min. DI n = data in for column n. 3 subsequent elements of data in are applied in the programmed order following DI n. DIS AP = Disable Auto Precharge. * = don't care if A10 is High at this point. PRE = Precharge; ACT = Active; RA = Row address. NOP commands are shown for ease of illustration; other valid commands may be possible at these times. Don’t Care 73 tCH tCK tCL CK CK tIH tIS VALID CKE tIH NanoAmp Solutions, Inc. DOC # 14-02-044 Rev A ECN # 01-1116 Write NOP NOP NOP NOP PRE NOP NOP ACT tIH tIS COL n RA tIS Command NOP A0-A9, A11, A12 tIH tIS Write DM Operation (Burst Length = 4) ALL BANKS RA A10 ONE BANK tIH tIS BA x BA x* DIS AP BA0, BA1 BA tWPRES tDQSH tDQSS tDQSL tWPST tDSH The specifications of this device are subject to change without notice. For latest documentation, see http://www.nanoamp.com tWR tRP DIn DQS DQ DM NT5DS64M4CT, NT5DS32M8CT, NT5DS16M16CT NT5DS64M4CS, NT5DS32M8CS, NT5DS16M16CS DI n = data in for column n. 3 subsequent elements of data in are applied in the programmed order following DI n (the second element of the 4 is masked). DIS AP = Disable Auto Precharge. * = Don't care if A10 is High at this point. PRE = Precharge; ACT = Active; RA = Row address; BA = Bank address. NOP commands are shown for ease of illustration; other valid commands may be possible at these times. tDQSS = min. Don’t Care 74 NanoAmp Solutions, Inc. NT5DS64M4CT, NT5DS32M8CT, NT5DS16M16CT NT5DS64M4CS, NT5DS32M8CS, NT5DS16M16CS Package Dimensions (400mil; 66 lead; Thin Small Outline Package) Detail A 22.22 ± 0.10 10.16 ±. 0.13 Lead #1 11.76 ± 0.20 Seating Plane 0.10 0.25 Basic Gage Plane 0.65 Basic 0.30 + 0.03 - 0.08 0.71REF Detail A 1.20 Max 0.5 ± 0.1 0.05 Min DOC # 14-02-044 Rev A ECN # 01-1116 The specifications of this device are subject to change without notice. For latest documentation, see http://www.nanoamp.com 75 NanoAmp Solutions, Inc. NT5DS64M4CT, NT5DS32M8CT, NT5DS16M16CT NT5DS64M4CS, NT5DS32M8CS, NT5DS16M16CS Revision History Revision A Date January 2005 Change Description Initial datasheet © 2005 Nanoamp Solutions, Inc. All rights reserved. NanoAmp Solutions, Inc. ("NanoAmp") reserves the right to change or modify the information contained in this data sheet and the products described therein, without prior notice. NanoAmp does not convey any license under its patent rights nor the rights of others. Charts, drawings and schedules contained in this data sheet are provided for illustration purposes only and they vary depending upon specific applications. NanoAmp makes no warranty or guarantee regarding suitability of these products for any particular purpose, nor does NanoAmp assume any liability arising out of the application or use of any product or circuit described herein. NanoAmp does not authorize use of its products as critical components in any application in which the failure of the NanoAmp product may be expected to result in significant injury or death, including life support systems and critical medical instruments. DOC # 14-02-044 Rev A ECN # 01-1116 The specifications of this device are subject to change without notice. For latest documentation, see http://www.nanoamp.com 76