UPD17202AGF-011

PRELIMINARY DATA SHEET MOS INTEGRATED CIRCUIT µPD17202AGF-011 4-BIT SINGLE-CHIP MICROCONTROLLER WITH LCD CONTROLLER/DRIVER AND KEY SCAN CIRCUIT FOR FPC (FRONT PANEL CONTROLLER) The µPD17202AGF-011 is a CMOS microcontroller for the FPC (Front Panel Controller) of a car stereo system. This microcontroller is housed in a 64-pin QFP and is provided with an LCD controller/driver and key scan circuit, enabling the reduction of the amount of wiring between the front panel of the car stereo system and the master microcontroller. FEATURES • LCD controller/driver • Key scan circuit • LED output • Supply voltage • System clock : : : : : Can display up to 75 segments. 1/3 duty, 1/3 bias, frame frequency: 325.5 Hz Can read up to 30 (5 × 6) keys. 1 pin CLOCK, DATA, and LOAD pins VDD = 4.5 to 5.5 V fX = 8 MHz • 3-wire serial communication mode : ORDERING INFORMATION Part Number Package 64-pin plastic QFP (14 × 20 mm, 1.0-mm pitch) µPD17202AGF-011-3BE The information in this document is subject to change without notice. Document No. U12127EJ1V0DS00 (1st edition) Date Published May 1997 N Printed in Japan © 1997 µPD17202AGF-011 PIN CONFIGURATION (Top View) 64-pin plastic QFP (14 × 20 mm, 1.0-mm pitch) µPD17202AGF-011-3BE LCD24 LCD23 LCD22 LCD21 LCD20 LCD19 LCD18 LCD17 LCD16 LCD15 LCD14 LCD13 LCD12 LCD11 LCD10 LCD9 LCD8 LCD7 LCD6 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 64 63 62 61 60 59 58 57 56 55 54 53 52 IC(VREG) GND1 VLCD1 VLCD0 VLCDC IC(VDET) COM2 COM1 COM0 CAPH CAPL VLCD2 IC(XTOUT) 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 IC (XTIN) IC (WDOUT) RESET XOUT XIN VDD IC (REM) IC (TMOUT/LED) DATA (P0D3) BLANK (P0D2) KS4 (P0D1) KS3 (P0D0) KS2 (P0C3) KS1 (P0C2) KS0 (P0C1) LED (P0C0) INT (P0B3) K5 (P0B2) K4 (P0B1) 20 21 22 23 24 25 26 27 28 29 30 31 32 33 CLOCK (INT) K0 (P0A1) K1 (P0A2) K2 (P0A3) Remarks 1. IC: Internally Connected 2. ( ): Pin names of µPD17202AGF-×××-3BE 2 LOAD (P0A0) K3 (P0B0) LCD5 LCD4 LCD3 LCD2 LCD1 LCD0 GND0 µPD17202AGF-011 CONTENTS 1. PIN FUNCTION ............................................................................................................................. 1.1 Pin Function List .................................................................................................................. 2. CONFIGURATION OF KEY MATRIX .......................................................................................... 2.1 Layout of Key Matrix ............................................................................................................ 2.2 Connection of Key Matrix .................................................................................................... 3. KEY SCAN .................................................................................................................................... 3.1 Key Scan Function ............................................................................................................... 3.2 Data Configuration ............................................................................................................... 4. LCD DISPLAY FUNCTION .......................................................................................................... 4.1 Configuration of LCD Data Segment and LCD Panel Display Data ................................. 4.2 LCD Display Data Configuration ........................................................................................ 5. SERIAL DATA COMMUNICATION .............................................................................................. 5.1 Serial Data Input ................................................................................................................... 5.2 Serial Data Output ................................................................................................................ 5.3 Timing Chart of Serial Data Communication ..................................................................... 6. APPLICATION CIRCUIT EXAMPLE ............................................................................................ 7. ELECTRICAL SPECIFICATIONS (preliminary) ......................................................................... 8. PACKAGE DRAWINGS ................................................................................................................. 4 4 6 6 7 8 8 9 10 10 12 13 14 15 16 19 20 25 3 µPD17202AGF-011 1. PIN FUNCTION 1.1 Pin Function List Pin No. 1 to 25 Symbol LCD24 to LCD0 Pin Name LCD segment signal output Description These pins output segment signals to an LCD panel. They are used to control the display on the LCD panel by forming a matrix with COM0 through COM2 (pins 62 through 64). Ground pin I/O Format CMOS pushpull output 26 58 27 GND0 GND1 CLOCK Ground – Clock input Serial communication clock input. Data is input to or output from the DATA pin (pin 43) at the rising edge of the clock input to this pin. Serial communication load input. Commands are executed and the output status is cleared in synchronization with the rising edge of this pin. While this pin is high, clock input is invalid. This pin is connected to an internal pull-up resistor. These pins input key return signals from a key matrix. These pins are connected to an internal pull-down resistor. Input 28 LOAD Load input Input 29 to 34 35 K0 to K5 INT Key return signal input Input Key scan end signal output This pin outputs a key scan end signal to the master microcontroller. It goes high when key scanning has ended after execution of a key data output command. This pin goes low at the rising edge of the LOAD pin (pin 28) after data has been output. While this pin is low, key data cannot be correctly output. The initial value of this pin is the low level. Be sure to connect a pull-down resistor to this pin. This pin is connected to an LED that is used to check connection with the master microcontroller. When this pin is low, the LED lights. This pin is output depending on the LED data value of display data input (data A, refer to 4.2 LCD Display Data Configuration). This pin is floated in the initial status. 5V CMOS pushpull output 36 LED LED output N-ch opendrain output µ PD17202AGF-011 LED 36 37 to 41 KS0 to KS4 Key source output These pins output key source signals to a key matrix. N-ch opendrain output 4 µPD17202AGF-011 Pin No. 42 Symbol BLANK Pin Name Blank input Description By connecting an external controller to this pin, the display of the LCD panel can be turned ON/OFF. Input level Low High LCD display status Lights Extinguishes I/O Format Input To control this pin, connect it to an external controller via pull-up resistor; otherwise, connect it to GND via pull-down resistor. 43 DATA Serial data I/O Serial communication data I/O pin. This pin outputs data from the rising edge of the LOAD pin (pin 28) after a key data output signal has been received, to the next rising edge; otherwise, it inputs data. Connect nothing to these pins. Connect these pins to GND via pull-down resistor. Short-circuit pins 52 and 53. Connect this pin to VDD. VDD XIN XOUT Power supply Crystal resonator This is a common power supply pin (VDD = 2.2 to 5.5 V). These pins are used to connect a crystal resonator. Connect an 8-MHz ceramic oscillator or crystal resonator to these pins. The accuracy of the watch is influenced only by the oscillation frequency of the oscillator. Reset input LCD reference voltage adjustment Reset input. This pin is used to adjust the reference voltage for the LCD driver. Example VLCDC VLCD0 VLCD1 µ PD17202AGF-011 N-ch opendrain output 44, 45 50, 51 52, 53 54 46 47 48 IC Internally connected – – Input – 49 55 RESET VLCDC Input – 55 56 57 59 0.47µF 0.47µF 2 MΩ 60 0.47µF CAPL 0.47µF CAPH 61 VLCD2 56 57 59 60 61 VLCD0 VLCD1 VLCD2 CAPL CAPH LCD regulator LCD regulator pin. – LCD boosting capacitor These pins connect a capacitor used to boost the LCD driver voltage. Connect a capacitor of 0.47 µF between the CAPL and CAPH pins. These pins output the common signals of the LCD controller/driver. – 62 to 64 COM0 to COM2 Common signal output of LCD controller/driver CMOS 3state output 5 µPD17202AGF-011 2. CONFIGURATION OF KEY MATRIX 2.1 Layout of Key Matrix The µPD17202AGF-011 can be used to configure a key matrix of up to 30 keys, KEY0 through KEY29, by using the KS0 through KS4 pins (key source pins) and K0 through K5 pins (key return pins). Keys KEY0 through KEY29 are allocated as shown below. The details of each key can be set arbitrarily. Input Pin (Pin No.) K0 (29) Output Pin (Pin No.) KS0 (37) KS1 (38) KS2 (39) KS3 (40) KS4 (41) KEY0 KEY6 KEY12 KEY18 KEY24 KEY1 KEY7 KEY13 KEY19 KEY25 KEY2 KEY8 KEY14 KEY20 KEY26 KEY3 KEY9 KEY15 KEY21 KEY27 KEY4 KEY10 KEY16 KEY22 KEY28 KEY5 KEY11 KEY17 KEY23 KEY29 K1 (30) K2 (31) K3 (32) K4 (33) K5 (34) Remark Numbers in brackets ( ) are pin numbers. 6 µPD17202AGF-011 2.2 Connection of Key Matrix An example of connection of the key matrix is shown below. KSn Momentary key = Kn KS4 41 KS3 40 KS2 39 µ PD17202AGF-011 KS1 38 KS0 37 K5 34 K4 33 K0 29 K1 30 K2 31 K3 32 7 µPD17202AGF-011 3. KEY SCAN 3.1 Key Scan Function Key scanning is started when a key data output command is executed. The INT pin (pin 35) goes high when key scanning has ended. The INT pin goes low when the LOAD pin (pin 28) goes high. Figure 3-1. Timing Chart of Key Scanning 50 - 60 µ s KS0 KS1 KS2 KS3 KS4 1.6 - 1.9 ms (2.8 - 3.4 ms)Note INT Key data output command Scanning ends LOAD pin rises Key data output command Note The value in brackets ( ) is when “display data input + key data output” is executed. 8 µPD17202AGF-011 3.2 Data Configuration The data output by the key data output command consists of 30 bits. The contents of the output data are as shown below. Figure 3-2. Configuration of Output Data (Key Data Output) 30 bits MSB KKKKKK EEEEEE YYYYYY 29 28 27 26 25 24 KS4 ··· KKKKKK EEEEEE YYYYYY 17 16 15 14 13 12 KS2 ··· K E Y 5 K E Y 4 K E Y 3 K E Y 2 K E Y 1 LSB K E Y 0 KS0 The status of the output data can be identified by the data of each bit as shown below. Data 0 1 Status Key off Key on 9 µPD17202AGF-011 4. LCD DISPLAY FUNCTION 4.1 Configuration of LCD Data Segment and LCD Panel Display Data The segments consisting of LCD0 through LCD24 pins and COM0 through COM2 pins correspond to the LCD panel display data as shown in the table below. Table 4-1 Configuration of LCD Segment and Table 4-2 Display Data Table correspond to each other. Any LCD display setting can be performed based on these tables. Table 4-1. Configuration of LCD Segment Common Pin (Pin No.) COM0 (62) Segment Pin (Pin No.) LCD0 (25) LCD1 (24) LCD2 (23) LCD3 (22) LCD4 (21) LCD5 (20) LCD6 (19) LCD7 (18) LCD8 (17) LCD9 (16) LCD10 (15) LCD11 (14) LCD12 (13) LCD13 (12) LCD14 (11) LCD15 (10) LCD16 (9) LCD17 (8) LCD18 (7) LCD19 (6) LCD20 (5) LCD21 (4) LCD22 (3) LCD23 (2) LCD24 (1) B4 A3 A4 B9 A8 A9 B14 A13 A14 B19 A18 A19 B24 A23 A24 B33 B29 A28 A29 B34 A33 A34 B39 A38 A39 A0 A1 A2 A5 A6 A7 A10 A11 A12 A15 A16 A17 A20 A21 A22 B38 A25 A26 A27 A30 A31 A32 A35 A36 A37 B0 B1 B2 B5 B6 B7 B10 B11 B12 B15 B16 B17 B20 B21 B22 B28 B25 B26 B27 B30 B31 B32 B35 B36 B37 COM1 (63) COM2 (64) 10 µPD17202AGF-011 Table 4-2. Display Data Table Segment A Data Name D40 D39 D38 D37 D36 D35 D34 D33 D32 D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 B0 B1 B2 B3 Note B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 Note B14 B15 B16 B17 B18 Note B19 B20 B21 B22 B23 Note B24 B25 B26 B27 B28 B29 B30 Note Segment B Data Name D9 D8 D7 D6 D5 D4 D3 D2 D1 A31 A32 A33 A34 A35 A36 A37 A38 A39 B31 B32 B33 B34 B35 B36 B37 B38 B39 A B Note The data of segments B3, B8, B13, B18, and B23 are invalid. Do not input anything for these data. 11 µPD17202AGF-011 4.2 LCD Display Data Configuration LCD display data is divided into two parts, A and B, for transmission (refer to Table 4-2 Display Data Table). The data consists of a command (4 bits), LCD data (40 bits), and LED data (1 bit), or a total of 45 bits (only when data A is transmitted. Data B consists of 44 bits, excluding LED data (1 bit)). Figure 4-1. Configuration of Input Data for LCD Display MSB b 3 b 2 b 1 b 0 DDD 40 39 38 D 3 D 2 D 1 LSB D 0 Command (4 bits) LCD data Data A or B (40 bits) LED data (1 bit) Note Note D0 (= LED data) is necessary only when data A is transmitted. The status of the data can be identified by the data of each bit (0 or 1) as shown below. Data 0 1 Status Extinguishers Lights The last 4 bits of the input data is read at the rising edge of the LOAD pin (pin 28) as a command, and the previous data is displayed on the LCD when display data input is identified. When a low level is input to the BLANK pin (pin 42), the LCD display is turned ON (the LED also lights when data A is transmitted). When a high level is input to the BLANK pin, the LCD display is turned OFF (refer to 5.2 Serial Data Output). Setting of the BLANK pin does not affect any operations other than the LCD display. The LCD display data is extinguished in the initial status (even if the BLANK pin is low level). The configuration of the LCD display data commands (4 bits of MSB) is shown below. Table 4-3. Serial Data I/O Commands Command Operation b3 0 0 0 0 0 1 1 Others b2 0 0 1 1 1 1 1 b1 1 1 0 1 1 0 1 b0 0 1 × 0 1 × × Inputs display data (data A) Inputs display data (data B) Outputs key data Inputs display data (A) + outputs key data Inputs display data (B) + outputs key data Outputs key data Outputs key data Setting prohibited ×: Undefined 12 µPD17202AGF-011 5. SERIAL DATA COMMUNICATION The µPD17202AGF-011 inputs or outputs data from or to the main microcontroller through 3-wire serial communication, using the CLOCK (pin 27), DATA (pin 43), and LOAD (pin 28) pins. Figure 5-1 shows connection between the µPD17202AGF-011 and main microcontroller. Figure 5-1. Connection between µPD17202AGF-011 and Main Microcontroller DATA DATA 43 LOAD µ PD17202AGF-011 Main microcontroller CLOCK CLOCK 27 LOAD 28 13 µPD17202AGF-011 5.1 Serial Data Input The serial data is input in synchronization with the rising of the CLOCK pin (pin 27) in the input status (the initial status is “input”). The last 4 bits read at the rising edge of the LOAD pin (pin 28) are identified and processed as a command. Figure 5-2 shows the timing chart of serial data input. Table 5-1 lists the serial data I/O commands. Figure 5-2. Timing Chart of Serial Data Input CLOCK LSB DATA D0 D1 b0 b1 b2 MSB b3 Input data (Last 4 bits are serial data input command) LOAD Table 5-1. Serial Data I/O Commands Command Operation b3 0 0 0 0 0 1 1 Others b2 0 0 1 1 1 1 1 b1 1 1 0 1 1 0 1 b0 0 1 × 0 1 × × Inputs display data (data A) Inputs display data (data B) Outputs key data Inputs display data (A) + outputs key data Inputs display data (B) + outputs key data Outputs key data Outputs key data Setting prohibited ×: Undefined Remarks 1. For the data configuration of display data input, refer to 4. LCD DISPLAY FUNCTION. 2. For the data configuration of key data output, refer to 3. KEY SCAN. 3. Execute display data input before key data output. 4. If a pulse is input to the LOAD pin without display data input, the device does not operate. 5. The device does not operate when data other than an I/O command is input. 14 µPD17202AGF-011 5.2 Serial Data Output Serial data is output in synchronization with the rising of the CLOCK pin (pin 27) in the output status (the output status is established only when the key data output command is executed). Serial data is output in the following procedure. Figure 5-3 shows the timing chart of serial data output. Input a key data output command. Input a pulse to the LOAD pin (pin 28) (the output status is established when this pin goes high). Input the clock (data is output in synchronization with the rising of the clock). Input a pulse to the LOAD pin (the input status is established when this pin goes high). Figure 5-3. Timing Chart of Serial Data Output CLOCK LSB DATA b0 b1 b2 b3 MSB LSB K0 K1 K28 MSB K29 Input data Input status LOAD Output data Output status Input status 15 µPD17202AGF-011 5.3 Timing Chart of Serial Data Communication The I/O timing charts of the respective pins during serial data communication are shown below. (1) Serial data I/O 100 ns 11.7 µ s MIN. MIN. 50 ns MAX. CLOCK 11.7 µ s MIN. DATA (input) 11.5 µ s MAX. DATA (output) 100 ns MIN. 50 µ s MIN. 23.4 µ s MIN. LOAD Remark Maximum clock frequency: 43 kHz (2) On reset execution 35 ms MIN. CLOCK 50 µ s MIN. RESET Clock 16 µPD17202AGF-011 (3) On execution of display data input CLOCK 41 or 40 clocks + 4 clocks Clock DATA Display data + command 2 ms MIN. 70 µ s MIN. Input data LOAD 2 ms MIN. Less than 2 ms BLANK Valid Invalid Valid Invalid BLANK pin (4) On execution of key data output CLOCK DATA LOAD 2 ms MIN. Less than 2 ms INT Less than 100 µ s BLANK BLANK pin                       Valid : The device operates within 50 µs after the value of the BLANK pin has been changed. If the clock is input to the CLOCK pin, however, the higher the clock frequency, the slower the operation (example: operates within 1 ms at 43 kHz). Invalid : The device does not operate even if the value of the BLANK pin has been changed. If the value of the pin is changed during this period, the device operates after the pin value has become valid. 4 clocks 30 clocks 100 µ s MIN. 1 clock Command 2 ms MIN. 70 µ s MIN. Key data 70 µ s MIN. Input data Valid Invalid Valid Invalid Invalid Valid : The device operates within 50 µs after the value of the BLANK pin has been changed. If the clock is input to the CLOCK pin, however, the higher the clock frequency, the slower the operation (example: operates within 1 ms at 43 kHz). Invalid : The device does not operate even if the value of the BLANK pin has been changed. If the value of the pin is changed during this period, the device operates after the pin value has become valid. 17 µPD17202AGF-011 (5) On execution of display data input + key data CLOCK 41 or 40 clocks + 4 clocks 30 clocks 100 µ s MIN. Clock DATA Display data + command 3.5 ms MIN. 70 µ s MIN. Key data 70 µ s MIN. Input data LOAD 3.5 ms MIN. Less than 3.5 ms INT Less than 100 µ s BLANK Valid Invalid Valid Invalid Invalid BLANK pin 18            Valid : The device operates within 50 µs after the value of the BLANK pin has been changed. If the clock is input to the CLOCK pin, however, the higher the clock frequency, the slower the operation (example: operates within 1 ms at 43 kHz). Invalid : The device does not operate even if the value of the BLANK pin has been changed. If the value of the pin is changed during this period, the device operates after the pin value has become valid. µPD17202AGF-011 6. APPLICATION CIRCUIT EXAMPLE CAPH CAPL VLCD2 GND VLCD1 VLCD0 VLCDC VDD COM0 COM1 COM2 64 63 62 61 60 59 58 57 56 55 54 53 52 LCD24 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 LCD6 19 RESET 51 50 49 XOUT 48 fx = 8 MHz XIN VDD 47 VDD 46 + 45 44 DATA 43 BLANK 42 KS4 41 40 VDD 39 38 KS0 37 LED 36 INT 35 K5 34 33 µ PD17202AGF-011-3BE LCD0 LCD panel LCD5 20 21 22 23 24 25 26 27 28 29 30 31 32 GND K0 K3 Momentary key switch CLOCK LOAD Connector Connector VDD BLANK CLK SIO Main microcontroller LOAD INT RES VDD GND 19 µPD17202AGF-011 7. ELECTRICAL SPECIFICATIONS (preliminary) Absolute Maximum Ratings (TA = 25 ˚C) Parameter Supply voltage Input voltage Output voltage High-level output current Symbol VDD VI VO IOH REM pin Peak r.m.s value 1 pin (other than REM pin) All pins (except REM pin) Low-level output current IOL 1 pin Peak r.m.s value Peak r.m.s value Peak r.m.s value All pins Peak r.m.s value Operating temperature Storage temperature TA Tstg Condition Rating –0.3 to +7.0 –0.3 to VDD + 0.3 –0.3 to VDD + 0.3 –30 –20 –7.5 –5.0 –22.5 –15.0 7.5 5.0 30 20 —20 to +75 –40 to +125 Unit V V V mA mA mA mA mA mA mA mA mA mA ˚C ˚C Caution If the rated value of even one of the above parameters is exceeded even momentarily, the quality of the product may be affected. The absolute maximum ratings, therefore, define the values exceeding which the product may be physically damaged. Be sure to use the product without ever exceeding these values. Capacitance (TA = 25 ˚C, VDD = 0 V) Parameter Input capacitance Symbol CIN CPIN Condition INT and RESET pins Other than INT and RESET pins MIN. TYP. MAX. 10 10 Unit pF pF 20 µPD17202AGF-011 Recommended Operation Range (TA = –20 to +75 ˚C) Parameter Supply voltage Symbol VDD0 VDD1 System clock oscillation frequency fX Condition Where system clock is fX = 4 MHz Where system clock is fX = 8 MHz MIN. 2.2 4.5 1.0 TYP. 3.0 5.0 4.0 MAX. 5.5 5.5 8.0 Unit V V MHz fX vs VDD (MHz) 10 9 8 7 6 5 System clock: fX 4 3 Operation guaranteed range 2 1 2.2 0.5 0 2 3 4 4.5 5 5.5 6 (V) Supply voltage: VDD 21 µPD17202AGF-011 System Clock Oscillation Circuit Characteristics (TA = –20 to +75 ˚C, VDD = 2.2 to 5.5 V) Recommended Constants Oscillator Ceramic resonator Note 1 Parameter Oscillation frequency (fX) Note 2 Condition MIN. 1.0 TYP. 4.0 MAX. 8.0 Unit MHz XIN XOUT Oscillation stabilization time Note 3 After VDD has reached MIN. value of oscillation voltage range 1.0 4.0 4 ms Crystal resonator Note 1 XIN XOUT Oscillation frequency (fX) Note 2 8.0 MHz Oscillation stabilization time Note 3 VDD = 4.5 to 6.0 V 10 30 ms ms Notes 1. Use of the ceramic resonator and crystal resonator shown on the next page is recommended. 2. The oscillation frequency only indicates the characteristics of the oscillation circuit. For the instruction execution time, refer to Recommended Operation Range. 3. The oscillation stabilization time is the time required for oscillation to stabilize after VDD application or release of the STOP mode. Caution When using the system clock oscillation circuit, wire the portion indicated by the dotted lines in the above figures to avoid adverse influence from wiring capacitance. • Keep the wiring length as short as possible. • Do not cross the wiring with any other signal lines. Do not route the wiring in the vicinity of a line through which a high alternating current flows. • Always keep the ground point of the capacitor of the oscillation circuit at the same potential as GND. Do not ground the capacitor to a ground pattern through which a high current flows. • Do not extract signals from the oscillation circuit. 22 µPD17202AGF-011 Recommended Oscillator Ceramic resonator External Manufacturer Part Number Capacitance (pF) C1 Murata Mfg. Co., Ltd. CSA3.58MG CSA4.00MG CSA4.19MG CST3.58MGW CST4.00MGW CST4.19MGW Kyocera Corp. KBR3.58MS KBR4.0MS KRB4.19MS Toko Ceramic Co. Ltd. Daishinku Corp. CRHF4.00 PRS0400BCSAN 33 33 33 18 39 33 33 33 18 33 30 30 30 Unnecessary C2 30 30 30 Unnecessary Oscillation Voltage Range (V) MIN. 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 MAX. 6.0 6.0 6.0 6.0 6.0 6.0 6.0 6.0 6.0 6.0 6.0 Capacitorcontained type Remark Crystal resonator External Capacitance (pF) C1 Kinseki Corp. 4.0 HC-49U-S 22 C2 22 Oscillation Voltage Range (V) MIN. 2.0 MAX. 6.0 Manufacturer Frequency (MHz) Retainer Remark External Circuit Example XIN XOUT C1 C2 23 µPD17202AGF-011 DC Characteristics (VDD = 3 V, TA = –20 to +75 ˚C, fX = 4 MHz) Parameter Low-voltage detection voltage High-level input voltage Symbol VDET VIH1 VIH2 Low-level input voltage VIL1 VIL2 High-level input current IIH1 IIH2 IIH3 Low-level input current IIL1 IIL2 R = 2.2 MΩ RESET, INT pins Other than RESET, INT pins RESET, INT pins Other than RESET, INT pins INT pin RESET pin P0A through P0D pins INT pin RESET pin VIH = VDD VIH = VDD VIH = VDD VIL = 0 V VIL = 0 V w/o pull-up resistor VIL = 0 V w/pull-up resistor P0A, P0B pins VIL = 0 V w/o pull-up resistor VIL = 0 V w/pull-up resistor P0C, P0D pins P0A, P0B pins REM pin LED pin P0A, P0B pins P0C, P0D pins REM pin LED, WDOUT pins Operating mode HALT mode VDD = 3 V, TA = 25 ˚C, R1 = R2 = 1 MΩ External variable resistor (0 to 2.2 MΩ) C1 to C4 = 0.47 µF C1 to C4 = 0.47 µF VDS = 0.2 V VDS = 0.2 V 0.5 0.8 1.9 VLCD0 2 VLCD0 2.85 VLCD0 3 VLCD0 30 5 VIL = 0 V VOH = VDD – 0.3 V VOH = VDD – 2.0 V VOH = VDD – 0.3 V VOL = 0.3 V VOL = 0.3 V VOL = 0.3 V VOL = 0.3 V –0.6 –7.0 –0.3 0.5 0.5 0.5 0.5 –2.0 –15.0 –1.0 1.5 1.5 1.5 1.5 0.6 0.5 0.6 –8 –15 –30 –60 Condition MIN. 1.3 0.8 VDD 0.7 VDD 0 0 TYP. 2.0 MAX. 2.9 VDD VDD 0.2 VDD 0.3 VDD 0.2 0.2 0.2 –0.2 –0.2 Unit V V V V V µA µA µA µA µA µA µA µA µA mA mA mA mA mA mA mA mA mA V V V V IIL3 –120 IIL4 –0.2 IIL5 –30 IIL6 High-level output current IOH1 IOH2 IOH3 Low-level output current IOL1 IOL2 IOL3 IOL4 Supply current IDD1 IDD2 VLCDC voltage LCD output voltage variable range Doubler output voltage Tripler output voltage Common output current Segment output current VLCDC VLCD0 VLCD1 VLCD2 ICOM ILCD –0.2 –4.0 –25.0 –2.0 2.5 2.5 2.5 2.5 1.5 1.5 0.7 1.8 µA µA AC Characteristics (TA = –20 to +75 ˚C, VDD = 3 V) Parameter INT high-, low-level widths Symbol tIOH tIOL RESET low-level width tRSL Condition MIN. 50 50 50 TYP. MAX. Unit µs µs µs 24 µPD17202AGF-011 8. PACKAGE DRAWINGS 64 PIN PLASTIC QFP (14 20) A B 51 52 33 32 detail of lead end CD S R Q 64 1 20 19 F J G P H I M K M N L NOTE Each lead centerline is located within 0.20 mm (0.008 inch) of its true position (T.P.) at maximum material condition. ITEM A B C D F G H I J K L M N P Q R S MILLIMETERS 23.2±0.2 20.0±0.2 14.0±0.2 17.2±0.2 1.0 1.0 0.40±0.10 0.20 1.0 (T.P.) 1.6±0.2 0.8±0.2 0.15 +0.10 –0.05 0.10 2.7 0.125±0.075 5 ° ±5 ° 3.0 MAX. INCHES 0.913 +0.009 –0.008 0.787 +0.009 –0.008 0.551 +0.009 –0.008 0.677±0.008 0.039 0.039 0.016 +0.004 –0.005 0.008 0.039 (T.P.) 0.063±0.008 0.031 +0.009 –0.008 0.006 +0.004 –0.003 0.004 0.106 0.005±0.003 5 ° ±5 ° 0.119 MAX. S64GF-100-3B8, 3BE-3 25 µPD17202AGF-011 NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS device behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD o r GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. 26 µPD17202AGF-011 Regional Information Some information contained in this document may vary from country to country. Before using any NEC product in your application, please contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify: • Device availability • Ordering information • Product release schedule • Availability of related technical literature • Development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, AC supply voltages, and so forth) • Network requirements In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. NEC Electronics Inc. (U.S.) Santa Clara, California Tel: 800-366-9782 Fax: 800-729-9288 NEC Electronics (Germany) GmbH Benelux Office Eindhoven, The Netherlands Tel: 040-2445845 Fax: 040-2444580 NEC Electronics Hong Kong Ltd. Hong Kong Tel: 2886-9318 Fax: 2886-9022/9044 NEC Electronics (Germany) GmbH Duesseldorf, Germany Tel: 0211-65 03 02 Fax: 0211-65 03 490 NEC Electronics Hong Kong Ltd. NEC Electronics (France) S.A. Velizy-Villacoublay, France Tel: 01-30-67 58 00 Fax: 01-30-67 58 99 Seoul Branch Seoul, Korea Tel: 02-528-0303 Fax: 02-528-4411 NEC Electronics (UK) Ltd. Milton Keynes, UK Tel: 01908-691-133 Fax: 01908-670-290 NEC Electronics (France) S.A. Spain Office Madrid, Spain Tel: 01-504-2787 Fax: 01-504-2860 NEC Electronics Singapore Pte. Ltd. United Square, Singapore 1130 Tel: 253-8311 Fax: 250-3583 NEC Electronics Italiana s.r.1. Milano, Italy Tel: 02-66 75 41 Fax: 02-66 75 42 99 NEC Electronics Taiwan Ltd. NEC Electronics (Germany) GmbH Scandinavia Office Taeby, Sweden Tel: 08-63 80 820 Fax: 08-63 80 388 Taipei, Taiwan Tel: 02-719-2377 Fax: 02-719-5951 NEC do Brasil S.A. Sao Paulo-SP, Brasil Tel: 011-889-1680 Fax: 011-889-1689 J96. 8 27 µPD17202AGF-011 The application circuits and their parameters are for reference only and are not intended for use in actual design-ins. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. NEC devices are classified into the following three quality grades: "Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance. Anti-radioactive design is not implemented in this product. M4 96.5