UPD78P328

DATA SHEET MOS Integrated Circuit µPD78P328 16/8-BIT SINGLE-CHIP MICROCONTROLLER The µ PD78P328 is a product provided by replacing the µ PD75328's internal mask ROM with one-time PROM or EPROM. The one-time PROM version is programmable only once and is useful for small-lot production of many different products and early development and time-to-market of application sets. The EPROM version is reprogrammable, and suited for the evaluation of systems. Functions are described in detail in the following user's manual. Be sure to read it before designing. µPD78328 User's Manual: IEU-1268 FEATURES • • µPD78328 compatible • For mass-production, the µPD78P328 can be replaced with the µPD78328 incorporating mask ROM Internal PROM: 16,384 x 8 bits • Programmable once only (one-time PROM version without window) • Erasable with ultraviolet rays and electrically programmable (EPROM version with window) • • PROM programming characteristics: µPD27C256A compatible The µPD78P328 is a QTOPTM microcontroller. Remark QTOP microcontroller is a general term for microcontrollers which incorporates one-time PROM, and are totally supported by NEC's programming service (from programming to marking, screening, and verification). ORDERING INFORMATION Part Number Package 64-pin plastic shrink DIP (750 mils) 64-pin plastic QFP (14 x 20 mm) 64-pin ceramic shrink DIP (750 mils) (with window) Internal ROM One-time PROM One-time PROM EPROM µPD78P328CW µPD78P328GF-3BE µPD78P328DW Functions common to the one-time PROM and EPROM versions are referred to as PROM functions throughout this document. The information in this document is subject to change without notice. Document No. U10209EJ4V0DS00 (4th edition) (Previous No. IC-2486) Date Published October 1995 P Printed in Japan The mark * shows revised points. © NEC Corporation 1990 µPD78P328 PIN CONFIGURATIONS (1) Normal operating mode • 64-pin plastic shrink DIP (750 mils) µPD78P328CW • 64-pin ceramic shrink DIP (750 mils) (with window) µPD78P328DW P20/NM1 P21/INTP0 P22/INTP1 P30/TxD P31/RxD P32/SO/SB0 P33/SI/SB1 P34/SCK P80/TO0 P81/TO1 P82/TO2 P83/TO3 P84/TO4 P85/TO5 P86/TO6/INTP2 P87/TO7/PWM VSS X1 X2 RESET P00/RTP0 P01/RTP1 P02/RTP2 P03/RTP3 P04/RTP4 P05/RTP5 P06/RTP6 P07/RTP7 EA P93/TMD P92/TAS VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 VDD AVDD AVREF P77/ANI7 P76/ANI6 P75/ANI5 P74/ANI4 P73/ANI3 P72/ANI2 P71/ANI1 P70/ANI0 AVSS VDD P57/A15 P56/A14 P55/A13 P54/A12 P53/A11 P52/A10 P51/A9 P50/A8 P47/AD7 P46/AD6 P45/AD5 P44/AD4 P43/AD3 P42/AD2 P41/AD1 P40/AD0 ASTB P90/RD P91/WR Remark These pins are compatible with the µPD78328CW pins. 2 µPD78P328 • 64-pin plastic QFP (14 x 20 mm) µPD78P328GF-3BE P32/SO/SB0 P22/INTP/TI P21/INTP0 P20/NMI VDD AVDD P33/SI/SB1 P34/SCK P80/TO0 P81/TO1 P82/TO2 P83TO3 P84/TO4 P85/TO5 P86/TO6/INTP2 P87/TO7/PWM VSS X1 X2 RESET P00/RTP0 P01/RTP1 P02/RTP2 P03/RTP3 P04/RTP4 39 38 37 36 16 35 17 34 18 19 33 20 21 22 23 24 25 26 27 28 29 30 31 32 64 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 6362 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 AVREF P77/ANI7 P76/ANI6 P75/ANI5 P74/ANI4 P31/RxD P30/RxD P73/ANI3 P72/ANI2 P71/ANI1 P70/ANI0 AVSS VDD P57/A15 P56/A14 P55/A13 P54/A12 P53/A11 P52/A10 P51/A9 P50/A8 P47/AD7 P46/AD6 P45/AD5 P44/AD4 P43/AD3 P07/RTP7 EA P93/TMD P92/TAS VSS P91/WR P05/RTP5 P06/RTP6 P90/RD ASTB Remark These pins are compatible with the µPD78328GF pins. P40/AD0 P41/AD1 P42/AD2 3 µPD78P328 P00-P07 P20-P22 P30-P34 P40-P47 P50-P57 P70-P77 P80-P87 P90-P93 A8-A15 AD0-AD7 ANI0-ANI7 TO0-TO7 NMI PWM INTP0-INTP2 RTP0-RTP7 TxD RxD : Port 0 : Port 2 : Port 3 : Port 4 : Port 5 : Port 7 : Port 8 : Port 9 : Address8-15 : Address0-7/Data0-7 : Analog Input0-7 : Timer Output0-7 : Nonmaskable Interrupt : Pulse Wide Modulation Output : Interrupt From Peripherals0-2 : Real-Time Port0-7 : Transmit Data : Receive Data SI SO SB0-SB1 RD WR ASTB EA RESET SCK TAS TMD X1, X2 AVDD AVREF AVSS VDD VSS : Serial Input : Serial Output : Serial Bus0-1 : Read Strobe : Write Strobe : Address Strobe : External Access : Reset : Serial Clock : Turbo Access Strobe : Turbo Mode : Crystal1, 2 : Analog VDD : Analog Reference Voltage : Analog VSS : Power Supply : Ground 4 µPD78P328 (2) PROM programming mode (RESET = H, AVDD = L) • 64-pin plastic shrink DIP (750 mils) µPD78P328CW • 64-pin ceramic shrink DIP (750 mils) (with window) µPD78P328DW A9 (G) (L) OE CE (L) A8 A10 A11 A12 A13 A14 (L) VSS (G) (Open) RESET A0 A1 A2 A3 A4 A5 A6 A7 VPP (L) VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 VDD AVDD (G) VDD (L) D7 D6 D5 D4 D3 D2 D1 D0 (Open) (L) Caution The recommended connection of the unused pins in the PROM programming mode are indicated in parentheses. L G : : Connect each pin to VSS via a resistor. Connect the pin to VSS. Leave the pin unconnected. Open : 5 µPD78P328 • 64-pin plastic QFP (14 x 20 mm) µPD78P328GF-3BE VDD AVDD OE (G) CE (L) A8 A10 A11 A12 A13 A14 (L) VSS (G) (Open) RESET A0 A1 A2 A3 A4 64 63 62 61 60 59 58 57 56 55 54 53 52 1 51 2 50 49 3 4 48 47 5 46 6 7 45 8 44 9 43 10 42 11 41 40 12 13 39 14 38 15 37 36 16 35 17 34 18 19 33 20 21 22 23 24 25 26 27 28 29 30 31 32 A9 (G) (L) (G) VDD (L) D7 D6 D5 D4 D3 A7 VPP (Open) A5 A6 VSS (L) Caution The recommended connection of the unused pins in the PROM programming mode are indicated in parentheses. L G : : Connect each pin to VSS via a resistor. Connect the pin to VSS. Leave the pin unconnected. : Address0-14 : Data0-7 : Chip Enable : Output Enable : Reset AVDD VDD VSS VPP : Analog VDD : Power Supply : Ground : Programming Power Supply Open : A0-A14 D0-D7 CE OE RESET 6 (L) D0 D1 D2 µPD78P328 BLOCK DIAGRAM EXU Main RAM (P20) NMI INTP0-INTP2 (P21, P22, P86) Programmable Interrupt Controller General Registers 128 x 8 & Data Memory 128 x 8 PROM/RAM BCU X1 X2 RESET ALU PROM 16K x 8 & Peripheral RAM 256 X 8 (P80) TO0 (P81) TO1 (P82) TO2 (P83) TO3 (P84) TO4 (P85) TO5 (P86) TO6 (P87) TO7/PWM (P22) TI/INTP1 System Control & Bus Control & Prefetch Control ASTB RD (P90) WR (P91) TAS (P92) TMD (P93) A8-A15 (P50-P57) AD0-AD7 (P40-P47) A0-A14 D0-D7 CE OE Note Timer/Counter Unit (Real-Time Pulse Unit) Micro Sequence Control Micro ROM EA/VPP Note (P34) SCK (P32) SO/SB0 (P33) SI/SB1 (P30) TxD (P31) RxD Serial Interface (SBI) (UART) A/D Converter (10-bit) AVREF AVSS AVDD INTP0 ANI0-ANI7 (P70-P77) WDT Ports P00-P07 (Real-Time Port) P20-P22 P30-P34 P40-P47 P50-P57 P70-P77 P80-P87 2 2 P90-P93 / VDD Note During PROM programming mode VSS / 7 µPD78P328 CONTENTS 1. PIN FUNCTIONS ... 9 1.1 Normal Operating Mode ... 9 1.2 PROM Programming Mode (RESET = H, AVDD = L) ... 11 1.3 Pin Input/Output Circuits and Recommended Connection of Unused Pins ... 12 DIFFERENCES BETWEEN µPD78P328 and µPD78328 ... 14 PROM PROGRAMMING ... 15 3.1 Operation Mode ... 15 3.2 PROM Write Procedure ... 16 3.3 PROM Read Procedure ... 18 ERASURE CHARACTERISTICS (EPROM VERSION ONLY) ... 19 WINDOW SEAL (EPROM VERSION ONLY) ... 19 ONE-TIME PROM VERSION SCREENING ... 19 ELECTRICAL SPECIFICATIONS ... 20 PACKAGE DRAWINGS ... 35 RECOMMENDED SOLDERING CONDITIONS ... 37 DRAWINGS OF CONVERSION SOCKET AND RECOMMENDED FOOTPRINT... 38 2. 3. 4. 5. 6. 7. 8. 9. APPENDIX A. * APPENDIX B. TOOLS ... 40 B.1 Development Tools ... 40 B.2 Evaluation Tools ... 43 B.3 Embedded Software ... 43 8 µPD78P328 1. PIN FUNCTIONS 1.1 Normal Operating Mode (1) Port Pins Pin Name Input/Output Function Alternate Function P00-P07 Input/Output PORT0 4-/8-bit input/output port Input or output mode can be specified bit-wise. The port can also operate as a real-time output port. P20 P21 P22 P30 P31 P32 P33 P34 P40-P47 Input/Output PORT 4 8-bit input/output port Input or output mode can be specified in 8-bit units. P50-P57 Input/Output PORT 5 8-bit input/output port Input or output mode can be specified bit-wise. P70-P77 Input PORT 7 8-bit input-only port P80 P81 P82 P83 P84 P85 P86 P87 P90 P91 P92 P93 Input/Output PORT 9 4-bit input/output port Input or output mode can be specified bit-wise. Input/Output PORT 8 8-bit input/output port Input or output mode can be specified bit-wise. TO0 TO1 TO2 TO3 TO4 TO5 TO6/INTP2 TO7/PWM RD WR TAS TMD ANI0-ANI7 A8-A15 Input/Output PORT 3 5-bit input/output port Input or output mode can be specified bit-wise. Input PORT 2 3-bit input-only port NMI INTP0 INTP1/TI TxD RxD SO/SB0 SI/SB1 SCK AD0-AD7 RTP0-RTP7 9 µPD78P328 (2) Non-Port Pins (1/2) Pin Name Input/Output Function Alternate Function RTP0-RTP7 Output Real-time output port which outputs a pulse in synchronization with the trigger signal from P00-P07 real-time pulse unit (RPU). NMI Input Edge-detected nonmaskable interrupt request input. The rising or falling edge can be selected for the valid edge by setting the mode register. P20 INTP0 INTP1 INTP2 TI RxD TxD SO SI SB0 SB1 SCK AD0-AD7 A8-A15 TO0 TO1 TO2 TO3 TO4 TO5 TO6 TO7 PWM RD WR Input Edge-detected external interrupt request input. The valid edge can be specified in the mode register. P21 P22/T1 P86/TO6 Input Input Output Output Input Input/Output External count clock input pin to timer 1 (TM1). Serial data input pin to asynchronous serial interface (UART). Serial data output pin from asynchronous serial interface (UART). Serial data output pin from clocked serial interface in 3-wire mode. Serial data input pin to clocked serial interface in 3-wire mode. Serial data input/output pins to/from clocked serial interface in SBI mode. S22/INTP1 P30 P31 P32/SB0 P33/SB1 P32/SO P33/SI Input/Output Input/Output Output Output Serial clock input/output pin to/from clocked serial interface. Multiplexed address/data bus used when external memory is added. Address bus used when external memory is added. Pulse output from real-time pulse unit. P34 P40-P47 P50-P57 P80 P81 P82 P83 P84 P85 P86/INTP2 P87/PWM Output Output PWM signal output from real-time pulse unit. Strobe signal output for external memory read operation. Strobe signal output for external memory write operation. Control signal output pins to access turbo access manager (µPD71P301). Note P87/TO7 P90 P91 P92 P93 * TAS TMD ASTB Output Timing signal output pin to externally latch an address information output to port 4 for external memory access. For µPD78P328, normally connect the EA pin to VDD. When the EA pin is connected to VSS, the µPD78P328 enters the ROMless mode and external memory is accessed. The EA pin level cannot be changed during operation. — EA Input — Note Turbo access manager (µPD71P301) is available for maintenance purposes only. 10 µPD78P328 (2) Non-Port Pins (2/2) Function Alternate Function ANI0-ANI7 Pin Name Input/Output Input Input — — Input Input — — — Analog input to A/D converter. A/D converter reference voltage input. A/D converter analog power supply. A/D converter GND. System reset input. Crystal connection pin for system clock generation. To supply external clock, input to the X1 and input reverse signal to the X2 pin (X2 pin can be unconnected.) Positive power supply pin. GND pin. P70-P77 — — — — — — — — AVREF AVDD AVSS RESET X1 X2 VDD VSS 1.2 PROM Programming Mode (RESET = H, AVDD = L) Pin Name Input/Output AVDD RESET A0-A14 D0-D7 CE OE VPP VDD VSS — — Input Input — Address bus. Data bus. PROM enable to PROM. Read strobe to PROM. Write power supply. Positive power supply. GND. Input Function PROM programming mode setting. 11 µPD78P328 1.3 Pin Input/Output Circuits and Recommended Connection of Unused Pins Table 1-1 and Figure 1-1 show the pin input/output circuit schematically. Table 1-1. Pin Input/Output Circuits and Recommended Connection of Unused Pins Pin Input/Output circuit type P00P07/RTP0-RTP7 5 Input state: Independently connect to VDD or VSS via a resistor. Output state: Leave Open. P21/NMI P21/INTP0 P27/INTP6/TI P30/TxD P31/RxD P32/SO/SB0 P33/SI/SB1 P34/SCK P40/AD0-P47/AD0-AD7 P50/P57/A8-A15 P70-P77/ANI0-ANI7 P80-P85/TO0-TO5 P86/TO6/INTP2 P87/TO7/PWM P90/RD P91/WR P92/TAS P93/TMD ASTB EA RESET AVREF, AVSS VDD 4 1 2 — — Leave Open. — — Connect to VSS. Connect to VDD. 9 5 6 5 5 Connect to VSS. Input state: Independently connect to VDD or VSS via a resistor. Output state: Leave Open. 5 8 5 Input state: Independently connect to VDD or VSS via a resistor. Output state: Leave Open. 2 Connect to VSS. Recommended connection of unused pins 12 µPD78P328 Figure 1-1. Pin Input/Output Circuits TYPE 1 TYPE 6 VDD data IN P-ch output disable data data input enable control signal control input enable TYPE 2 TYPE 8 VDD P-ch IN/OUT N-ch N-ch VDD data IN output disable P-ch N-ch IN/OUT Schmitt-triggerred input with hysteresis characteristics TYPE 4 TYPE 9 VDD IN data P-ch OUT P-ch N-ch Comparator + – VREF output disable N-ch (Threshold voltage) input enable Push-pull output that can be placed in high impedance (both P-ch and N-ch off). TYPE 5 VDD data output disable P-ch N-ch IN/OUT input disable 13 µPD78P328 2. DIFFERENCES BETWEEN µPD78P328 and µPD78328 The µPD78P328 is a product provided by replacing the µPD78328's on-chip mask ROM with one-time PROM or EPROM. Thus, the µPD78P328 and µPD78328 are the same in function except for the ROM specifications such as write or verify. Table 2-1 lists the differences between these two products. This Data Sheet describes the PROM specification function. Refer to the µPD78328 documents for details of other functions. Table 2-1. Differences between µPD78P328 and µPD78328 Item Internal program memory (electrical program) PROM programming pin Package µPD78P328 One-time PROM (programmable only once) Contained • 64-pin plastic shrink DIP • 64-pin plastic QFP • 64-pin ceramic shrink DIP (with window) EPROM (reprogrammable) µPD78328 Mask ROM (nonprogrammable) Not contained • 64-pin plastic shrink DIP • 64-pin plastic QFP * * * Electrical specifications Others Current dissipations are different. Noise immunity and noise radiation differ because circuit complexity and mask layout are different. Caution The noise immunity and noise radiation differ between the PROM and mask ROM versions. To replace the PROM version with the mask ROM version when shifting from experimental production to mass production, evaluate your system by using the CS version (not ES version) of the mask ROM version. 14 µPD78P328 3. PROM PROGRAMMING The PROM incorporated in the µPD78P328 is a 16,384 x 8-bit electrically writable PROM. For programming, set the PROM programming mode by using the RESET and AVDD pins. The programming characteristics are compatible with the µPD27C256A programming characteristics. Table 3-1. Pin Function in Programming Mode Function Address input Data input Chip enable/program pulse Output enable Program voltage Mode control Normal Operating Mode P00-P07, P80, P20, P81-P85 P40-P47 P33 P32 EA RESET, AVDD Programming Mode A0-A14 D0-D7 CE OE VPP 3.1 Operation Mode To set the program write/verify mode, set RESET = H and AVDD = L. For the mode, the operation mode can be selected by setting the CE and OE pins, as listed in Table 3-2. To read the PROM contents, set the read mode. Connect the unused pins exactly as indicated on Pin Configuration. Table 3-2. PROM Programming Operation Mode Mode Program write Program verify Program inhibit Read Output disable Standby RESET H AVDD L CE L H H L L H OE H L H L H L/H +5 V +5 V VPP +12.5 V VDD +6 V D0-D7 Data input Data output High impedance Data output High impedance High impedance Caution When VPP is set to +12.5 V and VDD is set to +6V, setting both CE and OE to L is inhibited. 15 µPD78P328 3.2 PROM Write Procedure The write procedure into PROM is as follows: (See also Figure 3-2). (1) Fix RESET = H and AVDD = L. Connect other unused pins exactly as indicated in section "Pin Configuration." (2) Supply +6 V to the VDD and +12.5 V to the VPP pin. (3) Supply an initial address. (4) Supply write data. (5) Supply 1 ms program pulse (active low) to the CE pin. (6) Execute the verify mode. Check whether or not the write data is written normally. • When it is written normally: Proceed to step (8). • When it is not written normally: Repeat steps (4) to (6). If the data is not written normally after 25 repetitions of the steps, proceed to step (7). (7) Assume the device to be defective. Stop write operation. (8) Supply write data and X (number of steps (4) to (6) repetitions) x 3 ms program pulses (additional write). (9) Increment the address. (10) Repeat steps (4) to (9) to the last address. Figure 3-1 shows the PROM Write/Verify Timing Steps (2) to (8) above. Figure 3-1. PROM Write/Verify Timing X-time repetition Write Verify Additional data write A0-A14 Address input Hi-Z D0-D7 Data input Data output Hi-Z Data input Hi-Z +12.5 V VPP VDD +6 V VDD VDD 3 X ms CE (input) OE (input) 16 µPD78P328 Figure 3-2. Write Procedure Flowchart (1) WRITE START (2) Supply power (3) Supply initial address (4) Supply write data (5) Write NG (after 24 repetition or less) Supply program pulse (6) Verify mode Write OK Write NG (at the 25th repetition) (8) Make additional write (3X ms pulses) X: Number of write repetitions (9) Increment address (10) < end address End address (7) Defective device > end address WRITE END 17 µPD78P328 3.3 PROM Read Procedure The read procedure of the PROM contents into the external data bus (D0-D7) is as follows. (1) Fix RESET = H and AVDD = L. Connect other unused pins exactly as indicated on Pin Configuration. (2) Supply +5 V to the VDD and VPP pins. (3) Input the address of the data to be read to the A0-A14 pins. (4) Execute the read mode. (5) The data is output to the D0-D7 pins. Figure 3-3 shows the PROM read timing steps (2) to (5) above. Figure 3-3. PROM Read Timing A0-A14 Address input CE (input) OE (input) D0-D7 Hi-Z Data output Hi-Z 18 µPD78P328 4. ERASURE CHARACTERISTICS (EPROM VERSION ONLY) The data written into the µPD78P328DW program memory can be erased (FFH) and new data can be rewritten into the memory. To erase data, apply light with a wave length shorter than 400 nm to the window. Normally, apply ultraviolet rays having the 254-nm wave length. The radiation amount required to completely erase data is as follows: • Ultraviolet strength x erasure time: 15 W•s/cm2 or more • Erasure time: 15 to 20 minutes when a 12,000 µW/cm2 ultraviolet lamp is used. However, the time may be prolonged due to ultraviolet lamp performance deterioration, dirty window, etc. For erasure, place an ultraviolet lamp at a position within 2.5 cm from the window. If a filter is attached to the ultraviolet lamp, remove the filter before applying ultraviolet rays. 5. WINDOW SEAL (EPROM VERSION ONLY) If the µPD78P328DW window is exposed to sunlight or fluorescent lamp light for hours, EPROM data may be erased and the internal circuit may operate erroneously. To prevent such accidents from occurring, put a protective seal on the window. A protective seal whose quality is guaranteed by NEC is attached to every EPROM version with window at shipment. 6. ONE-TIME PROM VERSION SCREENING The one-time PROM versions (µPD78P328CW, 78P328GF-3BE) cannot be completely tested by NEC for shipment because of their structure. For screening, it is recommended to verify PROM after storing the necessary data under the following conditions: NEC provides chargeable services ranging from one-time PROM writing to marking, screening, and verification for QTOP microcontroller products. For details, contact an NEC sales representative. Storage temperature 125˚C Storage time 24 hours 19 µPD78P328 7. ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings (TA = 25 °C) Parameter Power supply voltage Symbol VDD VDD VPP AVSS Input voltage VI1 VI2 Output voltage Output current, low VO IOL All output pins Total for all pins Output current, high IOH All output pins Total for all pins Analog input voltage VIAN Note 2 AVDD > VDD VDD ≥ AVDD A/D converter reference input voltage Operating ambient temperature Storage temperature TA Tstg AVREF AVDD > VDD VDD ≥ AVDD Note 1 P20/NIM (A9) PIN Test Conditions Ratings –0.5 to +7.0 –0.5 to VDD +0.5 –0.5 to +13.5 –0.5 to +0.5 –0.5 to VDD +0.5 –0.5 to +13.5 –0.5 to VDD +0.5 4.0 90 –1.0 –20 -0.5 to VDD +0.5 -0.5 to AVDD +0.5 -0.5 to VDD +0.3 -0.5 to AVDD +0.3 –10 to +70 –65 to +150 Unit V V V V V V V mA mA mA mA V V V V °C °C Notes 1. Pins except for P20/NMI (A9), P70/ANI0-P77/ANI7 2. P70/ANI0-P77/ANI7 * Caution Product quality may suffer if the absolute maximum rating is exceeded for even a single parameter, even momentarily. In other words, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions which ensure that the absolute maximum ratings are not exceeded. Recommended Operation Conditions Oscillation frequency 8 MHz ≤ fXX ≤ 16 MHz TA –10 to +70 ˚C VDD +5.0 V ±5% Capacitance (TA = 25 °C, VSS = VDD = 0 V) Parameter Input capacitance Output capacitance I/O capacitance Symbol CI CO CIO Test Conditions f = 1 MHz Unmeasured pins returned to 0 V MIN. TYP. MAX. 10 20 20 Unit pF pF pF 20 µPD78P328 Oscillator Characteristics (TA = –10 to +70 °C, VDD = +5 V±5%, VSS = 0 V) Resonator Ceramic or crystal resonator Recommended Circuit Parameter Oscillation frequency (fXX) MIN. 8 MAX. 16 Unit MHz X2 X1 VSS C2 C1 External clock X1 X2 X1 input frequency (fX) 8 16 MHz HCMOS Inverter or X1 X2 Open HCMOS Inverter X1 input rise, fall time (fXR, tXF) 0 20 ns X1 input high, low level width (tWXH, tWXL) 25 80 ns Caution When using the system clock oscillator, wire the portion enclosed in dotted line in the figure as follows to avoid adverse influences on the wiring capacitance: • Keep the wiring length as short as possible. • Do not cross the wiring over the other signal lines. Do not route the wiring in the vicinity of lines through which a high fluctuating current flows. • Always keep the ground point of the capacitor of the oscillator circuit at the same potential as VSS. Do not connect the power source pattern through which a high current flows. • Do not extract signals from the oscillation circuit. Recommended Oscillator Constants Ceramic resonator Manufacturer Name Part Number Frequency [MHz] Recommended Constants C1 [pF] MURATA CSA8.00MT CSA12.0MT CSA16.00MX040 CST8.00MTW CST12.00MTW CST16.00MXW0C3 8.0 12.0 16.0 8.0 12.0 16.0 15 Internal 15 Internal 30 C2 [pF] 30 21 µPD78P328 DC Characteristics (TA = –10 to +70 °C, VDD = +5 V ±5%, VSS = 0 V) Parameter Input voltage, low Input voltage, high Symbol VIL VIH1 VIH2 Output voltage, low Output voltage, high Input leakage current Output leakage current VDD power supply current VOL VOH ILI ILO IDD1 IDD2 Data retention voltage Data retention current VDDDR IDDDR Note 1 Note 2 IOL = 2.0 mA IOH = –400 µA 0 V ≤ V I ≤ VDD 0 V ≤ V O ≤ VDD Operation mode HALT mode STOP mode STOP mode VDDDR = 2.5 V VDDDR = 5.0 V ±5% 2.5 3 10 15 50 45 25 VDD–1.0 ±10 ±10 75 45 Test Conditions MIN. 0 2.2 0.8VDD 0.45 V V TYP. MAX. 0.8 Unit V V µA µA mA mA V µA µA Notes 1. Pins except for RESET, X1, X2, P20/NMI, P21/INTP0, P22/INTP1/TI, P86/INTP2/TO0, P32/SO/SB0, P33/SI/SB1, or P34/SCK. 2. RESET, X1, X2, P20/NMI, P21/INTP0, P22/INTP1/TI, P86/INTP2/TO0, P32/SO/SB0, P33/SI/SB1, or P34/SCK pins. 22 µPD78P328 AC Characteristics (TA = –10 to +70 °C, VDD = +5 V ±5%, VSS = 0 V) Discontinuous read/write operation (when general-purpose memory is connected) Parameter System clock cycle time Address setup time (to ASTB ↓) Address hold time (from ASTB ↓) Address → RD ↓ delay time RD ↓ → address float time Address → data input time RD ↓ → data input time ASTB ↓ → RD ↓ delay time Data hold time (from RD ↑) RD ↑ → address active time RD low-level width ASTB high-level width Address → WR ↓ delay time ASTB ↓ → data output time WR ↓ → data output time ASTB ↓ → WR ↓ delay time Data setup time (to WR ↑) Data hold time (from WR ↑) WR ↑ → ASTB ↓ delay time WR low-level width Symbol tCYK tSAST tHSTA tDAR tFRA tDAID tDRID tDSTR tHRID tDRA tWRL tWSTH tDAW tDSTOD tDWOD tDSTW tSODW tHWOD tDWST tWWL 42 137 32 42 147 42 0 37 147 37 85 102 40 Test Conditions MIN. 125 22 32 85 8 222 112 MAX. 250 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 23 µPD78P328 tCYK-Dependent Bus Timings Parameter tSAST tHSTA tDAR tDAID tDRID tDSTR tDRA tWRL tWSTH tDAW tDSTOD tDSTW tSODW tHWOD tDWST tWWL Calculation expression 0.5T – 40 0.5T – 30 T – 40 (2.5 + n) T – 90 (1.5 + n) T – 75 0.5T – 20 0.5T – 25 (1.5 + n) T – 40 0.5T – 25 T – 40 0.5T + 40 0.5T – 20 1.5T – 50 0.5T – 30 0.5T – 20 (1.5 + n) T – 40 MIN./MAX. MIN. MIN. MIN. MAX. MAX. MIN. MIN. MIN. MIN. MIN. MAX. MIN. MIN. MIN. MIN. MIN. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Remarks 1. T = tCYK = 1/fCLK (fCLK is the internal system clock frequency and is provided by dividing fXX or fX by two). 2. n is the number of wait cycles defined by user software. 3. Only parameters listed in the table are dependent on tCYK. 24 µPD78P328 Serial Operation (TA = –10 to +70 °C, VDD = +5 V ±5%, VSS = 0 V) Parameter Serial clock cycle time Symbol tCYSK Test Conditions Input Output External clock Internal divide by 8 Internal divide by 32 Serial clock high-level width tWSKL Input Output External clock Internal divide by 8 Internal divide by 32 Serial clock high-level width tWSKH Input Output External clock Internal divide by 8 Internal divide by 32 SI setup time (to SCK ↑) SI hold time (from SCK ↑) SO/SB0, SI/SB1 output delay time (from SCK ↓) tDSBSK2 tSRXSK tHSKRX tDSBSK1 CMOS push-pull output (3-wire serial I/O mode) Open drain output (SBI mode), RL = 1 kΩ SB0, SB1 high hold time (from SCK ↑) tHSBSK SB0, SB1 low setup time (from SCK ↓) tSSBSK SB0, SB1 low-level width SB0, SB1 high-level width tWSBL tWBSH SBI mode 4T 4T 4T–20 4T–20 tCYK tCYK ns ns 0 600 ns MIN. 1 8T 32T 420 4T–80 16T–100 420 4T–80 16T–100 80 80 0 210 MAX. Unit µs tCYK tCYK ns ns ns ns ns ns ns ns ns Remark T = tCYK = 1/fCLK (fCLK is the internal system clock frequency and is provided by dividing fXX or fX by two.) 25 µPD78P328 Other operations (TA = –10 to +70˚C, VDD = +5 V±5%, VSS = 0 V) Parameter NMI high-, low-level widths Symbol tWNIH, tWNIL INTP0 high-, low-level widths tWIOH, tWIOL INTP1 high-, low-level widths tWI1H, tWI1L INTP2 high-, low-level widths tWI2H, tWI2L RESET high-, low-level widths tWRSH, tWRSL TI high-, low-level widths tWTIH, tWTIL TM1 In the event counter mode 8T tCYK 5 8T tCYK 8T tCYK 8T tCYK Test Conditions MIN. 5 MAX. Unit µs µs Remark T = tCYK = 1/fCLK (fCLK is the internal system clock frequency and is provided by dividing fXX or fX by two.) External clock timing (TA = –10 to +70˚C, VDD = +5 V±5%, VSS = 0 V) Parameter X1 input high-, low-level widths Symbol tWXH , tWXL X1 input rise, fall times tXR, tXF TI input cycle time tCYK 62 125 ns 0 20 ns Test Conditions MIN. 25 MAX. 80 Unit ns 26 µPD78P328 A/D Converter (TA = –10 to +70˚C, VDD = +5 V±5%, VSS = AVSS = 0 V, VDD –0.5 V ≤ AVDD ≤ VDD) Parameter Resolution Total error Note1 Symbol Test Conditions MIN. 10 TYP. MAX. Unit bit 4.5 V ≤ AVREF ≤ AVDD 3.4 V ≤ AVREF ≤ AVDD ±0.4 ±0.7 ±1/2 %FSR %FSR LSB tCYK tCYK Quantification error Conversion time Sampling time Zero scale error Note1 tCONV tSAMP 4.5 V ≤ AVREF ≤ AVDD 3.4 V ≤ AVREF ≤ AVDD 144 24 +1.5 +1.5 +1.5 +1.5 +1.5 +1.5 –0.3 3.4 1.0 2.0 STOP mode AVDDDR = 2.5 V AVDDDR = 5 V± 5% 2.0 10 ±2.5 ±4.5 ±2.5 ±4.5 ±2.5 ±4.5 AVDD AVDD 3.0 6.0 10 50 LSB LSB LSB LSB LSB LSB V V mA mA Fullscale error Note1 4.5 V ≤ AVREF ≤ AVDD 3.4 V ≤ AVREF ≤ AVDD Nonlinear error Note1 4.5 V ≤ AVREF ≤ AVDD 3.4 V ≤ AVREF ≤ AVDD Analog input voltage Basic voltage AVREF current AVDD supply current A/D converter data retention current Note2 V IAN AVREF AI REF AIDD AI DDDR * µA µA Notes 1. Quantization error is excluded. 2. When –0.3 V ≤ VIAN ≤ 0 V, conversion result is 000H. When 0 V < VIAN < AVREF, conversion is executed by 10-bit resolution. When AVREF ≤ V IAN ≤ AVDD, conversion result is 3 FFH. Standby flag retention characteristics (TA = –10˚C to 70˚C) Parameter Standby flag retention power supply voltage V DD rising, falling time Symbol VDDDR tRVD, tFVD Test Conditions MIN. 2.5 200 MAX. 5.5 Unit V ns AC Timing Test Points VDD – 1 V 0.8 VDD or 2.2 V 0.8 V 0.45 V Test Points 0.8 VDD or 2.2 V 0.8 V 27 µPD78P328 Timing Wave Forms Discontinuous Read Operation tCYK (CLK) P50-P57 (output) tSAST P40-P47 (input/output) tDAID High-order address High-order address Low-order address (output) Hi-Z Data (input) tHRID Hi-Z Low-order address (output) Hi-Z tWSTH P50-P57 (output) tHSTA tFRA RD (output) tDSTR tDAR tDRID tWRA tDRA Discontinuous Write Operation (CLK) P50-P57 (output) tSAST P40-P47 (input/output) Low-order address (output) High-order address High-order address Data (output) tHWOD Low-order address (output) tWSTH ASTB (output) tHSTA tDSTOD tDSTA WR (output) tDSTW tDWOD tDAW tWWL tSODW 28 µPD78P328 Serial Operation Three-Wire Serial I/O Mode: tWSKL SCK tCYSK SI tWSKH tSRXSK tHSKRX Input data tDSBSKI SO Output data SBI Mode Bus Release Signal Transfer SCK tHSBSK SB0 tWSBL tWSBH tSSBSK Command Signal Transfer tWSKL tWSKH SCK tHSBSK SB0 tSSBSK tCYSK tDSBSK2 tSSSK tHSSK I/O data 29 µPD78P328 Interrupt Input Timing tWNIH 0.8 VDD 0.8 V tWNIL NMI tWIOH tWIOL INTP0 tWI1H tWI1L INTP1 tWI2H tWI2L INTP2 Reset Input Timing tWRSH 0.8 VDD 0.8 V tWRSL RESET 30 µPD78P328 External Clock Timing tWXH X1 tXR tXF tWXL tCYX Standby Flag Retention Timing VDD tFVD VDDDR tRVD TI Pin Input Timing tWTIH tWTIL TI 31 µPD78P328 DC Programming Characteristics (TA = 25 ± 5 °C, VSS = 0 V) Parameter Symbol Symbol Test conditions Note1 MIN. TYP. MAX. Unit Input voltage, high VIH VIH 2.2 VDDP +0.3 V Input voltage, low Input leakage current Output voltage, high Output voltage, low Input current Output leakage current PROG pin high voltage input current VDDP power supply voltage VIL ILIP VOH VOL IA9 ILO IIP VIL ILI VOH VOL — — — 0 ≤ V I ≤ VDDP IOL = 2.0 mA A9 (P20/NMI) pin 0 ≤ VO ≤ VDDP, OE = VIN Note 2 –0.3 IOH = –400 µA 0.8 ±10 V µA V V 2.4 0.45 ±10 10 ±10 µA µA µA V V V V VDDP VDD Program memory write mode Program memory read mode 5.75 4.5 12.2 6.0 5.0 12.5 6.25 5.5 12.8 VPP power supply voltage VPP VPP Program memory write mode Program memory read mode VPP = VDDP 10 10 30 30 VDDP power supply current IDD IDD Program memory write mode Program memory read mode CE = VIL, OE = VIN mA mA VPP power supply current IPP IPP Program memory write mode CE = VIL, OE = VIN Program memory read mode 10 30 mA 1 100 µA Notes 1. Corresponding µPD27C256A symbols. 2. VDDP is VDD pin during the programming mode. 32 µPD78P328 AC Programming Characteristics (TA = 25 ± 5 °C, VSS = 0 V) Parameter Address setup time (to CE ↓) Data → OE ↓ delay time Input data setup time (to CE ↓) Address hold time (from CE ↑) Input data hold time (from CE ↑ ) Output data hold time (from OE ↑ ) Symbol Symbol Test conditions Note MIN. TYP. MAX. Unit tSAC tDDOO tSIDC tHCA tHCID tHOOD tSVPC tSVDC tWL1 tWL2 tDAOD tDOOD tHCOD tHAOD tAS tOES tDS tAH tDH tDF tVPS tVDS tPW tOPW tACC tOE tDF tOH OE = VIL OE = VIL 2 2 2 2 2 0 2 2 0.95 2.85 1.0 1.05 78.75 2 1 0 0 130 130 µs µs µs µs µs ns V PP setup time (to CE ↓) V DDP setup time (to CE ↓) Initial program pulse width Additional program pulse width Address → data output time OE ↓ → data output time Data hold time (from OE ↑) Data hold time (from address) µs µs ms ms µs µs ns ns Note Corresponding µPD27C256A symbols. 33 µPD78P328 PROM Write Mode Timing A12-A0 tSAC D7-D0 Data input tSIDC VPP VPP VDDP VDDP +1 VDDP tSVDC VIH CE VIL VIH OE VIL tWL1 tDDOO Effective address tHOOD Data output tHCID Data onput tSIDC tHCID tHCA tSVPC VDDP tDOOD tWL2 Cautions 1. Apply VDDP before VPP and remove it after VPP. 2. VPP must not exceed +13 V, including the overshoot. PROM Read Mode Timing A12-A0 Effective address OE tDAOD D7-D0 Hi-Z tDOOD tHCOD tHAOD Data output Hi-Z 34 µPD78P328 8. PACKAGE DRAWINGS 64 PIN PLASTIC SHRINK DIP (750 mil) 64 33 1 A 32 K L J I F D G H N M C B M R NOTE 1) Each lead centerline is located within 0.17 mm (0.007 inch) of its true position (T.P.) at maximum material condition. 2) Item "K" to center of leads when formed parallel. ITEM A B C D F G H I J K L M N R MILLIMETERS 58.68 MAX. 1.78 MAX. 1.778 (T.P.) 0.50±0.10 0.9 MIN. 3.2±0.3 0.51 MIN. 4.31 MAX. 5.08 MAX. 19.05 (T.P.) 17.0 0.25 +0.10 –0.05 0.17 0~15° INCHES 2.311 MAX. 0.070 MAX. 0.070 (T.P.) 0.020 +0.004 –0.005 0.035 MIN. 0.126±0.012 0.020 MIN. 0.170 MAX. 0.200 MAX. 0.750 (T.P.) 0.669 0.010 +0.004 –0.003 0.007 0~15° P64C-70-750A,C-1 35 µPD78P328 36 µPD78P328 64 PIN PLASTIC QFP (14 × 20) A B 51 52 33 32 detail of lead end C D S Q R 64 1 20 19 F G H I M J K P N L M NOTE Each lead centerline is located within 0.20 mm (0.008 inch) of its true position (T.P.) at maximum material condition. ITEM A B C D F G H I J K L M N P Q R S MILLIMETERS 23.6±0.4 20.0±0.2 14.0±0.2 17.6±0.4 1.0 1.0 0.40±0.10 0.20 1.0 (T.P.) 1.8±0.2 0.8±0.2 0.15 +0.10 –0.05 INCHES 0.929±0.016 0.795 +0.008 –0.009 0.551+0.009 –0.008 0.693±0.016 0.039 0.039 0.016 +0.004 –0.005 0.008 0.039 (T.P) 0.071 +0.008 –0.009 0.031 +0.009 –0.008 0.006 +0.004 –0.003 0.10 0.004 2.7 0.106 0.1±0.1 0.004±0.004 5°±5° 5°±5° 3.0 MAX. 0.119 MAX. P64GF-100-3B8,3BE,3BR-2 37 µPD78P328 9. RECOMMENDED SOLDERING CONDITIONS It is recommended that this device be soldered under the following conditions. For details on the recommended soldering conditions, refer to information document "Semiconductor Devices Mounting Technology Manual" (IEI-1207). For soldering methods and conditions other than those recommended, please contact your NEC sales representative. * Table 9-1. Soldering Conditions for Surface Mount Devices µPD78P328GF-3BE: 64-pin plastic QFP (14 x 20 mm) Soldering Method Infrared reflow Soldering Conditions Package peak temperature: 235˚C, Time: 30 seconds max. (210˚C min.), Number of times: 2 max, Maximum number of days: 7 daysNote (thereafter, 20 hours of prebaking is required at 125˚C) < Cautions > (1) Wait for the device temperature to return to normal after the first reflow before starting the second reflow. (2) Do not perform flux cleaning with water after the first reflow. Package peak temperature: 215˚C, Time: 40 seconds max. (200˚C min.), Number of times: 2 max, Maximum number of days: 7 daysNote (thereafter, 20 hours of prebaking is required at 125˚C) < Cautions > (1) Wait for the device temperature to return to normal after the first reflow before starting the second reflow. (2) Do not perform flux cleaning with water after the first reflow. Soldering bath temperature: 260˚C max., Time: 10 seconds max., Number of times: 1, Preheating temperature: 120°C max. (package surface temperature), Maximum number of days: 7 daysNote (thereafter, 20 hours of prebaking is required at 125˚C). Pin temperature: 300˚C max., Time: 3 seconds max. (per pin row) Recommended Soldering Code IR35-207-2 VPS VP15-207-2 Wave soldering WS60-207-1 Partial heating — Note Number of days after unpacking the dry pack. Storage conditions are 25°C and 65% RH max. Caution Do not use different soldering methods together (except the partial heating method). Table 9-2. Soldering Conditions for Through-hole Devices µPD78P328CW: 64-pin Plastic Shrink DIP (750 mils) µPD78P328DW: 64-pin Ceramic Shrink DIP (750 mils) (with window) Soldering Method Wave soldering (pin only) Partial heating Soldering Conditions Soldering bath temperature: 260˚C max., Time: 10 seconds max. Pin temperature: 300˚C max., Time: 3 seconds max. (per pin) Caution Apply wave soldering only to the pins and be careful so as not to bring solder into direct contact with the package. 38 µPD78P328 APPENDIX A. DRAWINGS OF CONVERSION SOCKET AND RECOMMENDED FOOTPRINT * The emulation probe (EP-78327GF-R) for the µPD78P328GF-3BE is connected with the target system in combination with the conversion socket (EV-9200G-64). The drawings of the socket and recommended footprint are shown below. Figure A-1. Drawing of Conversion Socket (EV-9200G-64) (for reference only) A B G N F S T D C E U R EV-9200G-64-G0 INCHES 0.984 0.799 0.157 0.569 0.748 4-C 0.11 0.031 0.433 0.866 0.972 0.197 0.638 0.744 0.315 0.307 0.098 0.079 0.053 0.014+0.004 –0.005 O P EV-9200G-64 1 No.1 pin index Q H I J ITEM A B C D E F G H I J K L M O N P Q R S T U MILLIMETERS 25.0 20.30 4.0 14.45 19.0 4-C 2.8 0.8 11.0 22.0 24.7 5.0 16.2 18.9 8.0 7.8 2.5 2.0 1.35 0.35 ± 0.1 φ 2.3 φ 1.5 φ 0.091 φ 0.059 M K L 39 µPD78P328 Figure A-2. Recommended Footprint for EV-9200G-64 (for reference only) G H L E D F J M C B A EV-9200G-64-P0 INCHES 1.012 0.827 0.039+0.002 × –0.001 0.709=0.709+0.002 –0.003 0.598 0.783 0.433+0.004 –0.003 0.217+0.001 –0.002 0.197+0.003 –0.004 0.098+0.002 –0.001 0.024+0.001 –0.002 ITEM A B C D E F G H I J K L M Caution MILLIMETERS 25.7 21.0 1.0±0.02 × 18=18.0±0.05 1.0±0.02 × 12=12.0±0.05 0.039+0.002 × 0.472=0.472+0.003 –0.001 –0.002 15.2 19.9 11.00 ± 0.08 5.50 ± 0.03 5.00 ± 0.08 2.50 ± 0.03 0.6 ± 0.02 φ 2.36 ± 0.03 φ 1.57 ± 0.03 φ 0.093+0.001 –0.002 φ 0.062+0.001 –0.002 Dimensions of mount pad for EV-9200 and that for target device (QFP) may be different in some parts. For the recommended mount pad dimensions for QFP, refer to "SEMICONDUCTOR DEVICE MOUNTING TECHNOLOGY MANUAL" (IEI-1207). 40 K I µPD78P328 * APPENDIX B. TOOLS B.1 Development Tools The following development tools are readily available to support development of systems using the µPD78P328: Language Processor 78K/III Series relocatable assembler (RA78K/III) Relocatable assembler common to the 78K/III series. Since it contains the macro function, the development efficiency can be improved. A structured assembler which enables you to explicity describe program control structure is also attached and program productivity and maintenance can be improved. Host machine OS PC-9800 series MS-DOS TM Ordering code Supply medium 3.5-inch 2HD 5-inch 2HD (product name) µS5A13RA78K3 µS5A10RA78K3 µS7B13RA78K3 µS7B10RA78K3 µS3P16RA78K3 µS3K15RA78K3 µS3R15RA78K3 IBM PC/AT TM PC DOS TM 3.5-inch 2HC 5-inch 2HC and compatible machine HP9000 series 700TM SPARCstationTM NEWS 78K/III Series C compiler (CC78K/III) TM HP-UXTM SunOSTM NEWS-OS TM DAT Cartridge tape (QIC-24) C compiler common to the 78K/III series. This is a program to convert a program written in C language into an object code executable with a microcontroller. When using the compiler, 78K/III series relocatable assembler(RA78K/III) is necessary. Host machine OS PC-9800 series MS-DOS Supply medium 3.5-inch 2HD 5-inch 2HD IBM PC/AT TM Ordering code (product name) µS5A13CC78K3 µS5A10CC78K3 µS7B13CC78K3 µS7B10CC78K3 µS3P16CC78K3 µS3K15CC78K3 µS3R15CC78K3 PC DOS 3.5-inch 2HC 5-inch 2HC and compatible machine HP9000 series 700 SPARCstation NEWS HP-UX SunOS NEWS-OS DAT Cartridge tape (QIC-24) Remark The operation of the relocatable assembler and C compiler is guaranteed only on the host machine under the operating systems listed above. 41 µPD78P328 PROM Write Tools Hardware PG-1500 PG-1500 is a PROM programmer which enables you to program single chip microcontrollers containing PROM by stand-alone or host machine operation by connecting an attached board and optional programmer adapter to PG-1500. It also enables you to program typical PROM devices of 256K bits to 4M bits. UNISITE 2900 PA-78P328CW PA-78P328GF PROM programmer adapters to write programs onto the µPD78P328 on a general purpose PROM programmer such as PG-1500. PA-78P328CW ... µPD78P328CW and 78P328DW PA-78P328GF ... µPD78P328GF Software PG-1500 controller Connects PG-1500 and a host machine by a serial or parallel interface and controlls PG-1500 on the host machine. Host machine OS PC-9800 series MS-DOS Supply medium 3.5-inch 2HD 5-inch 2HD IBM PC/AT and compatible machine PC DOS 3.5-inch 2HD 5-inch 2HC Ordering code (product name) PROM programmer manufactured by Data I. O. Japan. µS5A13PG1500 µS5A10PG1500 µS7B13PG1500 µS7B10PG1500 Remark The operation of the PG-1500 controller is guaranteed only on the host machine under the operating systems listed above. Debugging Tools Hardware EP-78327CW-R EP-78327GF-R IE-78327-R IE-78327-R is an in-circuit emulator that can be used for application system development and debugging. Emulation probe for 64-pin plastic shrink DIP to connect IE-78327-R to the target system. Emulation probe for 94-pin plastic QFP to connect IE-78327-R to the target system. EV-9200G-64 One conversion socket EV-9200G-64 used for connection to the target system is attached. Software IE-78327-R control program (IE controller) Program to control IE-78327-R on a host machine. Automatic execution of commands, etc., is enabled for more efficient debugging. Host machine OS PC-9800 series MS-DOS Supply medium 3.5-inch 2HD 5-inch 2HD IBM PC/AT and compatible machine PC DOS 3.5-inch 2HD 5-inch 2HC Ordering code (product name) µS5A13IE78327 µS5A10IE78327 µS7B13IE78327 µS7B10IE78327 Remark The operation of the IE controller is guaranteed only on the host machine under the operating systems listed above. 42 µPD78P328 Development Tool Configuration Host machine PC-9800 series or IBM PC/AT RS-232C Emulation probe Software IE-78327-R In-circuit emulator RS-232C PROM programmer PG-1500 IE controller Relocatable controller assembler (with structure assembler) EP-78327GF-R EP-78327GF-R + + Socket to connect emulation probe and target systemNote On-chip PROM version PG-1500 EV-9200G-64 SDIP socket µPD78P328GF µPD78P328CW µPD78P328DW + + Programmer adapter + Target system PA-78P328GF PA-78P328CW Note The socket is attached to the emulation probe. Remarks 1. The host machine and PG-1500 can be connected directly by RS-232-C. 2. Supply media of software are represented as 3.5-inch floppy disks in the figure above. 43 µPD78P328 B.2 Evaluation Tools The following evaluation tools are provided to evaluate the µPD78P328 function: Ordering Code (product name) EB-78327-98 PC-9800 series The µPD78P328 function can be easily evaluated by connecting the evaluation tool to a host machine. The EB-78327-98/PC command system basically is compliant with the EB-78327-PC IBM PC/AT and compatible machine IE-78327-R command system. Thus, easy transition to application system development process by IE-78327-R can be made. The evaluation tools enable turbo access manager (µPD71P301)Note to be mounted on the printed circuit board. Host Machine Function Note Turbo access manager (µPD71P301) is available for maintenance purpose only. Cautions 1. 2. EB-78327-98/PC is not the µPD78P328 application system development tool. EB-78327-98/PC does not contain the emulation function at internal PROM execution of the µPD78P328. B.3 Embedded Software The following embedded software products are readily available to support more efficient program development and maintenance: Real-time OS Real-time OS (RX78K/III) The purpose of RX78K/III is to realize a multi-task environment in a control area which requires real-time processing. RX78K/III allocates idle times of CPU to other processing to improve overall performance of the system. RX78K/III provides a system call based on the µITRON specification. RX78K/III assembler package provides the RX78K/III nucleus and a tool (configurator) to prepare multiple information tables. Host machine OS PC-9800 series MS-DOS Supply medium 3.5-inch 2HD 5-inch 2HD IBM PC/AT and compatible machine PC DOS 3.5-inch 2HC 5-inch 2HC Ordering code (product name) µS5A13RX78320 µS5A10RX78320 µS7B13RX78320 µS7B10RX78320 Caution When purchasing the RX78K/III, fill in the purchase application form in advance, and sign the User's Agreement. Remark When using the RX78K/III Real-time OS, the RA78K/III assembler package (option) is necessary. 44 µPD78P328 Fuzzy Inference Development Support System Fuzzy knowledge Data Preparation Tool (FE9000, FE9200) Host machine OS PC-9800 series MS-DOS Supply medium 3.5-inch 2HD 5-inch 2HD IBM PC/AT and compatible machine Translator (FT78K3)Note PC DOS WindowsTM 3.5-inch 2HC 5-inch 2HC Ordering code (product name) Program supporting input of fuzzy knowledge data (fuzzy rule and membership function), input/editing (edit), and evaluation (simulation). µS5A13FE9000 µS5A10FE9000 µS7B13FE9200 µS7B10FE9200 Program converting fuzzy knowledge data obtained by using fuzzy knowledge data preparation tool to the assembler source program for the RA78K/III. Host machine OS PC-9800 series MS-DOS Supply medium 3.5-inch 2HD 5-inch 2HD IBM PC/AT and compatible machine PC DOS 3.5-inch 2HC 5-inch 2HC Ordering code (product name) µS5A13FT78K3 µS5A10FT78K3 µS7B13FT78K3 µS7B10FT78K3 Fuzzy Inference Module (FI78K/III)Note Program executing fuzzy inference. Fuzzy inference is executed by linking fuzzy knowledge data converted by translator. Host machine OS PC-9800 series MS-DOS Supply medium 3.5-inch 2HD 5-inch 2HD IBM PC/AT and compatible machine PC DOS 3.5-inch 2HC 5-inch 2HC Ordering code (product name) µS5A13FI78K3 µS5A10FI78K3 µS7B13FI78K3 µS7B10FI78K3 Fuzzy Inference Debugger (FD78K/III) Support software evaluating and adjusting fuzzy knowledge data at hardware level by using in-circuit emulator. Host machine OS PC-9800 series MS-DOS Supply medium 3.5-inch 2HD 5-inch 2HD IBM PC/AT and compatible machine PC DOS 3.5-inch 2HC 5-inch 2HC Ordering code (product name) µS5A13FD78K3 µS5A10FD78K3 µS7B13FD78K3 µS7B10FD78K3 Note Under development 45 CHAPTER 2 PIN FUNCTIONS [MEMO] 46 µPD78P328 NOTES FOR CMOS DEVICES (1) PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. (2) HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. (3) STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. QTOP is a trademark of NEC Corporation. MS-DOS and Windows are trademarks of Microsoft Corporation. PC/AT and PC DOS are trademarks of IBM Corporation. HP9000 series 700 and HP-UX are trademarks of Hewlett-Packard Company. SPARCstation is a trademark of SPARC International, Inc. SunOS is a trademark of Sun Microsystems, Inc. NEWS and NEWS-OS are trademarks of Sony Corporation. TRON is an abbreviation of The Realtime Operating system Nucleus. ITRON is an abbreviation of Industrial TRON. 47 µPD78P328 The export of these products from Japan is regulated by the Japanese government. The export of some or all of these products may be prohibited without governmental license. To export or re-export some or all of these products from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales representative. License not needed: µPD78P328DW The customer must judge the need for license: µPD78P328CW, 78P328GF-3BE No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customer must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. NEC devices are classified into the following three quality grades: "Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computer, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices in "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact NEC Sales Representative in advance. Anti-radioactive design is not implemented in this product. M4 94.11