NJW4302FA1

NJW4302 Preliminary THREE-PHASE DC BRUSHLESS MOTOR CONTROL IC s GENERAL DESCRIPTION The NJW4302 is a three-phase DC brushless motor pre-driver IC for precision applications. The NJW4302 consists of PWM driver, motor velocity control, FG(Frequency Generator) output, and voltage velocity integration circuit. The NJW4302 realizes stabilized velocity and it is suitable for printer, FAX, and other DC motor control systems. s PACKEGE OUTLINE NJW4302FA1 s FEATURES Speed discriminator and PLL speed control circuit Direct PWM driver CR oscillator Lock protection output Break circuit (short circuit braking) Start/stop switch Start/Stop Switch Circuit Current limit circuit Thermal shut down/Under voltage lockout circuit FG output amplifier/Integrating circuit Shunt regulator output : 5V Bi-CMOS technology PACKAGE OUTLINE QFP44 • • • • • • • • • • • • s PIN CONFIGRATION WL VH VL UH UL RF H3 H3 H2 H2 H1 WH PVCC VCC VREG DGND AGND VSH CR CROCK R C H1+ FGIN+ FGINFGOUT FGSOUT NJW4302 QFP44 PGND AGND N2 N1 SS CLK FILO FILI TOC INT IN POUT LD DOUT INTOUT INTREF BR FR sBLOCK DIAGRAM FGO FGSO O D o ut LD F C R OC K IN TR E IN TIN IN TOU TS/S R OC K OSC BR F/R V+ F LD FGINFGIN+ - IN TEGR ATION AMP BR F/R + + FG SPEED D I SC RIMI N ATOR L OGIC H AL L H YS AMP H1+ H1 H2+ H2 H3+ H3 - S/S Pou t Vreg VSH VC O U T O PR OTEC TION ALTER N ATIVE SPEE D PL L VR EG 1 VR EF CLK P LL C OU N TER P WM B LOC K C IR C U IT TS D / L VD S P R I D R IVER - C OU N TER C IR CU IT FILI FILO R C N1 N2 GN D C R R F TOC U L VL WL U H VH WH -1- NJW4302 Preliminary sPIN DESCRIPTION SYMBOL H1+,H1H2+,H2H3+,H3UH VH WH UL VL WL VPCC VCC VREG PGND.DGND AGND VSH PIN No. 33, 34 35, 36 37, 38 41 43 1 40 42 44 2 3 4 5,6 27,28 7 Power-supply voltage pin Connect a noise decoupling capacitor between these pins and the ground. Shunt regulator output pin Ground pins These pins are all connected internally to the ground(GND). Shunt regulator ON/OFF output pin “H” or open:ON “L”:OFF CR 8 PWM oscillator frequency setting pin Three blocks use the oscillator: motor constraint detection circuit, clock disconnection protection circuit and others CROCK R C 9 10 11 Reference clock signal oscillator pin Connect a capacitor between this pin to the ground.This oscillator provides clock signal when motor is locked. VCO oscillation frequency setting pin Connect a resistor between this pin and the ground. VCO oscillation frequency setting pin Connect a resister between this pin and ground. Set the value of the capacitor so that the oscillator frequency does not exceed 1MHz. FILI 13 VCO filter amplifier input pin This pin is connected to VCO PLL output with 10KΩ resistor internally in the IC. FILO D OUT P OUT LD 12 18 19 20 VCO filter amplifier output pin This pin is connected to VCO circuit internally in the IC. Speed discriminator output pin Output“L”level for over speed. PLL output pin Output the phase comparison result for 1/2fCLK and1/2fFG. Lock detection output pin Open collector becomes“L”within the speed lock range(±6.25). INT REF INT IN INT OUT TOC 14 17 16 15 Integrating amplifier forward rotation input(a potential of 1/2V+) Negative input for Integration amplifier Output for Integration amplifier Torque command input pin This pin is normally connected to the INT OUT pin. When the TOC voltage level falls,the UL,VL and Wl PWM duties are changed to increase. FG IN+ 32 Input pin for FG amplifier forward rotation (a potential of 1/2V+) Connect a noise decoupling capacitor between V+ terminal and the ground. Output pins(open collector sink outputs). Duty control implement with PWM signal. Output pins(for fixed current source ) DESCRIPTION Hall input pins Positive input terminal is defined as IN+,Negative input terminal as IN- respectably. Positive input is defined as IN+> IN- as Negative. -2- NJW4302 Preliminary FG INFGOUT FGSOUT 31 30 29 FG amplifier reverse rotation input. FG amplifier output. FG amplifier output(after the schmitt) Open collector output. RF 39 Output current detection Connect a resistor between this pin and GND pin.The output limitation maximum current(IOUT)is set to be 0.5/Rf. SS 24 Start⋅Stop control “L”:Start “H”or Open:Stop FR 22 Forward/reverse rotation control “L”:Forward “H”or Open:reverse BR 21 Brake control (short braking operation) “L”:Start “H”or Open:Brake CLK N1 N2 23 25 26 External clock signal input 10kHz max. Speed discriminator count switching -3- NJW4302 Preliminary s FUNCTIONAL DESCRIPTION 1. VCO circuit The variable range of PLL circuit is determined by two factors: VCO frequency determined by RC value connected to Pin 15 and Pin 16 and VCO loop filter constants. VCO frequency range must be within 160kHZ to 1.0MHZ. The typical external value is as follows: R=20kΩ,C=100pF. The filter constants are C=0.47µF,R=27kΩ. 2. Output drive circuit The PWM control is made by upper side of external transistor. 3. Speed lock range The speed lock range is ±6.25% of fixed speed. When the motor speed is within the lock range, the LD pin (an open collector output)goes “L”. If the motor speed goes out of the lock range, the LD pin goes “H”. Please be noted that the LD signal may go on during startup. 4. PWM frequency The PWM frequency is determined by resistor and capacitor value connected to the CR pin. The PWM frequency is given by expressed as: fPWM=1/(0.48CR) When C=1500pF,R=75KΩ,the PWM frequency goes about 19KHz. 5. Lock detection circuit(CLOCK) Lock detection circuit protects the driver IC and the motor from fatal over current failure when the motor is locked during startup. If the LD output remains “H” (motor lock state) for a certain period (Hold time),all phase of upper side transistors are to be turned off. The hold time can be programmed by capacitor value attached to the CLOCK pin by the following: Set time(sec) =66×C(µF) With C=0.068µF,the hold time can be programmed for approximately 4.5 sec. Once Lock detection circuit is activated, the state remains unchanged unless it is turned off, or stopped. This function can be disabled when the CLOCK pin is connected to the ground. 6. Forward / Reverse(F/R)Switching The direction control can be made with the state of the F/R pin. The direction can be changed even during the motor in motion. -4- NJW4302 Preliminary 7. Brake Switch NJW4302 uses a short brake method that turns on all phase of upper side transistors for braking. During the time, all lower side transistors are turned off. 8. VREG pin/VSH pin NJW4302 includes a regulator to generate for +5V regulated IC supply when the motor drive circuit is designed with a single power supply. The VREG pin and V+ pin compose a shunt regulator for 5V±5% output with a external resistor and a transistor. To use the regulator, the VSH pin must be either “H”, or Open. Otherwise, the VSH pin must be “L” and the VREG pin is to be opened. 9. Frequency Generator (FG) Amplifier The internal FG amplifier with few passive components composes a filter amplifier shown in the application. Circuit for noise rejection. The output voltage of the amplifier must be at least 250mA p-p since it feature Schmitt comparator. The capacitor connected between the FGIN+ pin and the ground is necessary for bias voltage stabilization and initial reset pulse generation for the internal logic. The reset pulse is generated when the FGIN+ pin goes from 0 to approximately 1.25V. 10. Integration Amplifier The integration amplifier integrates the D-out and P-out and converts them to speed command voltage. During the time, it also sets the control loop gain and frequency characteristics using external components. 11. Speed Control Circuit NJW4302 features two speed control method; speed discriminator circuit with PLL circuit and phase comparison circuit. The FG pulse frequency is controlled to be the same frequency with a clock frequency input to the CLK pin. Therefore, the motor speed can be controlled by changing the clock frequency. The motor speed (N) can be expressed as: N=CLK (Hz)×(60/FGP)[RPM] ( FGP: Number of FG pulse per one rotation) Given that the oscillation frequency range is 160kHz~1.0MHZ and the number of counts is 1024,the range of clock frequency is 156HZ~960HZ , and therefore the motor speed can be changed from 260rpm to 1600rpm. -5- NJW4302 Preliminary sABSOLUTE MAXIMUM RATING P ARAMETER SYMBOL TEST CONDITION RATINGS UNIT Ma ximum supply voltage Ma ximum input current Output current Operating temperature Storage temperature Power dissipation V+ Ireg Io Topr Tstg Pd Vreg pin(5.6V) UL,VL,WL 7 10 30 -40∼85 -55 ∼ 150 700 V mA mA °C °C mW sALLOWABLE MAXIMUM RANGES/Ta=25°C PARAMETER Input current range FG Schmitt output applied voltage FG Schmitt output current Lock detection output current Supply voltage SYMBOL IREG VFGSO IFGSO ILD V + CONDITION VREG pin=5.6V RATINGS 1.0~5.0 0~8 0~5 0~20 4.5~5.5 UNIT mA V mA mA V -6- NJW4302 Preliminary sELECTRICAL CHARACTERISTICS / Ta=25°C,V+=5.0V PARAMETER Supply current 1 Supply current 2 Output saturation voltage Output current Output leakage current Output off voltage •HALL AMPLIFIER PARAMETER Input bias current Common mode input voltage range Hall input sensitivity Hysteresis Input voltage Low → High Input voltage High →Low •CR OSCILLATOR PARAMETER Output high level voltage Output low level voltage RC oscillation frequency RC oscillation voltage •CLOCK OSCILLATOR PARAMETER Output high level voltage Output low level voltage External capacitor charge current External capacitor discharge current Clock oscillation frequency RC oscillation voltage SYMBOL ICC1 ICC2 VO (sat) IO IO(leak) VO(off) in stop mode UL,VL and WL terminal Io=20mA UH,VH and WHterminal Vout=1.4V UL,VL,WL output UH,VH,WH output CONDITION MIN. -20 TYP. 38 8 0.2 -16 MAX. 55 18 0.7 -12 100 0.5 UNIT mA mA V mA µA V SYMBOL IHB(HA) VICM ∆VIN(HA) ∆VIN(HA) VSLH VSHL TEST CONDITION MIN. -4 1.5 17 8 -30 TYP. -1 60 32 16 -16 MAX. VCC-1.5 60 30 -8 UNIT µA V mVP-P mV mV mV SYMBOL VOH(CR) VOL(CR) f(CR) V(CR) TEST CONDITION MIN. 2.4 1.3 TYP. 2.7 1.6 19 1.1 MAX. 3.0 1.9 1.3 UNIT V V kHz VP-P UNIT V V µA µA Hz VP-P UNIT V V MHz VP-P R=75kΩ,C=1500pF 0.9 SYMBOL VOH(RK) VOL(RK) ICHG1 ICHG2 f(RK) V(RK) TEST CONDITION MIN. 2.7 0.1 - TYP. 3.0 0.4 -10 10 35 2.6 MAX. 3.3 0.7 2.8 C=0.068µF 2.4 •VCO OSCILLATOR (PLL COUNTER) PARAMETER SYMBOL C-terminal high-level output voltage C-terminal low-level output voltage VCO oscillation frequency Amplitude VOH(C) VOL(C) f(C) V(C) TEST CONDITION MIN. 1.15 0.9 0.15 TYP. 1.25 1.0 0.25 MAX. 1.35 1.1 1.0 0.6 -7- NJW4302 •CURRENT LIMITING OPERATION PARAMETER SYMBOL Limiter •FG AMPLIFIER PARAMETER Input offset voltage Input bias current Output low-level voltage Output high-level voltage FG input sensitivity Schmitt amplifier for next stage Operating frequency range Open loop gain •FGSO OUTPUT PARAMETER Output saturation voltage Output leak current VRF Preliminary TEST CONDITION MIN. 0.47 TYP. 0.52 MAX. 0.57 UNIT V SYMBOL VIO(FG) IB(FG) VOH(FG) VOL(FG) ∆VIN(FG) ∆VSH(FG) ∆FG AV(FG) SYMBOL VO(FGSO) IL(FGSO) TEST CONDITION GAIN =40dB f(FG)=2kHz TEST CONDITION IO(FGS)=2mA VO=V+ MIN. -10 -1 + V -1.5 100 MIN. - TYP. 0 0 + V -1.0 1 3 180 16 51 TYP. 0.1 - MAX. 10 1 1.5 250 MAX. 0.5 10 UNIT mV µA V V mV mV kHz dB UNIT V µA •SPEED DISCRIMINATOR OUTPUT (Dout) PARAMETER SYMBOL TEST CONDITION Output high-level voltage Output low-level voltage VOH(D) VOL(D) MIN. V -1.0 + TYP. V -0.7 0.4 + MAX. - UNIT V V •SPEED CONTROL PLL OUTPUT (Pout) PARAMETER SYMBOL Output high-level voltage Output low-level voltage •LOCK DETECTION (LD) PARAMETER Output saturation voltage Output leak current Lock range VOH(P) VOL(P) SYMBOL VOL(LD) IL(LD) ∆LOCK TEST CONDITION MIN. 3.35 1.35 TYP. 3.65 1.65 TYP. 0.1 - MAX. 3.95 1.95 MAX. 0.5 10 +6.25 UNIT V V UNIT V µA % TEST CONDITION ILD=10mA VO=V + MIN. -6.25 Design target spec -8- NJW4302 •INTEGRATER AMPLIFIER PARAMETER SYMBOL Input offset voltage Input bias current Output high-level voltage Output low-level voltage Open loop gain Gain-band width product Reference voltage VIO(INT) IB(INT) VOH(INT) VOL(INT) AV(INT) GBW(INT) VB(INT) Preliminary TEST CONDITION MIN. -10 -0.4 + V -0.12 2.375 TYP. + V -0.8 0.8 60 1.6 2.5 MAX. 10 0.4 1.2 2.625 UNIT mV µA V V dB MHz V •FILTER AMPLIFIER (PLL COUNTER) PARAMETER SYMBOL Input bias current Output high-level voltage Output low-level voltage Hysteresis •S/S AMPLIFIER PARAMETER Input high-level voltage Input low-level voltage Hysteresis Pull-Up resistance •F/R AMPLIFIER PARAMETER Input high-level voltage Input low-level voltage Hysteresis Pull-Up resistance •BR AMPLIFIER PARAMETER Input high-level voltage Input low-level voltage Hysteresis Pull-Up resistance IB(FIL) VOH(FIL) VOL(FIL) VB(FIL) TEST CONDITION MIN. V -1.2 2.375 + TYP. 0.4 V -0.8 0.8 2.5 + MAX. 1.2 2.625 UNIT µA V V V SYMBOL VIH(S/S) VIL(S/S) ∆VIN(S/S) RU(S/S) TEST CONDITION MIN. 3.5 0 1.0 60 TYP. 4.2 0.8 1.3 80 MAX. V+ 1.0 1.6 100 UNIT V V V kΩ UNIT V V V kΩ UNIT V V V kΩ SYMBOL VIH(F/R) VIL(F/R) ∆VIN(F/R) RU(F/R) TEST CONDITION MIN. 3.5 0 1.0 60 TYP. 4.2 0.8 1.3 80 MAX. V + 1.0 1.6 100 SYMBOL VIH(BR) VIL(BR) ∆VIN(BR) RU(BR) TEST CONDITION MIN. 3.5 0 1.0 60 TPY. 4.2 0.8 1.3 80 MAX. V + 1.0 1.6 100 -9- NJW4302 •CLK AMPLIFIER PARAMETER Input high-level voltage Input low-level voltage Hysteresis Pull-Up resistance Input frequency •N1 AMPLIFIER PARAMETER Input high-level voltage Input low-level voltage Hysteresis Pull-Up resistance •N2 AMPLIFIER PARAMETER Input high-level voltage Input low-level voltage Hysteresis Pull-Up resistance Preliminary SYMBOL VIH(CLK) VIL(CLK) ∆VIN(CLK) RU(CLK) f(CLK) TEST CONDITION MIN. 3.5 0 1.0 60 TPY. 4.2 0.8 1.3 80 16 MAX. V+ 1.0 1.6 100 UNIT V V V kΩ kHz SYMBOL VIH(N1) VIL(N1) ∆VIN(N1) RU(N1) TEST CONDITION MIN. 3.5 0 1.0 60 TYP. 4.2 0.8 1.3 80 MAX. V + UNIT V V V kΩ 1.0 1.6 100 SYMBOL VIH(N2) VIL(N2) ∆VIN(N2) RU(N2) TEST CONDITION MIN. 3.5 0 1.0 60 TYP. 4.2 0.8 1.3 80 MAX. V+ 1.0 1.6 100 UNIT V V V kΩ •UNDER VOLTAGE LOCKOUT PARAMETER SYMBOL Operating voltage Release voltage Hysteresis •SHUNT REGULATOR PARAKMETER Output voltage •VSH AMPLIFIER PARAMETER Input high-level voltage Input low-level voltage Hysteresis Pull-Up resistance VSDL VSDH ∆VSD TEST CONDITION MIN. 0.15 TYP. 3.75 4.0 0.25 MAX. 0.35 UNIT V V V SYMBOL VO(VSH) TEST CONDITION MIN. 4.75 TYP. 5.0 MAX. 5.25 UNIT V SYMBOL VIH(VSH) VIL(VSH) ∆VIN(VSH) RU(VSH) TEST CONDITION MIN. 3.5 0 1.0 60 TYP. 4.2 0.8 1.3 80 MAX. V+ 1.0 1.6 100 UNIT V V V kΩ - 10 - NJW4302 Preliminary s SPEED DISCRIMINATOR COUNT TABLE N1 High or Open High or Open Low Low N2 High or Open Low High or Open Low NUMBER OF COUNTS 128 512 256 1024 s THREE PHASE LOGIC TRUTH TABLE F/R=L H1 1 2 3 4 5 6 H H H L L L H2 L L H H H L H3 H L L L H H H1 L L L H H H F/R=H H2 H H L L L H H3 L H H H L L OUTPUTS Source VH WH WH UH UH VH Sink UL UL VL VL WL WL s S/S TERMINAL High or Open Low s BRAKE TERMINAL High or Open Low Brake Release Stop Start - 11 - NJW4302 Preliminary s TYPICAL APPLICATION VM QVR R14 R13 R12 R10 R9 R11 WL H3+ H2+ H1- VH H3- VL UL H2- UH RF WH PVCC VCC CVR 47u C10 H1+ FGIN+ FGIN- 0.1u 1000p C8 2k 0.47u VREG DGND AGND R1 NJW4302 QFP44 VSH CR CROCK INT OUT INT REF R FILI C FILO DOUT INT IN POUT TOC FGOUT 100k R7 FGSOUT PGND AGND N2 N1 SS CLK BR FR LD R8 C9 FGS VSH C1 C2 R2 C3 75k 1500p 0.047u 20k 100p C R3 27k C4 220p 0.1u C6 0.22u C5 0.47u C7 R5 R6 150k 1 R4 8k 2.4M - 12 - NJW4302 Preliminary s TYPICAL CHARACTERISTICS - 13 - NJW4302 Preliminary s TYPICAL CHARACTERISTICS (Ta=25degC,With standard device) - 14 - NJW4302 Preliminary s APPLICATION NOTE •FG Amplifier FG Amplifier consists of input differential amplifier and output Schmitt-trigger comparator. Input amplifier is constructed as low-pass filter with external resistors and capacitors to reduce noise. The amplifier output level should be over 250mVp-p to adjust gain by external resistors, due to hysteresis of Schmitt-trigger comparator. FG+ input is biased internally to the half level of Vcc. This DC bias voltage is also used to RESET the internal logic circuit. For stable RESET operation, It a capacitor, requires a 0.1 uF capacitor connected to FG+ terminal. RESET is enable a during 0V to 1.25V of the voltage at the FG+. FG Sensor Amplifier Application Circuit 1000p 100k FGO 0.47u 2k FGFG+ 0.1u for Internal logic FGS NJW4302 - 15 - NJW4302 Preliminary • FG interfac for logic output device The circuit below is a FG interface for logic output device (i.e. Hall IC and optical encoder). Two external resistors are required to adjust the input voltage within the common mode input voltage range,0 to Vcc-1.5V. FG interface for logic level input 5V FGO logic 1.5k FG FG + 3.5k FG for Internal logic 0.1u NJW4302 • Power supply generating from Vref To supply for NJM4302, Hall sensor and Power stage, QR1 should have 100mA current capacity. It needs 47 microfarad capacitor on V+ of NJW4302 for ripple filtering. • Hall sensor biasing Hall biasing is determined by Hall signal amplitude. Hall signal amplitude must be larger than input sensitivity of NJW4302. • FG Input Internal FG Amplifier is a differential amplifier which inputs and output are pin-outed. The DC gain of this amplifier, AFG, is: AFG = R7 R8 C8 is for noise reduction, C9 is for DC cut. Typical value of C10 is 0.1 microfarad. The inductor symbol connected FGIN is FG sensing copper pattern on PC board. • Power supply generating from Vref To supply for NJM4302, Hall sensor and Power stage, QR1 should have 100mA current capacity. It needs 47 microfarad capacitor on V+ of NJW4302 for ripple filtering. • Hall sensor biasing Hall biasing is determined by Hall signal amplitude. Hall signal amplitude must be larger than input sensitivity of NJW4302. - 16 - NJW4302 Preliminary • FG Input Internal FG Amplifier is a differential amplifier and both inputs and output are connected to the pin. The DC gain of this amplifier, AFG, is: AFG = R7 R8 The C8 is for compensation or noise reduction, C9 is for DC cut. Typical value of C10 is 0.1 microfarad. inductor symbol connected FGIN is FG sensing copper pattern on PC board. • PWM Frequency PWM clock generates by CR oscillator. The frequency is: f PWM = 1 0.48 ⋅ R1 ⋅ C1 In fig.x*, fPWM is about 19kHz. If fPWM is about 20kHz, it could reduce audible noise. • Variable range of VCO frequency VCO frequency in typical value is recommend 160kHz to 1MHz. External constants is: R2 = 20k ohm, C3 = 100pF, R3 = 27k ohm, C4 = 0.47 uF If it can not be settled into this range, change the division of speed discriminator. • Detecting time of rock protection Detecting time is settled by C2 as follow: t ROCK = 66 ⋅ C 2 In fig.x*, trock is about 3.1 sec. • Integration Amplifier Both speed discriminator output and PLL output should be mixed via two resistors before input to INTIN of Integration Amplifier. Mixing resistor, Timing resistors and capacitors are necessary for good system operation. C6 is need for non-polar type capacitor for good stability. • Upper power transistor To reduce ripple of power line, Upper output transistor is connect NJM4302 via common-base NPN transistors. Minimum output current is 12mA, it is able to drive 1A class transistor. If more current is needed, change the output transistor to Darlington type. Re-circulating diodes is needed on between collector and emitter of output transistor. • Lower power transistor Lower output could drive external power transistor directly to about 1.5A. If more current is needed, change the output transistor to Darlington type. The resistor connected between base and emitter of power transistor is necessary on PWM operation for sharp cut-off of power transistor. When your system have any noise, attach a capacitor in parallel the resistor. Re-circulating diodes is needed on between collector and emitter of output transistor. R11 is a current sensing resistor and settled by following: R11 = VRE IO When VRF is sensing voltage, Io is sensing current. Take care of power dissipation of R11, also. - 17 - NJW4302 Preliminary • Recirculation Diodes Recirculation diodes are recommend to use Shottkey-burrier type. Forward voltage “VF” and reverse returning time “trr” are contributed for power dissipation. [CAUTION] The specifications on this databook are only given for information , without any guarantee as regards either mistakes or omissions. The application circuits in this databook are described only to show representative usages of the product and not intended for the guarantee or permission of any right including the industrial rights. - 18 -