SM5846AP

SM5846AP NIPPON PRECISION CIRCUITS INC. Multi-function Digital Filter Audio ICs OVERVIEW The SM5846AP is a multi-function digital filter that incorporates 4/8 times oversampling digital audio signal reproduction, digital deemphasis, digital attenuation and soft mute functions. The I/O interface allows serial data transmission of 16/20/24/32bit input data and 20/24-bit output data. Filter Construction s FEATURES Functions s s s s s s s s s s s s s s s s s s 8-times oversampling (interpolation) Switchable 8/4 times oversampling output Two master clock frequencies (refer to Clock Functions) • 384fs/512fs (normal-speed sampling) • 192fs/256fs (high-speed sampling) Digital deemphasis • Compatible with 32/44.1/48 kHz (normalspeed) and 64/88.2/96 kHz (high-speed) input sampling frequencies • ON/OFF control Digital attenuator • 128-step attenuation using linear 7-bit data setting Soft muting • 1016/fs (normal-speed sampling) • 2032/fs (high-speed sampling) Output data round-off operation (normal round-off or rectangular distribution dither round-off) Selectable LR clock polarity Microprocessor controllable Input data format • 2s complement, MSB first, alternating L/R serial • 16/20/24/32-bit data selectable Output data format • 2s complement, MSB first, simultaneous L/R serial • 20/24-bit data selectable. 24-bit internal data processing Jitter-free mode/synchronous mode selectable Crystal oscillator circuit built-in TTL-compatible outputs Molybdenum-gate CMOS s Interpolation filter (linear 3-stage FIR filter) • Normal-speed sampling mode 1st stage (fs to 2fs) 121st order 2nd stage (2fs to 4fs) 21st order 3rd stage (4fs to 8fs) 13th order • High-speed sampling mode: 1st stage (fs to 2fs) 177th order 2nd stage (2fs to 4fs) 29th order 3rd stage (4fs to 8fs) 17th order Deemphasis filter (IIR filter) Arithmetic units • 25× 24-bit parallel adder • 32-bit accumulator Overflow limiter built-in Applications s Digital audio equipment PINOUT (TOP VIEW) DIN 1 28 LRCI 27 MDS 26 BCKO 25 WCKO 24 DOL 23 DOR 22 VDD2 21 VSS2 20 ASEL1 19 OBS 18 TEST2 17 TEST1 16 DEEM 15 LRS BCKI 2 VDD1 3 DITH 4 CKEN 5 XTI 6 XTO 7 VSS1 8 SM5846AP CKO 9 CKS 10 ASEL2/MDCK 11 HS/MDT 12 SYNC/MDLE 13 RST 14 ORDERING INFOMATION Device SM5846AP Package 28pin DIP NIPPON PRECISION CIRCUITS—1 SM5846AP PACKAGE DIMENSIONS Unit: mm 28-pin plastic DIP Audio ICs 0° to 15° 13.8 0.2 + 0.3 1.5 − 0.05 3.8 0.1 3.2 0.2 7.7 0.5 2.54 0.45 0.1 4.5 0.3 NIPPON PRECISION CIRCUITS—2 + 0.10 0.25− 0.05 37.3 0.3 15.2 SM5846AP FILTER CHARACTERISTICS Normal-speed Sampling Parameter Passband bandwidth Stopband bandwidth Passband ripple Stopband attenuation Group delay time1 Rating 0 to 0.4535fs 0.5465 to 7.4535fs ±0.0004 dB ≥ 75 dB When CKS is HIGH: 63.89/fs (when SYNC is LOW) and 63.51/fs to 64.26/fs (when SYNC is HIGH) When CKS is LOW: 63.76/fs (when SYNC is LOW) and 63.59/fs to 64.14/fs (when SYNC is HIGH) Audio ICs 1. The time difference due to digital filter operation between the end of serial data input (at rate fs) and the start of serial data output (at rate 8fs). Overall frequency characteristic 0 20 Attenuation (dB) 40 60 80 100 120 140 0.0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 Frequency (fs) Passband frequency characteristic Attenuation (dB) -0.0005 -0.00025 0.00000 0.00025 0.0005 0.000 0.125 0.250 0.375 0.500 Frequency (fs) Transition band characteristic 0 20 40 60 80 100 120 140 0.00 0.125 0.25 0.375 0.50 0.625 0.75 0.825 1.00 Attenuation (dB) Frequency (fs) NIPPON PRECISION CIRCUITS—3 SM5846AP High-speed Sampling (8fs Output) Parameter Passband bandwidth Stopband bandwidth Passband ripple Stopband attenuation Group delay time1 Rating 0 to 0.4535fs 0.5465 to 7.4535fs ±0.00001 dB ≥ 105 dB When CKS is HIGH: 51.91/fs (when SYNC is LOW) and 51.53/fs to 52.28/fs (when SYNC is HIGH) When CKS is LOW: 51.78/fs (when SYNC is LOW) and 51.40/fs to 52.15/fs (when SYNC is HIGH) Audio ICs 1. The time difference due to digital filter operation between the end of serial data input (at rate fs) and the start of serial data output (at rate 8fs). Overall frequency characteristic 0 20 40 60 80 100 120 140 0.0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 Attenuation (dB) Frequency (fs) Passband frequency characteristic -0.0001 Attenuation (dB) -0.00005 0.00000 0.00005 0.0001 0.000 0.125 0.250 0.375 0.500 Frequency (fs) Transition band characteristic 0 20 40 60 80 100 120 140 0.00 0.125 0.25 0.375 0.50 0.625 0.75 0.825 1.00 Attenuation (dB) Frequency (fs) NIPPON PRECISION CIRCUITS—4 SM5846AP High-speed Sampling (4fs Output) Parameter Passband bandwidth Stopband bandwidth Passband ripple Stopband attenuation Group delay time1 Rating 0 to 0.4535fs 0.5465 to 7.4535fs ±0.00001 dB ≥ 104 dB When CKS is HIGH: 50.78/fs (when SYNC is LOW) and 50.40/fs to 51.15/fs (when SYNC is HIGH) When CKS is LOW: 50.77/fs (when SYNC is LOW) and 50.40/fs to 51.15/fs (when SYNC is HIGH) Audio ICs 1. The time difference due to digital filter operation between the end of serial data input (at rate fs) and the start of serial data output (at rate 8fs). Overall frequency characteristic 0 20 Attenuation (dB) 40 60 80 100 120 140 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 Frequency (fs) Passband frequency characteristic -0.0001 Attenuation (dB) -0.00005 0.00000 0.00005 0.0001 0.000 0.125 0.250 0.375 0.500 Frequency (fs) Transition band characteristic 0 20 40 60 80 100 120 140 0.125 0.25 0.375 0.50 0.625 0.75 0.825 1.00 Attenuation (dB) Frequency (fs) NIPPON PRECISION CIRCUITS—5 SM5846AP Deemphasis Filter Characteristics (Normal-speed Sampling) Parameter Sampling frequency (fs) Passband bandwidth Deviation from ideal characteristics Attenuation Phase 32 kHz 0 to 14.5 kHz Rating 44.1 kHz 0 to 20.0 kHz ±0.01 dB 0 to 6° 48 kHz 0 to 21.7 kHz Audio ICs Deemphasis passband characteristic (logarithmic scale) The phase traces are from top to bottom fs = 32/44.1/48 kHz, respectively. 0 Attenuation (dB) 2 4 6 8 10 10 20 50 100 200 500 1k 2k 5k 10k 20k Attenuation Phase 0 -20 -40 -60 Phase θ ( ° ) Phase θ ( ° ) Frequency (Hz) Deemphasis passband characteristic (linear scale) The phase traces are from top to bottom fs = 32/44.1/48 kHz, respectively. 0 Attenuation (dB) 2 4 6 8 10 Phase 0 -20 -40 -60 Attenuation 0 4k 8k 12k 16k 20k 22k 24k Frequency (Hz) NIPPON PRECISION CIRCUITS—6 SM5846AP Deemphasis Filter Characteristics (High-speed Sampling) Parameter Sampling frequency (fs) Passband bandwidth Deviation from ideal characteristics Attenuation Phase 64 kHz 0 to 29.0 kHz Rating 88.2 kHz 0 to 40.0 kHz ±0.001 dB 0 to 1° 96 kHz 0 to 43.5 kHz Audio ICs Deemphasis passband characteristic (logarithmic scale) The phase traces are from top to bottom fs = 64/88.2/96 kHz, respectively. 0 Attenuation (dB) 2 4 6 8 10 10 20 50 100 200 500 1k 2k 5k 10k 20k Attenuation Phase 0 -20 -40 -60 Phase θ ( ° ) Frequency (Hz) Deemphasis passband characteristic (linear scale) The phase traces are from top to bottom fs = 64/88.2/96 kHz, respectively. 0 2 Attenuation (dB) 4 6 8 10 0 Phase -20 -40 -60 Attenuation 0 4k 8k 12k Frequency (Hz) 16k 20k 22k 24k NIPPON PRECISION CIRCUITS—7 Phase θ ( ° ) SM5846AP SPECIFICATIONS Absolute Maximum Ratings VSS = 0 V Parameter Supply voltage range Input voltage range Storage temperature range Power dissipation Soldering temperature Soldering time Symbol VDD V IN Tstg PD Tsld tsld Rating −0.3 to 7.0 − 0.3 to V D D + 0.3 −40 to 125 750 255 10 Unit V V °C mW °C s Audio ICs Recommended Operating Conditions VSS = 0 V Parameter Supply voltage range Operating temperature range Symbol VDD Topr Rating 4.5 to 5.5 −20 to 70 Unit V °C DC Electrical Characteristics VDD = 4.5 to 5.5 V, VSS = 0 V, Ta = −20 to 70 °C Rating Parameter Supply current consumption1 HIGH-level input voltage LOW-level input voltage XTI AC-coupled input voltage HIGH-level output voltage LOW-level output voltage XTI HIGH-level input current XTI LOW-level input current LOW-level input current Input leakage current Symbol ID D V IH V IL V INAC VO H VO L IIH IIL IIL ILH All outputs, IO H = −1 mA All outputs, IO L = 2 mA V IN = V D D V IN = V S S Inputs excluding XTI, V IN = V S S Inputs excluding XTI, V IN = DV D D All inputs All inputs Condition min – 0.7VD D – 0.3VD D V D D − 0.4 – – – – – typ 110 – – – – – 10 10 10 – max 130 – 0.3VD D – – 0.4 20 20 20 1.0 mA V V V p-p V V µA µA µA µA Unit 1. V D D = 5.0 V, fsys = 18.432 MHz, 384fs operation, no output load. NIPPON PRECISION CIRCUITS—8 SM5846AP AC Characteristics XTI input timing VDD = 4.5 to 5.5 V, VSS = 0 V, Ta = −20 to 70 °C Rating Parameter Oscillator frequency XTI clock pulse cycle time XTI HIGH-level clock pulsewidth XTI LOW-level clock pulsewidth Symbol fOSC tXI tCWH tCWL Condition min 10 54 24 24 typ – – – – max 18.5 – – – MHz ns ns ns Unit Audio ICs XTI 0.5VDD tCHW tXI RST input timing VDD = 4.5 to 5.5 V, VSS = 0 V, Ta = −20 to 70 °C tCHW Rating Parameter Symbol Condition min When power is applied Reset pulsewidth tRST At all other times 1 50 typ – – max – – µs ns Unit RST 0.5VDD tRST NIPPON PRECISION CIRCUITS—9 SM5846AP Serial data input timing (BCKI, DIN, LRCI) VDD = 4.5 to 5.5 V, VSS = 0 V, Ta = −20 to 70 °C Rating Parameter BCKI pulse cycle time BCKI HIGH-level pulsewidth BCKI LOW-level pulsewidth DIN setup time DIN hold time BCKI rising edge to LRCI edge time LRCI edge to BCKI rising edge time Symbol tBCY tBCWH tBCWL tDS tDH tBL tLB Condition min 100 50 50 20 20 50 50 typ – – – – – – – max – – – – – – – ns ns ns ns ns ns ns Unit Audio ICs tBCY tBCWH BCKI tBCWL 0.5VDD tDS DIN tDH 0.5VDD VALID VALID tBL tLB LRCI 0.5VDD NIPPON PRECISION CIRCUITS—10 SM5846AP Microprocessor serial interface timing (MDCK, MDT, MDLE) VDD = 4.5 to 5.5 V, VSS = 0 V, Ta = −20 to 70 °C Rating Parameter MDCK pulse cycle time MDCK HIGH-level pulsewidth MDCK LOW-level pulsewidth MDT setup time MDT hold time MDCK rising edge to MDLE edge time MDLE edge to MDCK rising edge time MDLE HIGH-level pulsewidth MDLE LOW-level pulsewidth Symbol tMCY tMCWH tMCWL tMDS tMDH tMCL tMLC tMLWH tMLWL Condition min 100 50 50 20 20 50 50 20 20 typ – – – – – – – – – max – – – – – – – – – ns ns ns ns ns ns ns ns ns Unit Audio ICs tMCY tMCWH MDCK tMCWL 0.5VDD tMDS MDT tMDH 0.5VDD tMCL MDLE tMCL 0.5VDD tMLWL tMLWH NIPPON PRECISION CIRCUITS—11 SM5846AP Output signal timing (CKO, BCKO, DOR, DOL, WCKO) VDD = 4.5 to 5.5 V, VSS = 0 V, Ta = −20 to 70 °C, CL = 15 pF Rating Parameter Symbol tCKH tCKL tsbH XTI to BCKO propagation delay time tsbL tsbH tsbL BCKO to DOR propagation delay time BCKO to DOL propagation delay time BCKO to WCKO propagation delay time tbdH tbdL tbdH tbdL tbdH tbdL Normal and high-speed mode 4fs output High-speed mode 8fs output Condition min – – – – – – −5 −5 −5 −5 −5 −5 XTI to CKO propagation delay time typ 17 17 20 20 20 20 – – – – – – max 35 ns 35 60 60 ns 60 60 15 ns 15 15 ns 15 15 ns 15 Unit Audio ICs CKO output XTI 0.5V DD tCKH CKO tCKL 1.5V NIPPON PRECISION CIRCUITS—12 SM5846AP BCKO output XTI 0.5VDD Audio ICs tsbH BCKO *1 1.5V tsbL BCKO *2 tsbH 1.5V tsbL *1 : High speed mode 8fs output *2 : Normal and high-speed mode 8fs output DOR, DOL, WCKO output BCKO 1.5V tbdH DOR DOL WCKO tbdL 1.5V NIPPON PRECISION CIRCUITS—13 SM5846AP PIN DESCRIPTION Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 Name DIN BCKI VDD1 DITH CKEN XTI XTO VSS1 CKO CKS ASEL2/MDCK HS /MDT SYNC/MDLE RST LRS DEEM TEST1 TEST2 OBS ASEL1 VSS2 VDD2 DOR DOL WCKO BCKO MDS LRCI I/O1 Ip Ip – Ip Ip I O – O Ip Ip Ip Ip Ip Ip Ip Ip Ip Ip Ip – – O O O O Ip Ip Data input Bit clock input 5 V supply voltage Dither ON/OFF control Crystal oscillator operation enable Crystal oscillator input/external clock input Crystal oscillator output Ground Master clock output Master clock input frequency select Operating mode select/microprocessor interface clock input Operating mode select/microprocessor interface data input Sync mode select/microprocessor interface latch enable input Reset input LR clock polarity select Deemphasis ON/OFF select Test pin 1. Tie HIGH or leave open for normal operation. Test pin 2. Tie LOW for normal operation. Output data length select Operating mode select Ground 5 V supply voltage Right-channel data output Left-channel data output Word clock output Output data bit clock output Mode set method select LR clock input Description Audio ICs 1. Ip = input pin with pull-up resistor, I = input, O = output NIPPON PRECISION CIRCUITS—14 SM5846AP BLOCK DIAGRAM Audio ICs DOR DOL BCKO WCKO OBS DITH VDD2 CKEN VDD1 VSS2 ASEL2/MDCK CKO CKS Clock Generator Reset Circuit Output data Interface (serial output) Arithmetic Block Control DIN BCKI LRCI LRS Output data Interface (serial input) Control Control Micro controller Interface (serial input) Operation Mode Control SYNC/MDLE HS/MDT TEST2 TEST1 DEEM NIPPON PRECISION CIRCUITS—15 ASEL1 MDS VSS1 XTO RST XTI SM5846AP SYSTEM CONFIGURATION Setting +5V TEST2 MDS HS/MDT ASEL1 ASEL2/MCK SYNC/MLE DEEN DITH LRS OBS TEST1 DIN BCKI LRCI CKEN DOR DOL BCKO WCKO DAC VDD1 VSS1 VSS2 XTO CKS VDD2 CKO DSP Setting +5V Oscilation Control RST XTI Reset Circuits DATA FLOW ATT1/ATT2 soft muting uses the D-ATT function to set the gain to −∞ . Normal-speed sampling (fs = 32/44.1/48 kHz) FIRI IN (fs) fs 2fs SWa (121 order) LPF (×2) 2fs DEMI 2fs 2fs 2fs DLY 2fs ATT1 2fs 2fs (D-ATT / Soft Mute) FIR2 LPF (×2) 4fs (21 order) 4fs FIR3 LPF (×2) 8fs (13 order) 8fs OUT (8fs) High-speed sampling (fs = 64/88.2/96 kHz) FIR4 fs 2fs SWb(177 order) LPF (×2) 2fs FIR5 LPF (×2) 4fs (29 order) 4fs DEM2 4fs 4fs SWd(ON / OFF) ATT2 4fs 4fs (D-ATT / Soft Mute) FIR6 LPF (×2) 8fs (17 order) 8fs IN (fs) 8fs/4fs SWg ( 8fs / 4fs ) OUT ( 8fs / 4fs ) 4fs NIPPON PRECISION CIRCUITS—16 SM5846AP FUNCTIONAL DESCRIPTION Mode Switching and Function Switching The SM5846AP supports several operating modes and function switches. Internal control flags, set by the digital inputs or serial data input signal from a microprocessor, determine the status of those function switches. Mode switching/function switch controls Control request Stage System Name Input MDS HS Operating mode switch ASEL2 ASEL1 CKS Clock switch CKEN DEEM FSEL2 Filter switch FSEL1 MUTE DITH SYNC LRS Input interface switch IBS2 IBS1 Output interface switch OBS Yes Yes Input data length set Yes Yes Output data length set Yes (pos. logic) Yes Yes Yes Yes Yes Yes Deemphasis filter sampling frequency set Yes Yes Yes (neg. logic) Yes Mute ON/OFF control Dither ON/OFF control Jitter-free/sync mode switching LRCI (LR clock) input polarity switching Crystal oscillator operating control switching Deemphasis ON/OFF switching Yes Yes Yes Yes Yes Yes Yes Yes Input clock frequency switching Operating mode switching Control flag IC control request switch (input pin/control flag) Function Control request switching MDS input and device control Input pin functions when MDS is LOW Mode switching/function switching is performed under All pins that are part of the microprocessor interface input pin control when MDS is HIGH, and under internal can be used whenever MDS is LOW. flag control when MDS is LOW. Pin name MDS 1 HIGH LOW Control request Input pins Control flags HS /MDT ASEL2/MDC K SYNC/MDLE CKS CKEN LRS Function Serial data transfer data clock Serial data transfer clock input Serial data transfer latch enable input CKS function switch input CKEN function switch input LRS function switch input Input pin control only because there is no corresponding control flag. Used for the microprocessor interface Notes 1. Switching MDS during device operation is prohibited. NIPPON PRECISION CIRCUITS—17 SM5846AP Control flag functions when MSD is HIGH (default) Other requests are controlled by internal flag only because there is no corresponding input pin. These control flags are valid when MDS is HIGH. The default values are shown in the following table. Flag name FSEL2 FSEL1 MUTE IBS2 IBS1 Default value HIGH HIGH HIGH LOW 16-bit input data length HIGH Default setting 44.1 kHz deemphasis filter sampling frequency Muting OFF Clock Functions Input clock frequency switching (CKS) This switch is used to select the input clock frequency—384fs or 512fs (normal-speed sampling), and 192fs or 256fs (high-speed sampling). System clock CKS Input sampling frequency fs (kHz) Frequency (MHz) 32 LOW 64 32 44.1 48 HIGH 64 88.2 96 12.288 16.9344 18.432 192fs High-speed sampling mode 16.384 12.288 16.9344 18.432 384fs Normal-speed sampling mode 256fs High-speed sampling mode 16.384 (× fs) 512fs Notes Normal-speed sampling mode Crystal oscillator control switch (CKEN) This switch is used to start/stop the crystal oscillator circuit. CKEN HIGH LOW Crystal oscillator operation Oscillating Stopped NIPPON PRECISION CIRCUITS—18 SM5846AP Crystal oscillator circuit The built-in crystal oscillator circuit comprises a feedback resistor and several logic gates. The system clock can be generated using an external quartz crystal and 2 capacitors. System Clock Rf CKEN XTI X'tal C1 XTO CKO Oscilation/Stop Contorol C2 System Clock Output External clock When an external clock is used, XTO is left opencircuit and the clock signal is input on XTI. System Clock Rf CKEN XTI XTO Open CKO Oscilation/ Stop Contorol External Clock Input System Clock Output NIPPON PRECISION CIRCUITS—19 SM5846AP Other control settings Input data length select Filter Stage Operating mode The SM5846A supports 3 different operating modes to control output data rate switching. The operating mode is selected by the state of HS, ASEL1 and ASEL2. Operating mode1 The length is set to the default value of 16 bits (IBS2 = LOW and IBS1 = HIGH) after a reset. HS ASEL1 ASEL2 Speed HIGH LOW HIGH HIGH LOW HIGH LOW Normal-speed sampling High-speed sampling Oversampling 8-times 8-times 4-times ISB1 and ISB2 flags are used to set the input data length. IBS2 HIGH HIGH LOW LOW IBS1 HIGH LOW HIGH LOW Input data length 20 bits 24 bits 16 bits 32 bits Notes LRCI input polarity select Pin LRS is used to set the LRCI input polarity. LRS HIGH HIGH LOW LOW LRCI HIGH LOW HIGH LOW Input channel Left Right Right Left 1. Only the above 3 modes are valid. Operating speed and sampling frequency The SM5846AP supports sampling frequencies of 32/44.1/48 kHz (normal-speed sampling mode) and 64/88.2/96 kHz (high-speed sampling mode). Operating speed Normal-speed sampling Input sampling frequency 32/44.1/48 kHz 64/88.2/96 kHz Sync mode select High-speed sampling The SYNC pin or flag setting can be used to select either jitter-free mode or sync mode to control synchronization between input data and internal arithmetic blocks. SYNC HIGH LOW Mode Jitter-free mode Sync mode Notes The SYNC flag is set HIGH (default) after a reset. Deemphasis filter The SM5846AP contains a digital deemphasis filter controlled by DEEM. DEEM HIGH LOW Deemphasis ON OFF The sampling frequency is selected by FSEL1 and FSEL2. Sampling frequency fs (kHz) FSEL2 FSEL1 Normal-speed sampling 44.1 48 44.1 32 High-speed sampling 88.2 96 88.2 64 HIGH HIGH LOW LOW HIGH LOW HIGH LOW Digital attenuator The digital attenuator is controlled by serial data from the microprocessor interface. This data can set attenuation and muting. Note that the digital attenuator is only enabled when MDS is LOW. ATT1 and ATT2 are used to set the attenuation in normal-speed sampling and high-speed sampling, respectively. NIPPON PRECISION CIRCUITS—20 SM5846AP Attenuation setting The data stored in the D-ATT attenuation register, accessed through the microprocessor interface, determines the attenuation setting of the digital attenuator. The D-ATT register data format is shown below. bit1 "0" bit2 a1 bit3 a2 bit4 a3 bit5 a4 bit6 a5 bit7 a6 bit8 a7 MSB LSB DATT attenation data (7bit) Register information The attenuation setting is given by the following equations. Attenuation = 0 [dB] 127 – D ATT A ttenuation = 20log 10  ------------------------------ [dB]   128 A ttenuation = – ∞ ( DATT = 0 ) ( 0 < DATT output data width). The SM5846AP can select either normal round-off or dither round-off on the output data. Round-off processing can be selected either by input pin or control flag settings. DITH pin HIGH HIGH LOW HIGH LOW × LOW × DITH flag Output data round-off Dither round-off Normal round-off Normal round-off Dither round-off The DITH flag is set HIGH (default) after a system reset. Dither round-off Dither round-off is carried out by adding a pseudorandom number between 0 and 1 LSB, derived from a rectangular distribution, to the filter output data to form 20/24-bit output data, depending on the selected output data length. The random number rectangular distribution is shown below (average = 1/2 LSB). M DS Notes Probavility 0 ,,,,,,,, ,,,,,,,, ,,,,,,,, ,,,,,,,, 1/2 1 (LSB) Normal round-off Overflow limiter If an overflow or underflow condition occurs after round-off or filter arithmetic processing, the output data will be fixed at positive or negative maximum value. Normal round-off is carried out by adding 1/2 LSB to the filter output data to form 20/24-bit output data, depending on the selected output data length. NIPPON PRECISION CIRCUITS—22 SM5846AP Audio Data Input Interface Serial data transmission is used for the digital audio data input. The data has the following format: s s Audio data input interface pins Audio data is input using pins LRCI, BCKI, and DIN. The LRCI input polarity is determined by pin LRS. Pin name LRCI BCKI DIN LRS Function Left/right-channel latch clock input Bit transfer clock input Serial data input LRCI input polarity switch Audio ICs s s s 16/20/24/32-bit data length Alternating left/right-channel serial data transmission MSB first Rear packed 2s complement for negative values Serial data on DIN is input to the serial-to-parallel shift register on the falling edge of the bit transfer clock BCKI. The parallel data is then stored in the left/right-channel input buffers on the HIGH/LOWlevel pulse of the LRCI latch clock signal, depending on the selected polarity of the LRCI clock. Audio data input interface schematic 32bit SIPO Shiftregister DIN BCKI D C Q 32bit Register D Left channel C Input Data Buffer Q 32bit Register D Right channel C Input Data Buffer Q LRCI LRS Left channel Input Data Right channel Input Data NIPPON PRECISION CIRCUITS—23 SM5846AP Input data interface example (LRS = HIGH) 32-bit input data length fs Left channel Input Data (MSB) DIN 31 30 29 28 2 1 Audio ICs Right channel Input Data (LSB) 29 28 2 1 0 31 30 (LSB) (MSB) 0 BCKI (64fs) LRCI 24-bit input data length fs Left channel Input Data (MSB) DIN 23 22 2 1 Right channel Input Data (LSB) 0 (MSB) 23 22 2 1 (LSB) 0 BCKI (64fs) LRCI 20-bit input data length fs Left channel Input Data (MSB) DIN 19 18 2 1 Right channel Input Data (LSB) 0 (MSB) 19 18 2 1 (LSB) 0 BCKI (64fs) LRCI 16-bit input data length fs Left channel Input Data (MSB) DIN 15 14 1 Right channel Input Data (LSB) 0 (MSB) 15 14 1 (LSB) 0 BCKI (64fs) LRCI NIPPON PRECISION CIRCUITS—24 SM5846AP Input data validity 32-bit input data length 31 30 Polarity Mark 28 26 24 ,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,, , ,,,,,, ,,, ,,, ,,, ,,, , ,,, , ,,, , ,,, Low order 8 bits cut it off (No round-offattention) 8 6 4 2 0 Decimal point Effective Number of Bits (24bits) Input Data (32bits) 24-bit input data length 23 22 Polarity Mark 20 18 16 6 4 2 0 Decimal point Effective Number of Bits (24Bits) Input Data (24Bits) 20-bit input data length 19 18 Polarity Mark 16 14 4 2 0 0 0 0 0 Decimal point Effective Number of bits (24bits) Input Data (20bits) Input to "0"(4 bits) 16-bit input data length 15 14 Polarity Mark 12 2 0 00000000 Decimal point Effective Number of Bits (24bits) Input Data (16bits) Input to "0"(8 bits) NIPPON PRECISION CIRCUITS—25 SM5846AP Audio Data Output Interface Serial data transmission is used for the digital audio data output. The data has the following format: s s s s s 20/24-bit data length Simultaneous left/right-channel serial data transmission MSB first Bit transfer clock burst (NPC format) 2s complement for negative values Serial data is output on DOL and DOR on the falling edge of the bit transfer clock BCKO. Generally, external circuits, such as a serial D/A converter, sample the serial data output on DOL and DOR on the rising edge of the bit transfer clock signal, and then shift the data into a register. At the completion of one data cycle (20/24-bit selectable) transfer, the word clock WCKO goes LOW with a 50% duty ratio. Then the external circuit writes parallel data to a buffer register on the falling edge of word clock WCKO. Output data length select The output data length is set by either the OBS pin or flag. O BS HIGH LOW Output data length 24 bits 20 bits Notes The OBS flag is set LOW (default) after a system reset. Audio ICs Audio data output interface pins Audio data is output using pins WCKO, BCKO, DOL and DIN. Pin name W CKO BCKO DOL DOR Word clock output Bit transfer clock output Left-channel serial data output Right-channel serial data output Function NIPPON PRECISION CIRCUITS—26 SM5846AP Audio data output interface L-ch Serial DAC DOL D C STB VO VOUT(L-ch) Audio ICs Following Block R-ch Serial DAC DOR BCKO D D C C 20/24bit SIPO Shiftregister WCKO STB D 20/24bit SIPO Shiftregister IN VO DAC VOUT(R-ch) output data format 24-bit output data length 23 22 Polarity Mark 20 18 16 6 4 2 0 Decimal point Output Data (24bits) 20-bit output data length 19 18 Polarity Mark 16 14 4 2 0 Decimal point Output Data (20bits) NIPPON PRECISION CIRCUITS—27 SM5846AP Audio data output timing Normal-speed sampling: 384fs clock, 24-bit data output, 8fs output data rate Audio ICs 1 frame (1/8fs) fCK/2 (192fs) 1 10 12 20 24 WCKO BCKO DOL 23 22 21 20 3 2 1 0 DOR MSB LSB 24bits Normal-speed sampling: 384fs clock, 20-bit data output, 8fs output data rate 1 frame (1/8fs) fCK/2 (192fs) 1 2 10 12 20 21 24 WCKO BCKO DOL 19 18 17 1 0 DOR MSB LSB 20bits NIPPON PRECISION CIRCUITS—28 SM5846AP Normal-speed sampling: 512fs clock, 24-bit data output, 8fs output data rate 1 frame (1/8fs) 1 2 13 14 15 16 17 18 25 30 32 Audio ICs fCK/2 (256fs) WCKO BCKO DOL 23 22 21 0 DOR MSB LSB 24bits Normal-speed sampling: 512fs clock, 20-bit data output, 8fs output data rate 1 frame (1/8fs) fCK/2 (256fs) 1 2 13 14 15 16 17 18 19 20 21 30 32 WCKO BCKO DOL 19 18 17 0 DOR MSB LSB 20bits NIPPON PRECISION CIRCUITS—29 SM5846AP High-speed sampling: 192fs clock, 24-bit data output, 8fs output data rate 1 frame (1/8fs) fCK (192fs) WCKO 1 2 10 12 20 21 24 Audio ICs BCKO DOL 23 22 21 20 3 2 1 0 DOR MSB LSB 24bits High-speed sampling: 192fs clock, 20-bit data output, 8fs output data rate 1 frame (1/8fs) fCK (192fs) 1 2 10 12 20 21 24 WCKO BCKO DOL 19 18 17 1 0 DOR MSB LSB 20bits NIPPON PRECISION CIRCUITS—30 SM5846AP High-speed sampling: 256fs clock, 24-bit data output, 8fs output data rate 1 frame (1/8fs) fCK (256fs) 1 2 13 14 15 16 17 18 25 30 32 Audio ICs WCKO BCKO DOL 23 22 21 0 DOR MSB LSB 24bits High-speed sampling: 256fs clock, 20-bit data output, 8fs output data rate 1 frame (1/8fs) fCK (256fs) 1 2 13 14 15 16 17 18 19 20 21 30 32 WCKO BCKO DOL 19 18 17 0 DOR MSB LSB 20bits NIPPON PRECISION CIRCUITS—31 SM5846AP High-speed sampling: 192fs clock, 24-bit data output, 4fs output data rate 1 frame (1/4fs) fCK/2 (96fs) 1 10 12 20 24 WCKO BCKO DOL 23 22 21 20 3 2 1 0 DOR MSB LSB 24bits High-speed sampling: 192fs clock, 20-bit data output, 4fs output data rate 1 frame (1/4fs) 1 10 12 20 21 24 fCK/2 (96fs) WCKO BCKO DOL 19 18 17 1 0 DOR MSB LSB 20bits NIPPON PRECISION CIRCUITS—32 SM5846AP High-speed sampling: 256fs clock, 24-bit data output, 4fs output data rate 1 frame (1/4fs) 1 2 13 14 15 16 17 18 25 30 32 fCK/2 (128fs) WCKO BCKO DOL 23 22 21 0 DOR MSB LSB 24bits High-speed sampling: 256fs clock, 20-bit data output, 4fs output data rate 1 frame (1/4fs) 1 2 13 14 15 16 17 18 19 20 21 30 32 fCK/2 (128fs) WCKO BCKO DOL 19 18 17 0 DOR MSB LSB 20bits NIPPON PRECISION CIRCUITS—33 SM5846AP Microprocessor Interface Microprocessor interface pins When MDS is LOW, the SM5846AP is controlled by internal flags set by serial data transferred over the microprocessor interface comprising MDLE, MDCK and MDT. Pin name MDLE MDCK Function Microprocessor data latch enable input Microprocessor data transfer clock input Pin name MDT Serial data input Function Internal control flag serial data on MDT is input into an internal shift register on the rising edge of MDCK. After 8-bit data has been input, the data in the shift register is stored in one of four internal flag registers on the rising edge of MDLE latch enable. The address of the flag register is derived by decoding bits 1 to 3 of the 8-bit data. Microprocessor interface 8bit SIPO Shift Register MDT MDCK D C Q 8bit Register D C Q C D Q 8bit Register D C Q 8bit Register D C Q 8bit Register Decoder MDLE D-ATT Attenation Mode flag 1 Mode flag 2 Mode flag 3 Microprocessor interface data input timing MDCK and MDLE can also follow the dotted lines above MDLE MDCK MDT bit1 MSB bit2 bit3 bit4 bit5 bit6 bit7 bit8 LSB NIPPON PRECISION CIRCUITS—34 SM5846AP Serial data format Register D-ATT attenuation Mode flag 1 Mode flag 2 Mode flag 3 Bit 1 0 1 1 1 Bit 2 a1 0 1 1 Bit 3 a2 SYNC MUTE ASEL1 Bit 4 a3 TEST1 = 0 DITH ASEL2 Bit 5 a4 HS OBS 1 Bit 6 a5 FSEL1 IBS1 TEST2 = 0 Bit 7 a6 FSEL2 IBS2 1 Bit 8 a7 DEEM 1 0 Address information is displayed in double-line cells of the table. Test bits (mode flag 1 bit 4 and mode flag 3 bit 6) should be set to 0. System Reset When a reset is necessary The device must be reset under the following conditions. s s A 0.01 µF external capacitor is recommended. However, the time constant can be lengthened if longer time is required for the XTI and LRCI clocks to stabilize after power-ON. The external capacitor discharges through the internal pull-up resistor at power-OFF as this is the only possible discharge path. This could cause reset failure if power is reapplied while the external capacitor is discharging. Therefore, a diode should be connected between RST and VDD to quickly discharge the capacitor and ensure correct power-ON reset operation. External power-ON reset circuit When power is first applied When the LRCI clock or system clock stop Reset input conditions The RST input is active LOW. At power-ON reset, RST must go LOW and then go HIGH after the XTI and LRCI clocks stabilize (reset release). Reset timing The internal arithmetic registers and output sequence are initialized on the rising edge of the LRCI clock after reset release. The internal control flags and DATT attenuation register are initialized after RST goes LOW. Outputs DOL and DOR are tied LOW while RST is LOW. Power-ON reset using a capacitor The RST input configuration is a Schmitt-trigger input with a pull-up resistor, which means that a simple power-ON reset circuit can be made by connecting a capacitor between RST and VSS as shown below. ‘ Discharge for Diode Internal Pull-up Register RST Schmitt Buffer External Capacitor C Internal Pull-up Register RST Schmitt Buffer External Capacitor C NIPPON PRECISION CIRCUITS—35 SM5846AP Internal control flag/D-ATT attenuator Register D-ATT attenuation Mode flag 1 Mode flag 2 Mode flag 3 Bit 1 0 1 1 1 Bit 2 a1 = 0 0 1 1 Bit 3 a2 = 0 SYNC = 1 MUTE = 1 ASEL1 = 1 register initial values Bit 4 a3 = 0 TEST1 = 0 DITH = 1 ASEL2 = 1 Bit 5 a4 = 0 HS = 1 OBS = 0 1 Bit 6 a5 = 0 FSEL1 = 1 IBS1 = 1 TEST2 = 1 Bit 7 a6 = 0 FSEL2 = 1 IBS2 = 0 1 Bit 8 a7 = 0 DEEM = 0 1 0 Audio ICs When external muting is required The SM5846AP has a relatively long group delay time because multi-stage filters are employed to achieve the desired filter characteristics. Under the following conditions, undesirable noise output can occur during the group delay time period. In this case, it may be necessary to use external muting. s Test Precautions The following conditions should be maintained for normal operation. s s s s s s s When power is first applied. The state of internal registers may be undefined during power-ON. When switching the operating mode. When switching the operating mode using HS, ASEL1 and ASEL2, the internal register assignments may be changed. If the LRCI and/or XTI clock stop. If a disturbance occurs during an input data cycle, normal filter output may not be achieved. When switching deemphasis ON/OFF. Switching the deemphasis filter parameters may cause switching noise output. When switching the sampling frequency (clock frequency). When switching between input/output data formats (including LRCI clock polarity switching). s s MDS and DITH inputs should not be simultaneously LOW. TEST1 (bit 4 of mode flag 1 register) should not be set to 1. TEST2 (bit 4 of mode flag 3 register) should be set to 0 after system reset (including power-ON). Mode flag 3 register bit 5 and/or bit 7 should not be set to 0. Note that switching MDS is inhibited during system operation. NIPPON PRECISION CIRCUITS INC. reserves the right to make changes to the products described in this data sheet in order to improve the design or performance and to supply the best possible products. Nippon Precision Circuits Inc. assumes no responsibility for the use of any circuits shown in this data sheet, conveys no license under any patent or other rights, and makes no claim that the circuits are free from patent infringement. Applications for any devices shown in this data sheet are for illustration only and Nippon Precision Circuits Inc. makes no claim or warranty that such applications will be suitable for the use specified without further testing or modification. The products described in this data sheet are not intended to use for the apparatus which influence human lives due to the failure or malfunction of the products. Customers are requested to comply with applicable laws and regulations in effect now and hereinafter, including compliance with export controls on the distribution or dissemination of the products. Customers shall not export, directly or indirectly, any products without first obtaining required licenses and approvals from appropriate government agencies. NIPPON PRECISION CIRCUITS INC. 4-3, Fukuzumi 2 chome Koto-ku, Tokyo 135-8430, Japan Telephone: 03-3642-6661 Facsimile: 03-3642-6698 NC9616BE 1998.01 NIPPON PRECISION CIRCUITS INC. NIPPON PRECISION CIRCUITS—36