SM8212

SM8212B NIPPON PRECISION CIRCUITS INC. POCSAG Decoder For Multiframe Pagers - BS2 (RF DC-level adjustment signal) before/during reception selectable adjustment timing - 1-bit and 2-bit burst error auto-correction function - 25 to 75% duty factor signal coverage - 8 rate error detection condition settings - 76.8 kHz system clock (crystal oscillator) - 76.8 or 38.4 kHz clock output pin - Built-in oscillator capacitor and feedback resistor - 2.0 to 3.5 V operating supply voltage - Molybdenum-gate CMOS process realizes low power dissipation - 16-pin SSOP OVERVIEW The SM8212B is a POCSAG-standard (Post Office Code Standardization Advisory Group) signal processor LSI, which conforms to CCIR recommendation 584 concerning standard international wireless calling codes. The SM8212B supports call messages in either tone, numerical or character outputs at signal speeds of 512, 1200 or 2400 bps. The signal input stage features a built-in filter. Each of the addresses (max. 8) can be assigned to any frame, which also makes the device configurable for many additional services. Each address can be independently set ON/OFF. Furthermore, built-in buffer memory means decoded information can be fetched in sync with the microcontroller clock, thereby reducing the microcontroller CPU time required. Intermittent-duty method (battery saving (BS) method) control signals, compatible with PLL operation, and Molybdenum-gate CMOS structure makes possible the construction of low-voltage operation, low power dissipation systems. The SM8212B is available in 16-pin SSOPs. PINOUTS (16-pin SSOP) BS1 BS2 BS3 SIGNAL XVSS XT XTN VSS 1 16 VDD ATTN SDI SDO SCK AREA RSTN CLKO 8212BM 8 9 FEATURES - Conforms to POCSAG standard for pagers - 512, 1200 or 2400 bps signal speed - Multiframe compatible (each address individually controllable) - 8 addresses × 4 sub-address (total of 32 addresses) control - Built-in buffer memory - Supports tone, numeric or character call messages - Built-in input signal filter, with filter ON/OFF and 4 selectable filter characteristics - PLL-compatible battery saving method (BS1, BS2, BS3 outputs) - BS1 (RF control main output signal) 61-step setup time setting - BS3 (PLL setup signal) 61-step setup time setting PACKAGE DIMENSIONS 16-pin SSOP (SM8212BM) (Unit: mm) 4.4 0.2 6.2 0.3 0.6TYP 6.8 0.3 0.15 - 0.05 + 0.10 0.05 0.05 1.5 0.1 0.36 0.1 0.8 0 10 0.4 0.2 NIPPON PRECISION CIRCUITS-1 SM8212B BLOCK DIAGRAM VDD BS1 Timing Control Buffer Register Flag Register (Ring) Buffer Register ATTN BS2 SDI SDO SCK BS3 Address Register Receive Data Register SIGNAL Digital PLL Error Correction Timer Data Comparator AREA Preamble Pattern Sync Code Idle Code XVSS XT Main Control Circuit RSTN Each Switch and Register Clock Control Each Working Block CLKO XTN VSS NIPPON PRECISION CIRCUITS-2 SM8212B PIN DESCRIPTION Pin number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Pin name BS1 BS2 BS3 SIGNAL XVSS XT XTN VSS CLKO RSTN AREA SCK SDO SDI ATTN VDD i/o o o o i i o o i o i o i o Description RF control main output signal RF DC-level adjustment signal PLL setup signal NRZ signal input pin Crystal oscillator ground. Capacitor connected between XVSS and VDD Oscillator input pin Oscillator output pin Ground 76.8 or 38.4 kHz clock output Hardware clear (reset) Sync code detection output (HIGH for minimum 1 sec. on detection) CPU-to-decoder data transfer sync clock Status and received data output to CPU Data input from CPU (including ID data) Interrupt detect signal output pin (Ready for data transmission when LOW) Supply voltage i = Input, o = Output SM8212B Paging Receiver Block Diagram RF Waveform Recovery POCSAG Decoder SM8212 Alert Melody IC ID ROM SP PLL Circuit CPU Unit Supply Unit D/D Converter LCD Driver LCD NIPPON PRECISION CIRCUITS-3 SM8212B SPECIFICATIONS Absolute Maximum Ratings (VSS=0V) Unit V V °C mW °C sec. Parameter Supply voltage range Input voltage range Storage temperature range Power dissipation Soldering temperature Soldering time Symbol VDD VIN TSTG PW TSLD Condition Rating -0.3 to 7.0 VSS-0.3 to VDD+0.3 -40 to 125 250 255 10 tSLD Recommended Operating Conditions (VSS=0V) Rating Parameter Supply voltage Operating temperature Symbol VDD TOPR Condition MIN 2.0 -20 TYP MAX 3.5 70 Unit V °C DC Characteristics (Recommended operating conditions unless otherwise noted) Rating Parameter Operating current consumption (IDLE mode) Standby supply current Input voltage Output current Output current VDD All input pins All outputs except XTN All outputs except XTN IDD2 VIH VIL IOH IOL IOH IOL VOH=2.6V, VDD=3.0V VOL=0.4V, VDD=3.0V VOH=1.6V, VDD=2.0V VOL=0.4V, VDD=2.0V 0.6 1.0 0.3 0.7 1.4 2.2 0.7 1.5 mA Pin VDD Symbol IDD1 Condition VDD=3.0V (Note1) VDD=2.0V (Note 1) VDD=3.0V (Note 2) VDD=2.0V (Note 2) 0.8*VDD 0.2*VDD mA MIN TYP 3.0 2.0 2.0 1.5 MAX 6.0 4.0 4.0 3.0 V µA Unit µA (Note 1) When killed CLKO output (Note 2) Oscillator circuit is working The consumption current is slightly higher when RSTN is going LOW. NIPPON PRECISION CIRCUITS-4 SM8212B AC Characteristics (Recommended operating conditions unless otherwise noted) Rating Parameter XT clock frequency XT clock duty cycle SCK clock pulsewidth SCK clock interval (except WRITE mode) SCK clock interval (WRITE mode) SDI data setup time SDI data hold time SDO data setup time SDO data hold time ATTN signal setup time ATTN signal hold time CLKO clock rise time CLKO clock fall time CLKO clock delay time RSTN pulsewidth Synbol fCYXT DXT tPWSC tCYSC tCYSC tSSDI tHSDI tSSDO tHSDO tSATT tHATT tRCLK tFCLK DCLKO tPWRS 1 0 1 500 500 1 MIN -250ppm 25 2 5 5 5 5 1 1 3 0 TYP 76.8 MAX +250ppm 75 150 1900 830 415 830 Unit kHz % µs µs µs µs µs µs µs µs µs µs µs ns ns µs ms No load No load 512bps 1200bps 2400bps Condition tHATT ATTN tPWSC SCK 1 2 tCYSC 3 32 1/ 2*VDD tSSDI SDI INPUT DATA 1 tHSDI INPUT DATA 2 INPUT DATA 3 INPUT DATA 32 Parameter/address set timing tHATT ATTN START command : 66 bit time max Others : 2 bit time max tPWSC SCK 1 2 8 1/ 2*VDD tSSDI SDI tHSDI Decoder Setting1 Decoder Setting 2 Decoder Setting 8 tCYSC Decoder Mode Current Mode Auxiliary operating mode set timing NIPPON PRECISION CIRCUITS-5 Next Mode SM8212B ATTN tPWSC SCK 1 2 8 9 16 1/ 2*VDD tSSDI SDI tHSDI READ COMMAND 2 READ COMMAND 8 READ COMMAND 9 READ COMMAND 16 READ COMMAND 1 tCYSC SDO Don't Care 1 Don't Care 2 Don't Care 8 tHSDO STATUS DATA 1 STATUS DATA 8 tSSDO Status data read timing ATTN tHATT tSATT tPWSC 1 2 tCYSC 3 32 1/ 2*VDD SCK SDI tSSDO tHSDO SDO OUTPUT DATA 1 OUTPUT DATA 2 OUTPUT DATA 3 OUTPUT DATA 32 Received data transfer timing α (XT) (76.8kHz ) β 0.7*VDD 1/ 2*VDD DCLKO DXT = α α+β 0.3*VDD 0.7*VDD 1/ 2*VDD CLKO (76.8kHz Mode) tFCLK tRCLK 0.3*VDD 0.7*VDD CLKO (38.4kHz Mode) 1/ 2*VDD tFCLK CLKO clock output timing tRCLK 0.3*VDD NIPPON PRECISION CIRCUITS-6 SM8212B FUNCTIONAL DESCRIPTION Unless otherwise specified, values in diagrams without parentheses are for 512 bps, in ( ) are for 1200 bps, and in [ ] are for 2400 bps. “M” represents the value of PL5 (MSB) to PL0 (LSB), and “N” represents the value of RF5 (MSB) to RF0 (LSB). 1. Receive Format The receive format conforms to CCIR RPC No. 1 (POCSAG). Preamble Continuous 575-bit "1, 0" bit pattern Sync Code 19 20 Address bits Function bits 21 22 31 1 1st Batch Sync Code 2nd Batch 12 32 Even-parity bit 32 Address signal Message signal 0 Check bits Sync Code Word 1 Message bits Check bits Even-parity bit 1 Code Word Frame No. 7 SC 0 1 2 3 4 5 6 7 SC 0 1 Frame (= 2 Code Words) Sync Code Part Frame Part 1 Batch Figure 1. Receive signal format Sync Code Part (1) Sync signal (SC) The sync signal is a continuous code word in the received signal, used for word synchronization. It comprises 31 bits in an M-series bit pattern plus one even-parity bit, making a 32-bit signal. The sync code word pattern is shown in table 1. Table 1. Sync code format Bit number 1 2 3 4 5 6 7 8 Bit value 0 1 1 1 1 1 0 0 Bit number 9 10 11 12 13 14 15 16 Bit value 1 1 0 1 0 0 1 0 Bit number 17 18 19 20 21 22 23 24 Bit value 0 0 0 1 0 1 0 1 Bit number 25 26 27 28 29 30 31 32 Bit value 1 1 0 1 1 0 0 0 NIPPON PRECISION CIRCUITS-7 SM8212B (2) Code words (address and message signals) Each code word comprises 32 bits as shown in table 2. Table 2. Code word format Code word Bit number 1 (MSB) 2 to 19 20 to 21 Function bits 20 21 Function Address Signal 0 0 Address bits 0 1 1 Message Signal 1 0 1 0 1 A call B call C call D call Check bits Even-parity bit Check bits Even-parity bit 22 to 31 32 (LSB) Message bits 1. The MSB is the address/message code word control bit. It is 0 for an address signal, and 1 for a message signal. 2. Bits 2 to 21 contain the address or message information. 3. Bits 22 to 31 are BCH(31,21) format generated check bits, where BCH(n,k) = BCH(word length, number of information bits). 4. The LSB is an even-parity bit for bits 1 to 31. (3) Call number to call sign conversion This conversion expands a 7-digit decimal call number into a 21-bit binary call sign, as shown in figure 2. After expansion, the high-order 18 bits are assigned to bits 2 to 19 (address signal), and the low-order 3 bits are the user-defined frame identification pattern, which is stored in ID-ROM. The two function bits define which of four call functions is active. 7-digit decimal call signal (gap code) (8 to 2000000) 1 2 3 4 5 6 7 MSB 21-bit binary conversion 2 3 4 5 6 7 8 LSB 1 9 10 11 12 13 14 15 16 17 18 19 20 21 Frame identification pattern 19 20 21 22 31 32 1 2 Call sign Bits 2 to 19 (18 bits) 0 Bits 22 to 31 (10 bits) Function bits BCH(31, 21) generated check bits P Even-parity bit (for bits 1 to 31) Flag : "0" = Adderss signal Figure 2. Call number to call sign conversion NIPPON PRECISION CIRCUITS-8 SM8212B (4) Idle signal In the POCSAG format, for pager systems that send numeric data, the message information content varies and as a result an idle signal or another address signal is inserted after the message to indicate the end of the message. That is, if no address word or message word exists for a frame within a batch or for a code word within a frame, the idle pattern, shown in table 3, is transmitted in its place. Then during message signal reception, the message ends when the idle signal is detected. The SM8212B, however, supports 2 methods of determining the end of message. Namely, message ends when either an idle signal or another address is received (POCSAG format), or solely by an interrupt signal from the CPU. Table 3. Idle code format Bit number 1 2 3 4 5 6 7 8 Bit value 0 1 1 1 1 0 1 0 Bit number 9 10 11 12 13 14 15 16 Bit value 1 0 0 0 1 0 0 1 Bit number 17 18 19 20 21 22 23 24 Bit value 1 1 0 0 0 0 0 1 Bit number 25 26 27 28 29 30 31 32 Bit value 1 0 0 1 0 1 1 1 (5) Receive signal duty factor During preamble detection, the preamble pattern (1,0) is recognized at duty factors from 25% (min) to 75% (max) of the (1,0) preamble cycle. (6) Error Correction and Detection The SM8212B performs error correction (or detection) on each code word as described in table 4. Note that there are 8 selectable error correction conditions for the preamble pattern. Table 4. Error correction Item Preamble Pattern Detection Synchronization Code word Detection Self Address Code word Detection Message Code word Description Selectable 1 to 8 rate errors in 6 to 544 bits 2 random errors in 32 bits 2 random errors in 32 bits 1-bit and 2-bit burst errors in 31 bits An error is deemed to have occurred when 2 or more signal edges occur within 1-bit unit time, and a rate error is deemed to have occurred when the number of errors exceeds the counter value. Refer to the “Preamble Mode” section for a discussion of the error counter. NIPPON PRECISION CIRCUITS-9 SM8212B 2. Battery Saving (BS1, BS2, BS3) The SM8212B controls the intermittent-duty operation of the RF stage, which reduces battery consumption, and outputs three control signals (BS1, BS2, BS3). The function each signal controls in each mode is described below. BS1 (RF-control main output signal) The RF stage is active when BS1 is HIGH. The rising-edge setup time for receive timing is set by flags RF0 to RF5 (61 steps). The maximum setup time is 25.417 ms at 2400 bps, 50.833 ms at 1200 bps and 119.141 ms at 512 bps. Note that 3E and 3F are invalid settings for BS1. BS2 (RF DC-level adjustment signal) BS2 is used to control the discharge of the receive signal DC-cut capacitor. The function of BS2 is determined by flag BS2, as described below. -When flag “BS2 option” is 0, pin BS2 goes HIGH together with BS1 and then goes LOW again after the BS1 setup time in idle mode. In preamble and lock (during address/message reception) mode, it keeps LOW. -When flag “BS2 option” is 1, pin BS2 goes HIGH during lock mode sync code receive timing and idle mode signal receive timing. In preamble mode, it keeps LOW. BS3 (PLL setup signal) BS3 is used to control PLL operation when the PLL is used. The rising-edge setup time for receive timing is set by flags PL0 to PL5 (61 steps). The maximum setup time is 25.833 ms at 2400 bps, 51.667 ms at 1200 bps and 121.094 ms at 512 bps. Note that 3F is an invalid setting for BS3. Note also that the setup times should be set such that (BS3 rising-edge setup time) > (BS1 rising-edge setup time). SYN ICW ICW ADD MES MES ICW ADD MES MES MES MES ICW ICW ICW ADD MES SYN MES MES MES MES ICW ICW ADD MES MES MES MES ICW ADD MES 6 ICW ADD 7 ICW Address does not match Self address BS1 BS2 (flag BS2 option = 0) BS2 (flag BS2 option = 1) BS3 1.953*Mms (0.833*Mms) [0.417*Mms] SYN MES MES ICW ICW ICW ICW ADD MES MES MES 1.953*Nms (0.833*Nms) [0.417*Nms] 1.953*Nms (0.833*Nms) [0.417*Nms] 1.953*Mms (0.833*Mms) [0.417*Mms] 5 MES MES 6 MES MES MES 7 MES SYN MES 0 MES 1 MES ICW ADD 2 MES MES 3 MES 4 MES ICW ADD 5 MES MES ICW SYN Receive code BS1 BS2 (flag BS2 option = 0) BS2 (flag BS2 option = 1) BS3 BREAK command 0 1 2 3 4 Self address BREAK detection to reception stop (32 bit max.) Figure 3. BS1, BS2 and BS3 timing (LOCK mode, frame 3) NIPPON PRECISION CIRCUITS-10 MES SYN Receive code 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 SM8212B 3. Operating Modes The SM8212B has four operating modes: Power-ON (Write), Preamble, Idle and Lock modes. (1) Power-ON mode After power is applied, the internal registers should be reset using RSTN. When ATTN goes HIGH, the decoder sends a write request for a decoder set read command and then waits for the microcontroller (decoder set write command timing starts approximately 50 ms after reset, but for safety, wait minimum 900ms when Power-ON mode). The internal operation in write mode takes place at the same timing as for 1200 bps speed mode. Write data is prepared in 32-bit batches of 1 parameter batch and 8 address data batches for a total of 9 batches. The parameter and address set commands are processed in sync with the decoder internal clock (1200 Hz). As a consequence, a gap of 28.4 ms minimum should be left between batches to provide time for processing. Alternatively, data can be written by first using the decoder set read command to confirm whether or not processing is still in progress (BUSY) before writing each batch. If the time gap is 28.4 ms or greater, confirmation (READY) is not required. After parameters and all addresses have been written and after decoder processing, the decoder set start command transfers operation from write mode and starts preamble mode operation. When setting parameters and addresses in write mode, the SCK clock frequency should not be less than 1200 Hz. If this occurs, the SCK counter is reinitialized. This function, however, does make restoring operation easy even if this or another clock is accidentally input. In write mode, after power is applied and after reset initialization, all 9 batches (1 parameter and 8 address batches) should be set. If not all batches are set, subsequent operation may become unstable. RSTN SCK SDI READY 1 ms min READ READ READ START DAT A BUSY READY DAT A SDO BUSY max 900ms max. 1.67ms max. 28.4ms WRITE MODE 129ms max PREAMBLE MODE : 8-bit unit time clock : 8-bit unit time data : 8-bit unit time indeterminate data 129ms max DAT A : 32-bit unit time parameter/address data Refer to the AC Characteristics section for detailed timing specifications. Figure 4. Power-ON (WRITE) mode timing NIPPON PRECISION CIRCUITS-11 SM8212B (2) Preamble mode Preamble mode is a continuous 544-bit long period. If neither a preamble pattern, rate error nor sync code is detected during this period, operation transfers to idle mode. (a) If a preamble pattern is detected, the preamble mode 544-bit long period is recommenced. (b) If the sync code is detected, AREA goes HIGH and operation transfers to lock mode. If an error of 2 bits or less occurs, the detected word is recognized as the sync code. During the preamble mode interval, BS1 and BS3 are held HIGH. BS2 keeps LOW. * A single error occurs when two active edges occur in the received signal on SIGNAL within 1-bit unit time. A rate error occurs when the number of errors in the error counter equals the error threshold set by flags ER0 to ER2. The error counter is reset when a preamble pattern is detected. Error counter (e. g. set value ≥ 3) Preamble Signal Error bit 0111220 t Preamble detected t t t t t t ..1010111010101010.. 1010101 Preamble and error count starts Preamble detected and count reset Preamble count restarts Count reset to 0 Preamble count starts Counting t : 1-bit time Figure 5. PREAMBLE mode internal operation (3) Idle mode In idle mode, a check is made for the presence of a preamble signal when the RF intermittent-duty control signals (BS1, BS2, BS3) for battery saving are active. If a preamble pattern is detected, operation immediately transfers to preamble mode. If a preamble pattern is not detected, intermittent-duty operation continues. A preamble pattern is detected when either a 101010 or 010101 6-bit pattern is detected. Since there is a reasonable probability that this simple pattern can occur during a BS1 valid communicated signal (data, not preamble), this 6-bit pattern makes returning to preamble mode easier. This is useful for cases where weak electric fields, noise or other temporary interference cause device operation to transfer to idle mode. Further, the idle mode receive timing immediately after transfer from lock mode is the same as the original sync code receive timing. As a result, if a sync code is detected, operation returns to lock mode. 62.5ms (26.7ms) [13.4ms] Receive timing 1.953*Nms (0.833*Nms) [0.417*Nms] 1.953*Mms (0.833*Mms) [0.417*Mms] 1062.5ms (453.3ms) [226.7ms] BS2 (flag BS2 option = 0) BS2 (flag BS2 option = 1) BS3 Figure 6. IDLE mode timing NIPPON PRECISION CIRCUITS-12 SM8212B (4) Lock mode If the sync code is detected during the preamble period, device operation transfers to lock mode and BS1 goes LOW. BS1 then goes HIGH again under frame timing, where the frame number is set by flags FF0 to FF2, and the 32 addresses are compared with ID-ROM (If the frame number is 0, BS1 stays HIGH). If errors of 2 bits or less occur, the address is still recognized. Since there are two code words per frame, this check is done twice. When one of the 32 addresses does not match, BS1 goes LOW and the device waits for the next frame or sync code receive timing. If the sync code is still not detected after two consecutive attempts, device operation transfers to idle mode, except during message reception where operation stays in lock mode. If the sync code is not detected on the second attempt, but instead a pattern forming a preamble is detected, device operation transfers to preamble mode and not idle mode (preamble mode is more advantageous for sync code detection). When one of the 32 addresses does match, ATTN goes LOW and the address information (see “Data/Flags” section) is transmitted to the CPU on SDO in sync with the SCK clock. When the address information is confirmed to be a message, BS1 is held HIGH and the message is received. The received message is stored in a buffer as 32-bit error-corrected information (see “Data/Flags” section), then ATTN goes LOW and the data is transmitted to the CPU on SDO in sync with the SCK clock. When the address and message is received, ATTN should be held LOW while the data is output on SDO. When an incoming message spans two or more batches, additional sync code detection occurs during sync code receive timing. Message reception can be selected to end when either an address code or idle code is detected, or when interrupted using the decoder set command BREAK input. This selection is made when setting parameters that will not cause the message to terminate. If the BREAK mode is selected, even if an address other than the self address (MSB = 0) is received during message reception, reception continues without interruption and address data is sent to the microcontroller using the same data handling as for a message. In this case, reception can only be interrupted by a BREAK input signal from the microcontroller. In either of the above cases, message reception ends if an end-of-message signal is sent. (Except MSB=0 but self address, no BREAK input) When message reception ends, BS1 goes LOW and the device waits for either the address detect timing of the next frame or the sync code receive timing. When sending data from the decoder to the microcontroller, the SCK clock frequency should not be less than 512, (1200), [2400] Hz. If this occurs, the SCK counter is reinitialized. This function, however, does make restoring operation easy even if this or another clock is accidentally input. POWER-ON Mode A H PREAMBLE Mode C B G D E F A: After reset, parameters/addresses are set and start command is issued. B: Rate error or, within a fixed period, preamble pattern/sync code not detected. C: Preamble pattern detected. D: Sync code detected 1 cycle immediately after transfer from lock mode. E: Sync code not detected on 2 consecutive attempts F: Same as E, but preamble detected on the second attempt. G: Sync code detected. H: Parameters/addresses are set and start command is issued from preamble/idle/lock mode. IDLE Mode LOCK Mode Figure 7. Operating mode transition diagram NIPPON PRECISION CIRCUITS-13 SM8212B 4. Address/Parameter Data Transmission (CPU to SM8212B) After device reset initialization, the address and parameter data is transmitted from the CPU in 32-bit batches, 1 parameter batch and 8 address batches for a total of 9 batches (288 bits), on SDI in sync with the falling edge of the SCK clock (see “Power-ON Mode” section). The SM8212B supports 8 independent addresses (identified as A, B, C, D, E, F, G and H). Also, each address can be assigned a frame number to cover all kinds of group calls or subsidiary services. Any of the 8 addresses can be individually disabled. In this case, the address can be disabled using the “ADDRESS ENABLE” flag when setting the addresses. The address data for each of the 8 addresses comprises an 18-bit address plus two function bits used to select one of four sub-addresses. Then, one MSB bit (0 for address signals), ten BCH(31,21) format generated check bits and an even-parity bit are added to form 32-bit code words representing the address information which is then stored in RAM. This address information is then compared with the received data to determine correct addressing. Even if the number of addresses used is less than 8, all addresses should be set immediately after power is applied and immediately after reset. If not all addresses are set, subsequent operation may become unstable. Each address is 18 bits long and should be input MSB first. Refer to the “AC Characteristics” section for SCK and data specifications, and the “Data/Flags” section for data and flag functions. When setting parameters and addresses in write mode, the SCK clock frequency should not be less than 1200 Hz. If this occurs, the SCK counter is reinitialized. This function, however, does make restoring operation easy even if this or another clock is accidentally input. ATTN SCK WRITE READ READ START SDI SDO DAT A BUSY READY DAT A 1.67ms max BUSY WRITE MODE 2bit time max max 28.4ms 129ms max PREAMBLE MODE 129ms max : 8-bit unit time clock : 8-bit unit time data : 8-bit unit time indeterminate data DAT A : 32-bit unit time parameter/address data Refer to the AC Characteristics section for detailed timing specifications. Figure 8. Address/parameter transmit timing NIPPON PRECISION CIRCUITS-14 SM8212B 5. Received Data Transmission (SM8212B to CPU) In lock mode, if the receive data for the frame is recognized as one of the 32 addresses with 2 bit errors or less, then the data is temporarily stored in the transmit buffer and then error correction and other processing takes place. After processing, ATTN goes LOW to inform the CPU that transmit ready data is available. The SM8212B switches the data internally and then outputs 32-bit data, shown in table 6, on SDO in sync with the falling edge of the SCK clock. The CPU can then read the data on either the SCK rising edge or the falling edge. The message bits (1 to 20), which are the 13th to 32nd bits of the detected address data, comprises 18 address information bits and 2 function bits. When the 32-bit transmission ends, ATTN goes HIGH to indicate that all necessary information has been transmitted. When an address is detected, the next 32-bit data code word is received. The BCH(31,21) format error check bits are checked and if a 1-bit or two consecutive bit errors occur, they are corrected. Two random bit errors, or three or more bit errors are not corrected. If the corrected data MSB is 1, the data is recognized as a message, data reception continues and the corrected message data and error check flags are sent to the CPU as 32bit data, shown in table 7, with the same data handling as an address. In this case also, ATTN goes LOW after processing to inform the CPU that transmit ready data is available. The time from when ATTN goes LOW until the CPU sends the SCK should be the same as shown in figure 9. Also, when the message continues, the normal SCK clock speed becomes faster than the receive signal bit rate and as a result there is a limit to the transmitted information capacity. As ATTN is used as the transmit ready data available signal output, it can be used as the CPU interrupt signal to receive data with the timing shown in figure 9. Conversely, when the decoder takes ATTN LOW to indicate transmit ready data is available, the microcontroller operates under normal starting conditions (highspeed clock operation), and 32-bit clock is input on SCK. After data is read in and until ATTN goes LOW for the next transmit ready data signal, the series processing should be such that it takes less than {32x(bit rate)} time. When the MSB is 0 and data is recognized as an idle signal or idle code, data reception and data transfer to the CPU stops after the end-of-message is output for addresses not matching the self address. However, when CPU BREAK input interrupt end-ofmessage method is selected (see “Flag Setting” section), data is treated as a message and reception continues even if the MSB is 0. When sending data from the decoder to the microcontroller, the SCK clock frequency should not be less than 512, (1200), [2400] Hz. If this occurs, the SCK counter is reinitialized. This function, however, does make restoring operation easy even if this or another clock is accidentally input. 32 bit time 0ms min ATTN 0ms min SCK SDO DATA DATA : 8-bit × 4-byte = 32-bit unit time clock DATA : 8-bit × 4-byte = 32-bit unit time data Refer to the AC Characteristics section for detailed timing specifications. Figure 9. Received data transmit timing NIPPON PRECISION CIRCUITS-15 SM8212B 6. Decoder Set Command Transfer (CPU to SM8212B) In the SM8212B, the Break, Back-up, Write, BS-test, Start and End auxiliary modes are controlled control signals from the CPU. These modes are set by data written on SDI in sync with the SCK clock (see “Data/Flags” section). When sending data from the decoder to the microcontroller, the SCK clock frequency should not be less than (1) Break This is the interrupt command to stop reception and data transfer. When the Break command is detected, the received code word ends and reception stops, then the device waits for self frame address detection or sync code detection timing. Reception may continue for up to 32-bit unit time after the Break command is received (or 34-bit time after the Break command is sent). Even though message reception may continue for a short time when the Break command is sent, sync code detection does not take place and accordingly the received data may be deemed to have many errors. (2) Back-up (Power save control) This is the decoder OFF mode command. This command stops all internal operation except the oscillator, and thus is used to control current consumption. CLKO output is stopped. Note that in back-up mode, the input/output pins do not become high impedance. Back-up mode is released and operation restarts when the decoder set start command is issued. All parameter and (3) Write This is the parameter and address write command. This operation mode can also be used to modify parameters and addresses. Write mode can be activated from BS-test mode, and also approximately 50 ms after reset, but for safety, wait minimum 900ms when Power-ON reset. Parameters and addresses can be changed by first issuing a decoder set command to enter write mode and then writing new parameters and addresses. Note that in write mode, all internal operation takes place with the same timing as for 1200 bps speed mode. BS1, BS2 andBS3 are keep LOW. Each of the addresses can be turned ON/OFF, according to flag settings in the data written. Using this feature for a specific address in a pager allows the service provider, by prior agreement, to prohibit improper use of the pager delivery service (excluding delivery testing, stopping subsidiary services and similar functions). In the SM8212B, data writes from the microcontroller have priority, even if a received information transmit ready signal (ATTN = LOW) is present (forced write). When reception from the decoder RF stage has priority, operation switches to write mode after the end-of-message is confirmed by monitoring the internal operation using the read command. Then the parameter set commands and address set commands are written. After writing, write mode is released using the decoder set start command, and operation starts from preamble mode. address information is retained during back-up, so operation starts directly from preamble mode. Note that only the decoder set start command is accepted during back-up mode. Note that issuing the BACK-UP command is prohibited in the WRITE mode. Also, when CPU BREAK input interrupt end-of-message method only is selected, message reception continues even if an address code or an idle code is present, as long as the Break command is not issued. The time required from when the Break command is issued until received data is output can be approximately 2 to 3 code words at internal sync speed. During this interval, 32 clock cycles are sent to the decoder while ATTN is LOW, and processing should be performed just as for normal operation. If no processing is performed, subsequent operation may become unstable. 1200 Hz. If this occurs, the SCK counter is reinitialized. This function, however, does make restoring operation easy even if this or another clock is accidentally input. Note that read mode function is described in the “Decoder Internal Status Transfer” section. NIPPON PRECISION CIRCUITS-16 SM8212B (4) BS-test This mode is used to test the RF stage operation, and is only available from write mode. BS1 and BS3 held HIGH for RF stage testing. After testing, BS-test mode is released using the decoder (5) Start This command is used to return to normal operation from back-up, write and BS-test modes. Operation always Note the following points when setting commands: Immediately after ATTN goes LOW Commands send 8 SCK clock cycles to the decoder and the received data is sent using 32 clock cycles immediately after ATTN goes LOW. However, apart from the 8 clock cycles needed for the command, 32 clock cycles are needed to release ATTN. After being transferred the command, even if ATTN keeps LOW, transmitted reception data is unstable. When ATTN is HIGH These commands should use when ATTN HIGH timing only. After command is transferred and until ATTN goes LOW for the next transmit ready data signal, the series processing should be such that it takes less than {32x(bit rate)} time. restarts from preamble mode. set start command, and operation starts from preamble mode. Note that issuing the BACK-UP command is prohibited in the BS-test mode. When ATTN goes HIGH (excluding write mode), SCK is examined to determine if the signal is a break, back-up, write or read command. During message reception, ATTN is temporarily held HIGH if a com- mand is issued to set ATTN LOW. This delay ensures that the data from the decoder is not misinterpreted. And in this case, even if ATTN keeps LOW, transmitted receiving data is unstable. SCK Decoder Setting Data SDI Decoder Mode Current Mode Next Mode START command : 66 bit time max Others : 2 bit time max : 8-bit × 1-byte = 8-bit unit time clock : 8-bit × 1-byte = 8-bit unit time data Refer to the AC Characteristics section for detailed timing specifications. Figure 10. Auxiliary operating mode timing NIPPON PRECISION CIRCUITS-17 SM8212B 7. Decoder Internal Status Transfer (SM8212B to CPU) In the SM8212B, the internal decoder status and parameter/address end-of-processing confirmation, is transmitted to the CPU. The microcontroller uses this status information only when needed. This is a 2-byte (16 bits) command where the first byte is a decoder set read command and the second byte is the decoder internal status that is sent to the microcontroller in sync with the SCK clock. The microcontroller can use this function when not receiving data from the decoder (when ATTN is HIGH timing only). Note the following points when setting the read command: When ATTN is HIGH Read command should use when ATTN HIGH timing only. After data is transferred and until ATTN goes LOW for the next transmit ready data signal, the series processing should be such that it takes less than {32x(bit rate)} time. When ATTN goes HIGH (excluding write mode), SCK is examined to determine if the signal is a break, back-up, write or read command. During message reception, ATTN is temporarily held HIGH if a command is issued to set ATTN LOW. This delay ensures that the data from the decoder is not mis-interpreted. And in this case, even if ATTN keeps LOW, transmitted receiving data is unstable. ATTN SCK READ SDI STATUS DATA SDO : 8-bit × 2-byte = 16-bit unit time clock Indicates indeterminate data output. When the CPU interprets the internal status, these portions can be ignored (discarded). : 8-bit × 1-byte = 8-bit unit time data : 8-bit × 1-byte = 8-bit unit time indeterminate data Refer to the AC Characteristics section for detailed timing specifications. Figure 11. Internal status transfer timing NIPPON PRECISION CIRCUITS-18 SM8212B 8. Miscellaneous Interface Pins (1) SIGNAL NRZ-format signal input pin, with built-in noise canceller filter. Current pager systems operate at 3 baud rates (512, 1200 and 2400 bps). In conventional systems, the RF stage LPF time constants are changed in response to the baud rate in order to get the best possible reception. However, this requires changing the external components which results in increased product operating costs. The SM8212B, however, performs digital processing on the input signal which allows the 3 baud rates to be covered without the need to substitute RF stage LPF components. The side effect of this digital filter processing is a small probability of rate errors occurring. Digital processing can be turned ON/OFF using flags. When turned ON, there are 4 filter constant settings that can be selected to obtain the best possible reception conditions in a flexible manner (see “Parameter Flags” section). (2) XT, XTN Crystal oscillator element connection pins. The SM8212B operates at 76.8 kHz system clock speed, and this clock can be provided simply by connecting a crystal element between XT and XTN. The oscillator amplifier, feedback resistance and oscillator capacitance are all built-in. In this case, XTN should not be used as a clock to drive an external device. Also, a 1000 pF to 0.1 µF capacitor should be connected between XVSS and VDD. (3) CLKO Clock output pin. The clock output can be used as a CPU sleep clock or melody IC (SM1124 series) clock. The output clock frequency, 76.8 or 38.4 kHz, is selected using the decoder parameter set command. (4) RSTN Decoder IC internal initialization reset pin. It also functions as an oscillator start-up booster (current source) immediately after power is applied to speed up oscillator stabilization. (5) AREA This pin goes HIGH for ≥ 1 second when a sync code is detected with 2 or less random bit errors in preamble, lock or idle mode sync code detection timing. During intermittent-duty CPU operation, monitoring this pin is useful for out-of-range signal strength. However, even if a sync code is detected, this pin is not held HIGH for ≥ 1 second if 2 consecutive sync codes could not be detected, or under the following situations in 1200 and 2400 bps modes. When the second of 2 consecutive sync codes could not be detected but a 6-bit preamble is detected and preamble continues. When operation transfers from lock mode to idle mode and then to preamble mode. Note that if operation stays in idle mode after transfer from lock mode, this pin goes HIGH for ≥ 1 second. NIPPON PRECISION CIRCUITS-19 SM8212B Data/Flags 1. Parameter set flags (1) Table 5. Parameter set flags Parameter setting flag 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 0 1 0 0 0 0 0 BS2 OPTION (BS2 option) END OF MESSAGE DETECTION SELECT CLKO FREQUENCY KILL CLKO BIT RATE SET 1 (BRS1) BIT RATE SET 0 (BRS0) SIGNAL POLARITY PL5 PL4 PL3 PL2 PL1 PL0 RF5 RF4 RF3 RF2 RF1 RF0 FILTER ENABLE/ DISABLE FILTER 1 FILTER 0 ERROR 2 (ER 2) ERROR 1 (ER 1) ERROR 0 (ER 0) When the “BS2 option” flag is 0, pre-receive adjustment mode is selected, and BS2 goes HIGH for a period of 1.953xN ms (0.833xN ms) [0.417xN ms] immediately before receive timing during intermittent-duty operation in idle mode. BS2 is held LOW in preamble and lock mode. Note that values without parentheses are for 512 bps, in ( ) are for 1200 bps, and in [ ] are for 2400 bps. “N” represents the value set by RF5 (MSB) to RF0 (LSB). When the “BS2 option” flag is 1, mid-receive adjustment mode is selected, with different timing depending on the mode. In idle mode, BS2 is held HIGH only during intermittent-duty operation receive timing which is a period of 62.5 ms (26.7 ms) [13.4 ms]. In preamble mode, BS2 is held LOW. In lock mode, BS2 is held HIGH during sync code receive timing. The sync code is a POCSAG-format conforming signal comprising 32 bits of 16 “0” and 16 “1” bits to maintain energy balance so that, even for long message reception and fast-changing reception conditions, it can still be detected. Bit 9 End-of-message method select flag. When 0, end of message occurs when either an idle code word or another address is received during message reception, or when a break command is issued from the CPU. When 1, end of message occurs only when a break command is issued from the CPU. So even if another address is received, the data is sent continuously to the CPU with message data handling. Therefore, the signal is considered to be valid even if the service provider sends a message and not enough information is received due to signal noise. Bit 10 CLKO output clock frequency select flag. When 0, 76.8 kHz is selected. When 1, 38.4 kHz is selected. Bit 11 CLKO clock output enable flag. When 0, output is enabled. When 1, output is disabled. If CLKO clock output is not used, it can be useful in preventing unwanted noise generation. Bits 1 to 7 These bits form the parameter set command. Bit 8 This bit selects the output format of the RF DC-level adjustment signal output on BS2. NIPPON PRECISION CIRCUITS-20 SM8212B 2. Parameter set flags (2) Table 5. Parameter set flags Parameter setting flag 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 0 1 0 0 0 0 0 BS2 OPTION (BS2 option) END OF MESSAGE DETECTION SELECT CLKO FREQUENCY KILL CLKO BIT RATE SET 1 (BRS1) BIT RATE SET 0 (BRS0) SIGNAL POLARITY PL5 PL4 PL3 PL2 PL1 PL0 RF5 RF4 RF3 RF2 RF1 RF0 FILTER ENABLE/ DISABLE FILTER 1 FILTER 0 ERROR 2 (ER 2) ERROR 1 (ER 1) ERROR 0 (ER 0) Bit 14 NRZ input signal polarity select flag. When 0, normal logic is selected. When 1, inverse logic is selected. Bits 15 to 20 BS3 (PLL setup signal) setup time set flags. “M” represents the value of PL5 (MSB) to PL0 (LSB) and is used to control the receive timing setup time before BS3 rising edge. The setup time is 1.953xM ms (0.833xM ms) [0.417xM ms]. The valid values are from 2 to 62 (61 steps). Note that 3F HEX is an invalid setting. Bits 21 to 26 BS1 (RF control main output signal) setup time set flags. “N” represents the value of RF5 (MSB) to RF0 (LSB) and is used to control the receive timing setup time before BS3 rising edge. The setup time is 1.953xN ms (0.833xN ms) [0.417xN ms]. The valid values are from 2 to 62 (61 steps). Note that 3E and 3F HEX are invalid settings. Note also that the setup times should be set such that (BS3 rising-edge setup time) > (BS1 rising-edge setup time). Bit 27 NRZ signal input noise canceller filter ON/OFF flag. When 0, filter is OFF. When 1, filter is ON. Bits 28 to 29 These bits set the noise canceller filter on-state (strength) when the filter is turned ON using bit 27. FILTER 1 FILTER 0 0 0 1 1 0 1 0 1 Filter strength Filter strength 1 Filter strength 2 Filter strength 3 Filter strength 4 Filter ON-state strength: 1