54F194LM

54F 74F194 4-Bit Bidirectional Universal Shift Register November 1994 54F 74F194 4-Bit Bidirectional Universal Shift Register General Description The ’F194 is a high-speed 4-bit bidirectional universal shift register As a high-speed multifunctional sequential building block it is useful in a wide variety of applications It may be used in serial-serial shift left shift right serial-parallel parallel-serial and parallel-parallel data register transfers The ’F194 is similar in operation to the ’F195 universal shift register with added features of shift left without external connections and hold (do nothing) modes of operation Features Y Y Y Y Typical shift frequency of 150 MHz Asynchronous master reset Hold (do nothing) mode Fully synchronous serial or parallel data transfers Commercial 74F194PC Military Package Number N16E Package Description 16-Lead (0 300 Wide) Molded Dual-In-Line 16-Lead Ceramic Dual-In-Line 16-Lead (0 150 Wide) Molded Small Outline JEDEC 16-Lead (0 300 Wide) Molded Small Outline EIAJ 16-Lead Cerpack 20-Lead Ceramic Leadless Chip Carrier Type C 54F194DM (Note 2) 74F194SC (Note 1) 74F194SJ (Note 1) 54F194FM (Note 2) 54F194LM (Note 2) J16A M16A M16D W16A E20A Note 1 Devices also available in 13 reel Use suffix e SCX and SJX Note 2 Military grade device with environmental and burn-in processing Use suffix e DMQB FMQB and LMQB Logic Symbols IEEE IEC Connection Diagrams Pin Assignment for DIP SOIC and Flatpak Pin Assignment for LCC TL F 9498 – 1 TL F 9498 – 2 TL F 9498–5 TL F 9498–3 TRI-STATE is a registered trademark of National Semiconductor Corporation C1995 National Semiconductor Corporation TL F 9498 RRD-B30M105 Printed in U S A Unit Loading Fan Out Pin Names S0 S1 P0 – P3 DSR DSL CP MR Q 0 – Q3 54F 74F Description Mode Control Inputs Parallel Data Inputs Serial Data Input (Shift Right) Serial Data Input (Shift Left) Clock Pulse Input (Active Rising Edge) Asynchronous Master Reset Input (Active LOW) Parallel Outputs UL HIGH LOW 10 10 10 10 10 10 10 10 10 10 10 10 50 33 3 Input IIH IIL Output IOH IOL 20 mA b0 6 mA 20 mA b0 6 mA 20 mA b0 6 mA 20 mA b0 6 mA 20 mA b0 6 mA 20 mA b0 6 mA b 1 mA 20 mA Functional Description The ’F194 contains four edge-triggered D flip-flops and the necessary interstage logic to synchronously perform shift right shift left parallel load and hold operations Signals applied to the Select (S0 S1) inputs determine the type of operation as shown in the Mode Select Table Signals on the Select Parallel data (P0 – P3) and Serial data (DSR DSL) inputs can change when the clock is in either state provided only that the recommended setup and hold times with respect to the clock rising edge are observed A LOW signal on Master Reset (MR) overrides all other inputs and forces the outputs LOW Mode Select Table Operating Mode Reset Hold Shift Left Shift Right Parallel Load H (h) e High Voltage Level L (l) e Low Voltage Level pn (qn) e Lower case letters indicate the state of the referenced input (or output) one setup time prior to the LOW-to-HIGH clock transition X e Immaterial Inputs MR L H H H H H H S1 X l h h l l h S0 X l l l h h h DSR X X X X l h X DSL X X l h X X X Pn X X X X X X pn Q0 L q0 q1 q1 L H p0 Outputs Q1 L q1 q2 q2 q0 q0 p1 Q2 L q2 q3 q3 q1 q1 p2 Q3 L q3 L H q2 q2 p3 Logic Diagram TL F 9498 – 4 Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays 2 Absolute Maximum Ratings (Note 1) If Military Aerospace specified devices are required please contact the National Semiconductor Sales Office Distributors for availability and specifications Storage Temperature Ambient Temperature under Bias Junction Temperature under Bias Plastic VCC Pin Potential to Ground Pin b 65 C to a 150 b 55 C to a 125 b 55 C to a 175 b 55 C to a 150 Recommended Operating Conditions Free Air Ambient Temperature Military Commercial Supply Voltage Military Commercial b 55 C to a 125 C 0 C to a 70 C a 4 5V to a 5 5V a 4 5V to a 5 5V C C C C b 0 5V to a 7 0V b 0 5V to a 7 0V Input Voltage (Note 2) b 30 mA to a 5 0 mA Input Current (Note 2) Voltage Applied to Output in HIGH State (with VCC e 0V) b 0 5V to VCC Standard Output b 0 5V to a 5 5V TRI-STATE Output Current Applied to Output in LOW State (Max) twice the rated IOL (mA) Note 1 Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired Functional operation under these conditions is not implied Note 2 Either voltage limit or current limit is sufficient to protect inputs DC Electrical Characteristics Symbol VIH VIL VCD VOH Parameter Min Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage Output LOW Voltage Input HIGH Current Input HIGH Current Breakdown Test Output HIGH Leakage Current Input Leakage Test Output Leakage Circuit Current Input LOW Current Output Short-Circuit Current Power Supply Current b 60 54F 74F Typ Max Units V 08 b1 2 VCC Conditions Recognized as a HIGH Signal Recognized as a LOW Signal 20 V V V Min Min IIN e b18 mA IOH e b1 mA IOH e b1 mA IOH e b1 mA IOL e 20 mA IOL e 20 mA VIN e 2 7V VIN e 7 0V VOUT e VCC IID e 1 9 mA All Other Pins Grounded VIOD e 150 mV All Other Pins Grounded VIN e 0 5V VOUT e 0V 54F 10% VCC 74F 10% VCC 74F 5% VCC 54F 10% VCC 74F 10% VCC 54F 74F 54F 74F 54F 74F 74F 74F 25 25 27 05 05 20 0 50 100 70 250 50 4 75 3 75 b0 6 b 150 VOL IIH IBVI ICEX VID IOD IIL IOS ICC V mA mA mA V mA mA mA mA Min Max Max Max 00 00 Max Max Max 33 46 3 AC Electrical Characteristics 74F Symbol Parameter Min fmax tPLH tPHL tPHL Maximum Shift Frequency Propagation Delay CP to Qn Propagation Delay MR to Qn 105 35 35 45 TA e a 25 C VCC e a 5 0V CL e 50 pF Typ 150 52 55 86 70 70 12 0 Max 54F TA VCC e Mil CL e 50 pF Min 90 30 30 45 85 85 14 5 Max 74F TA VCC e Com CL e 50 pF Min 90 35 35 45 80 80 14 0 Max MHz ns ns Units AC Operating Requirements 74F Symbol Parameter TA e a 25 C VCC e a 5 0V Min ts(H) ts(L) th(H) th(L) ts(H) ts(L) th(H) th(L) tw(H) tw(L) trec Setup Time HIGH or LOW Pn or DSR or DSL to CP Hold Time HIGH or LOW Pn or DSR or DSL to CP Setup Time HIGH or LOW Sn to CP Hold Time HIGH or LOW Sn to CP CP Pulse Width HIGH MR Pulse Width LOW Recovery Time MR to CP 40 40 10 0 10 0 80 0 0 50 50 90 Max 54F TA VCC e Mil Min 60 40 15 10 10 5 80 0 0 55 50 90 Max 74F TA VCC e Com Min 40 40 10 10 11 0 80 0 0 55 50 11 0 ns ns ns Max Units ns ns 4 Ordering Information The device number is used to form part of a simplified purchasing code where the package type and temperature range are defined as follows 74F Temperature Range Family 74F e Commercial 54F e Military Device Type Package Code P e Plastic DIP D e Ceramic DIP F e Flatpak L e Leadless Chip Carrier (LCC) S e Small Outline SOIC JEDEC SJ e Small Outline SOIC EIAJ 194 S C X Special Variations QB e Military grade device with environmental and burn-in processing X e Devices shipped in 13 reel Temperature Range C e Commercial (0 C to a 70 C) M e Military (b55 C to a 125 C) Physical Dimensions inches (millimeters) 20-Lead Ceramic Leadless Chip Carrier (L) NS Package Number E20A 5 Physical Dimensions inches (millimeters) (Continued) 16-Lead Ceramic Dual-In-Line Package (D) NS Package Number J16A 16-Lead (0 150 Wide) Molded Small Outline Package JEDEC (S) NS Package Number M16A 6 Physical Dimensions inches (millimeters) (Continued) 16-Lead (0 300 Wide) Molded Small Outline Package EIAJ (SJ) NS Package Number M16D 16-Lead (0 300 Wide) Molded Dual-In-Line Package (P) NS Package Number N16E 7 54F 74F194 4-Bit Bidirectional Universal Shift Register Physical Dimensions inches (millimeters) (Continued) 16-Lead Ceramic Flatpak (F) NS Package Number W16A LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION As used herein 1 Life support devices or systems are devices or systems which (a) are intended for surgical implant into the body or (b) support or sustain life and whose failure to perform when properly used in accordance with instructions for use provided in the labeling can be reasonably expected to result in a significant injury to the user National Semiconductor Corporation 1111 West Bardin Road Arlington TX 76017 Tel 1(800) 272-9959 Fax 1(800) 737-7018 2 A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system or to affect its safety or effectiveness National Semiconductor Europe Fax (a49) 0-180-530 85 86 Email cnjwge tevm2 nsc com Deutsch Tel (a49) 0-180-530 85 85 English Tel (a49) 0-180-532 78 32 Fran ais Tel (a49) 0-180-532 93 58 Italiano Tel (a49) 0-180-534 16 80 National Semiconductor Hong Kong Ltd 13th Floor Straight Block Ocean Centre 5 Canton Rd Tsimshatsui Kowloon Hong Kong Tel (852) 2737-1600 Fax (852) 2736-9960 National Semiconductor Japan Ltd Tel 81-043-299-2309 Fax 81-043-299-2408 National does not assume any responsibility for use of any circuitry described no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications