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54F273FM

54F273FM

  • 厂商:

    NSC

  • 封装:

  • 描述:

    54F273FM - Octal D Flip-Flop - National Semiconductor

  • 数据手册
  • 价格&库存
54F273FM 数据手册
54F 74F273 Octal D Flip-Flop May 1995 54F 74F273 Octal D Flip-Flop General Description The ’F273 has eight edge-triggered D-type flip-flops with individual D inputs and Q outputs The common buffered Clock (CP) and Master Reset (MR) inputs load and reset (clear) all flip-flops simultaneously The register is fully edge-triggered The state of each D input one setup time before the LOW-to-HIGH clock transition is transferred to the corresponding flip-flop’s Q output All outputs will be forced LOW independently of Clock or Data inputs by a LOW voltage level on the MR input The device is useful for applications where the true output only is required and the Clock and Master Reset are common to all storage elements Features Y Y Y Y Y Y Y Y Ideal buffer for MOS microprocessor or memory Eight edge-triggered D flip-flops Buffered common clock Buffered asynchronous Master Reset See ’F377 for clock enable version See ’F373 for transparent latch version See ’F374 for TRI-STATE version Guaranteed 4000V minimum ESD protection Commercial 74F273PC Military Package Number N20A Package Description 20-Lead (0 300 Wide) Molded Dual-In-Line 20-Lead Ceramic Dual-In-Line 20-Lead (0 300 Wide) Molded Small Outline JEDEC 20-Lead (0 300 Wide) Molded Small Outline EIAJ 20-Lead Cerpack 20-Lead Ceramic Leadless Chip Carrier Type C 54F273DM (Note 2) 74F273SC (Note 1) 74F273SJ (Note 1) 54F273FM (Note 2) 54F273LM (Note 2) J20A M20B M20D W20A E20A Note 1 Devices also available in 13 reel Use suffix e SCX and SJX Note 2 Military grade device with environmental and burn-in processing Use suffix e DMQB FMQB and LMQB Logic Symbols IEEE IEC TL F 9511 – 3 TL F 9511 – 5 TRI-STATE is a registered trademark of National Semiconductor Corporation C1995 National Semiconductor Corporation TL F 9511 RRD-B30M75 Printed in U S A Connection Diagrams Pin Assignment for DIP SOIC and Flatpak Pin Assignment for LCC TL F 9511 – 2 TL F 9511–1 Unit Loading Fan Out 54F 74F Pin Names Description UL Input IIH IIL HIGH LOW Output IOH IOL 10 10 10 10 10 10 50 33 3 20 mA b0 6 mA 20 mA b0 6 mA 20 mA b0 6 mA b 1 mA 20 mA D 0 – D7 MR CP Q0 – Q7 Data Inputs Master Reset (Active LOW) Clock Pulse Input (Active Rising Edge) Data Outputs Mode Select-Function Table Operating Mode MR Reset (Clear) Load ‘1’ Load ‘0’ L H H Inputs CP X L L Dn X h l Output Qn L H L H e HIGH Voltage Level steady state h e HIGH Voltage Level one setup time prior to the LOW-to-HIGH clock transition L e LOW Voltage Level steady state I e LOW Voltage Level one setup time prior to the LOW-to-HIGH clock transition X e Immaterial L e LOW-to-HIGH clock transition Logic Diagram TL F 9511 – 4 Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays 2 Absolute Maximum Ratings (Note 1) If Military Aerospace specified devices are required please contact the National Semiconductor Sales Office Distributors for availability and specifications Storage Temperature Ambient Temperature under Bias Junction Temperature under Bias Plastic VCC Pin Potential to Ground Pin b 65 C to a 150 b 55 C to a 125 b 55 C to a 175 b 55 C to a 150 Recommended Operating Conditions Free Air Ambient Temperature Military Commercial Supply Voltage Military Commercial b 55 C to a 125 C 0 C to a 70 C a 4 5V to a 5 5V a 4 5V to a 5 5V C C C C b 0 5V to a 7 0V b 0 5V to a 7 0V Input Voltage (Note 2) b 30 mA to a 5 0 mA Input Current (Note 2) Voltage Applied to Output in HIGH State (with VCC e 0V) b 0 5V to VCC Standard Output b 0 5V to a 5 5V TRI-STATE Output Current Applied to Output in LOW State (Max) twice the rated IOL (mA) ESD Last Passing Voltage (min) 4000V Note 1 Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired Functional operation under these conditions is not implied Note 2 Either voltage limit or current limit is sufficient to protect inputs DC Electrical Characteristics Symbol VIH VIL VCD VOH Parameter Min Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage Output LOW Voltage Input HIGH Current Input HIGH Current Breakdown Test Output HIGH Leakage Current Input Leakage Test Output Leakage Circuit Current Input LOW Current Output Short-Circuit Current Power Supply Current b 60 54F 74F Typ Max Units V 08 b1 2 VCC Conditions Recognized as a HIGH Signal Recognized as a LOW Signal 20 V V V Min Min IIN e b18 mA IOH e b1 mA Mil 10% VCC 5% VCC Mil 10% VCC 5% VCC 54F 74F 54F 74F 54F 74F 74F 74F 25 25 27 05 05 05 20 0 50 100 70 250 50 4 75 3 75 b0 6 b 150 VOL IOL e 20 mA V Min VIN e 2 7V VIN e 7 0V VOUT e VCC IID e 1 9 mA All other pins grounded VIOD e 150 mV All other pins grounded VIN e 0 5V VOUT e 0V CP e L Dn e MR e HIGH IIH IBVI ICEX VID IOD IIL IOS ICCH ICCL mA mA mA V mA mA mA mA Max Max Max 00 00 Max Max Max 44 56 3 AC Electrical Characteristics 74F Symbol Parameter Min fmax tPLH tPHL tPLH tPHL Maximum Clock Frequency Propagation Delay Clock to Output Propagation Delay MR to Output 160 30 40 45 70 9 00 95 TA e a 25 C VCC e a 5 0V CL e 50 pF Typ Max 54F TA VCC e Mil CL e 50 pF Min 95 25 30 30 95 11 0 11 0 Max 74F TA VCC e Com CL e 50 pF Min 130 25 35 40 75 90 10 0 Max MHz ns ns Units AC Operating Requirements 74F Symbol Parameter TA e a 25 C VCC e a 5 0V Min ts(H) ts(L) th(H) th(L) tw(L) tw(H) tw(L) trec Setup Time HIGH or LOW Data to CP Hold Time HIGH or LOW Data to CP MR Pulse Width LOW CP Pulse Width HIGH or LOW Recovery Time MR to CP 30 35 05 10 60 60 60 30 Max 54F TA VCC e Mil Min 35 40 10 10 40 50 50 45 Max 74F TA VCC e Com Min 30 35 05 10 60 60 60 35 ns ns ns Max Units ns Ordering Information The device number is used to form part of a simplified purchasing code where a package type and temperature range are defined as follows 74F Temperature Range Family 74F e Commercial 54F e Military Device Type Package Code P e Plastic DIP D e Ceramic DIP S e Small Outline SOIC JEDEC SJ e Small Outline SOIC EIAJ F e Flatpak L e Leadless Chip Carrier (LCC) 273 S C X Special Variations X e Devices shipped in 13 reels QB e Military grade with environmental and burn-in processing shipped in tubes Temperature Range C e Commercial (0 C to a 70 C) M e Military (b55 C to a 125 C) 4 Physical Dimensions inches (millimeters) 20-Lead Ceramic Leadless Chip Carrier (LCC) NS Package Number E20A 20-Lead Ceramic Dual-In-Line Package (D) NS Package Number J20A 5 Physical Dimensions inches (millimeters) (Continued) 20-Lead (0 300 Wide) Molded Small Outline Package JEDEC (S) NS Package Number M20B 20-Lead (0 300 Wide) Molded Small Outline Package EIAJ (SJ) NS Package Number M20D 6 Physical Dimensions inches (millimeters) (Continued) Lit 114645 20-Lead (0 300 Wide) Molded Dual-In-Line Package (P) NS Package Number N20A 7 54F 74F273 Octal D Flip-Flop Physical Dimensions inches (millimeters) (Continued) 20-Lead Ceramic Flatpak (F) NS Package Number W20A LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION As used herein 1 Life support devices or systems are devices or systems which (a) are intended for surgical implant into the body or (b) support or sustain life and whose failure to perform when properly used in accordance with instructions for use provided in the labeling can be reasonably expected to result in a significant injury to the user National Semiconductor Corporation 2900 Semiconductor Drive P O Box 58090 Santa Clara CA 95052-8090 Tel 1(800) 272-9959 TWX (910) 339-9240 National Semiconductor GmbH Livry-Gargan-Str 10 D-82256 F4urstenfeldbruck Germany Tel (81-41) 35-0 Telex 527649 Fax (81-41) 35-1 National Semiconductor Japan Ltd Sumitomo Chemical Engineering Center Bldg 7F 1-7-1 Nakase Mihama-Ku Chiba-City Ciba Prefecture 261 Tel (043) 299-2300 Fax (043) 299-2500 2 A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system or to affect its safety or effectiveness National Semiconductor Hong Kong Ltd 13th Floor Straight Block Ocean Centre 5 Canton Rd Tsimshatsui Kowloon Hong Kong Tel (852) 2737-1600 Fax (852) 2736-9960 National Semiconductores Do Brazil Ltda Rue Deputado Lacorda Franco 120-3A Sao Paulo-SP Brazil 05418-000 Tel (55-11) 212-5066 Telex 391-1131931 NSBR BR Fax (55-11) 212-1181 National Semiconductor (Australia) Pty Ltd Building 16 Business Park Drive Monash Business Park Nottinghill Melbourne Victoria 3168 Australia Tel (3) 558-9999 Fax (3) 558-9998 National does not assume any responsibility for use of any circuitry described no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications
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