54F652FM

54F 74F651  54F 74F652 Transceivers Registers December 1994 54F 74F651  54F 74F652 Transceivers Registers General Description These devices consist of bus transceiver circuits with D-type flip-flops and control circuitry arranged for multiplexed transmission of data directly from the input bus or from internal registers Data on the A or B bus will be clocked into the registers as the appropriate clock pin goes to HIGH logic level Output Enable pins (OEAB OEBA) are provided to control the transceiver function Features Y Y Y Y Independent registers for A and B buses Multiplexed real-time and stored data Choice of non-inverting and inverting data paths ’F651 inverting ’F652 non-inverting Guaranteed 4000V minimum ESD protection Commercial 74F651SPC Military Package Number N24C Package Description 24-Lead (0 300 Wide) Molded Dual-In-Line 24-Lead (0 300 Wide) Ceramic Dual-In-Line 24-Lead (0 300 Wide) Molded Small Outline JEDEC 24-Lead Cerpack 24-Lead Ceramic Leadless Chip Carrier Type C 24-Lead (0 300 Wide) Molded Dual-In-Line 24-Lead (0 300 Wide) Ceramic Dual-In-Line 24-Lead (0 300 Wide) Molded Small Outline JEDEC 24-Lead Cerpack 24-Lead Ceramic Leadless Chip Carrier Type C 54F651SDM (Note 2) 74F651SC (Note 1) 54F651FM (Note 2) 54F651LM (Note 2) 74F652SPC 54F652SDM (Note 2) 74F652SC (Note 1) 54F652FM (Note 2) 54F652LM (Note 2) Note 1 Devices also available in 13 reel Use suffix e SCX J24F M24B W24C E28A N24C J24F M24B W24C E28A Note 2 Military grade device with environmental and burn-in processing Use suffix e DMQB FMQB and LMQB Connection Diagrams Pin Assignment DIP SOIC and Flatpak Pin Assignment for LCC TL F 9581 – 3 TL F 9581 – 4 TRI-STATE is a registered trademark of National Semiconductor Corporation C1995 National Semiconductor Corporation TL F 9581 RRD-B30M75 Printed in U S A Logic Symbols IEEE IEC ’F651 IEEE IEC ’F652 TL F 9581–1 TL F 9581 – 10 ’F651 ’F652 TL F 9581 – 11 TL F 9581–2 Unit Loading Fan Out 54F 74F Pin Names Description UL HIGH LOW Input IIH IIL Output IOH IOL A0 – A7 B0 – B7 A and B Inputs 10 10 20 mA b0 6 mA TRI-STATE Outputs 600 106 6 (80) b12 mA 64 mA (48 mA) CPAB CPBA Clock Inputs 10 10 20 mA b0 6 mA SAB SBA Select Inputs 10 10 20 mA b0 6 mA OEAB OEBA Output Enable Inputs 10 10 20 mA b0 6 mA 2 Logic Diagrams ’F652 TL F 9581 – 5 Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays ’F651 TL F 9581 – 12 Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays 3 Functional Description In the transceiver mode data present at the HIGH impedance port may be stored in either the A or B register or both The select (SAB SBA) controls can multiplex stored and real-time The examples in Figure 1 demonstrate the four fundamental bus-management functions that can be performed with the Octal bus transceivers and receivers Data on the A or B data bus or both can be stored in the internal D flip-flop by LOW to HIGH transitions at the approNote A Real-Time Transfer Bus B to Bus A Note B Real-Time Transfer Bus A to Bus B priate Clock Inputs (CPAB CPBA) regardless of the Select or Output Enable Inputs When SAB and SBA are in the real time transfer mode it is also possible to store data without using the internal D flip-flops by simultaneously enabling OEAB and OEBA In this configuration each Output reinforces its Input Thus when all other data sources to the two sets of bus lines are in a HIGH impedance state each set of bus lines will remain at its last state Note C Storage Note D Transfer Storage Data to A or B TL F 9581 – 8 TL F 9581–6 OEAB L OEBA L CPAB X CPBA X SAB X SBA L OEAB H OEBA H CPAB X TL F 9581– 7 CPBA X SAB L SBA X OEAB X L L OEBA H X H CPAB L X L CPBA X L L SAB X X X SBA X X X OEAB H OEBA L CPAB H or L TL F 9581 – 9 CPBA H or L SAB H SBA X FIGURE 1 Inputs OEAB L L X H L L L L H H H OEBA H H H H X L L L H H L CPAB H or L L L L H or L L X X X H or L H or L CPBA H or L L H or L L L L X H or L X X H or L SAB X X X X X X X X L H H SBA X X X X X X L H X X H Output Output Input Output Input Input Not Specified Output Output Not Specified Output Input Input Input Inputs Outputs (Note 1) A0 thru A7 Input B0 thru B7 Input Isolation Store A and B Data Store A Hold B Store A in Both Registers Hold A Store B Store B in Both Registers Real-Time B Data to A Bus Store B Data to A Bus Real-Time A Data to B Bus Stored A Data to B Bus Stored A Data to B Bus and Stored B Data to A Bus Operating Mode H e HIGH Voltage Level L e LOW Voltage Level X e Immaterial L e LOW to HIGH Clock Transition Note 1 The data output functions may be enabled or disabled by various signals at OEAB or OEBA inputs Data input functions are always enabled i e data at the bus pins will be stored on every LOW to HIGH transition on the clock inputs 4 Absolute Maximum Ratings (Note 1) If Military Aerospace specified devices are required please contact the National Semiconductor Sales Office Distributors for availability and specifications Storage Temperature Ambient Temperature under Bias Junction Temperature under Bias Plastic VCC Pin Potential to Ground Pin Input Voltage (Note 2) Input Current (Note 2) b 65 C to a 150 C b 55 C to a 125 C b 55 C to a 175 C b 55 C to a 150 C b 0 5V to a 7 0V b 0 5V to a 7 0V b 30 mA to a 5 0 mA Voltage Applied to Output in HIGH State (with VCC e 0V) b 0 5V to VCC Standard Output b 0 5V to a 5 5V TRI-STATE Output Current Applied to Output in LOW State (Max) twice the rated IOL (mA) ESD Last Passing Voltage (Min) 4000V Recommended Operating Conditions Free Air Ambient Temperature Military Commercial Supply Voltage Military Commercial b 55 C to a 125 C 0 C to a 70 C a 4 5V to a 5 5V a 4 5V to a 5 5V Note 1 Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired Functional operation under these conditions is not implied Note 2 Either voltage limit or current limit is sufficient to protect inputs DC Electrical Characteristics Symbol VIH VIL VCD VOH VOL IIH IBVI IBVIT ICEX VID IOD IIL IIH a IOZH IIL a IOZL IOS IZZ ICCH ICCL ICCZ Parameter Min Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage Output LOW Voltage Input HIGH Current Input HIGH Current Breakdown Test Input HIGH Current Breakdown (I O) Output HIGH Leakage Current Input Leakage Test Output Leakage Circuit Current Input LOW Current Output Leakage Current Output Leakage Current Output Short-Circuit Current Bus Drainage Test Power Supply Current Power Supply Current Power Supply Current 105 118 115 b 100 54F 74F Typ Max Units V 08 b1 2 VCC Conditions Recognized as a HIGH Signal Recognized as a LOW Signal 20 V V V Min Min Min Max Max Max Max 00 00 Max Max Max Max 0 0V Max Max Max IIN e b18 mA (Non I O Pins) IOH e b12 mA (An Bn) IOH e b15 mA (An Bn) IOL e 48 mA (An Bn) IOL e 64 mA (An Bn) VIN e 2 7V (Non I O Pins) VIN e 7 0V VIN e 5 5V (An Bn) VOUT e VCC IID e 1 9 mA All Other Pins Grounded VIIOD e 150 mV All Other Pins Grounded VIN e 0 5V (Non I O Pins) VOUT e 2 7V (An Bn) VOUT e 0 5V (An Bn) VOUT e 0V VOUT e 5 25V VO e HIGH VO e LOW VO e HIGH Z 54F 10% VCC 74F 10% VCC 54F 10% VCC 74F 10% VCC 54F 74F 54F 74F 54F 74F 54F 74F 74F 74F 20 20 0 55 0 55 20 0 50 100 70 10 05 250 50 4 75 3 75 b0 6 V mA mA mA mA V mA mA mA mA mA mA mA mA mA 70 b 650 b 225 500 135 150 150 5 AC Electrical Characteristics 74F Symbol Parameter TA e a 25 C VCC e a 5 0V CL e 50 pF Min fmax tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL Max Clock Frequency Propagation Delay Clock to Bus Propagation Delay Bus to Bus (’F651) Propagation Delay Bus to Bus (’F652) Propagation Delay SBA or SAB to A or B 90 20 20 20 10 10 10 20 20 70 80 85 75 70 65 85 80 Max 54F TA VCC e Mil CL e 50 pF Min 75 20 20 10 10 10 10 20 20 85 95 90 80 80 80 11 0 10 0 Max 74F TA VCC e Com CL e 50 pF Min 90 20 20 20 10 10 10 20 20 80 90 90 80 75 70 95 90 Max MHz ns ns ns ns Units AC Operating Requirements 74F Symbol Parameter TA e a 25 C VCC e a 5 0V Min tPZH tPZL tPHZ tPLZ tPZH tPZL tPHZ tPLZ ts(H) ts(L) th(H) th(L) tw(H) tw(L) Enable Time OEBA to A Disable Time OEBA to A Enable Time OEAB to B Disable Time OEAB to B Setup Time HIGH or LOW Bus to Clock Hold Time HIGH or LOW Bus to Clock Clock Pulse Width HIGH or LOW 20 20 10 20 20 30 20 20 50 50 20 20 50 50 Max 95 12 0 75 85 95 13 0 90 10 5 54F TA VCC e Mil Min 20 20 10 10 20 20 10 10 50 50 25 25 50 50 Max 10 0 10 0 90 90 10 0 12 0 90 12 0 74F TA VCC e Com Min 20 20 10 20 20 30 20 20 50 50 20 20 50 50 Max 10 0 12 5 80 90 10 0 14 0 10 0 11 0 ns ns ns ns ns Units Ordering Information The device number is used to form part of a simplified purchasing code where the package type and temperature range are defined as follows 74F Temperature Range Family 74F e Commercial 54F e Military Device Type Package Code SP e Slim Plastic DIP SD e Slim Ceramic DIP S e Small Outline (SOIC) 651 652 S C X Special Variations QB e Military grade device with environmental and burn-in processing X e Devices shipped in 13 reel Temperature Range C e Commercial (0 C to a 70 C) M e Military (b55 C to a 125 C) 6 7 Physical Dimensions inches (millimeters) 28 Lead Ceramic Leadless Chip Carrier Type C NS Package Number E28A 24 Lead (0 300 Wide) Ceramic Dual-In-Line Package (SD) NS Package Number J24F 8 Physical Dimensions inches (millimeters) (Continued) 24 Lead (0 300 Wide) Molded Small Outline Package JEDEC (S) NS Package Number M24B 24 Lead (0 300 Wide) Molded Dual-In-Line Package (SP) NS Package Number N24C 9 54F 74F651  54F 74F652 Transceivers Registers Physical Dimensions inches (millimeters) (Continued) 24 Lead Cerpack NS Package Number W24C LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION As used herein 1 Life support devices or systems are devices or systems which (a) are intended for surgical implant into the body or (b) support or sustain life and whose failure to perform when properly used in accordance with instructions for use provided in the labeling can be reasonably expected to result in a significant injury to the user National Semiconductor Corporation 2900 Semiconductor Drive P O Box 58090 Santa Clara CA 95052-8090 Tel 1(800) 272-9959 TWX (910) 339-9240 National Semiconductor GmbH Livry-Gargan-Str 10 D-82256 F4urstenfeldbruck Germany Tel (81-41) 35-0 Telex 527649 Fax (81-41) 35-1 National Semiconductor Japan Ltd Sumitomo Chemical Engineering Center Bldg 7F 1-7-1 Nakase Mihama-Ku Chiba-City Ciba Prefecture 261 Tel (043) 299-2300 Fax (043) 299-2500 2 A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system or to affect its safety or effectiveness National Semiconductor Hong Kong Ltd 13th Floor Straight Block Ocean Centre 5 Canton Rd Tsimshatsui Kowloon Hong Kong Tel (852) 2737-1600 Fax (852) 2736-9960 National Semiconductores Do Brazil Ltda Rue Deputado Lacorda Franco 120-3A Sao Paulo-SP Brazil 05418-000 Tel (55-11) 212-5066 Telex 391-1131931 NSBR BR Fax (55-11) 212-1181 National Semiconductor (Australia) Pty Ltd Building 16 Business Park Drive Monash Business Park Nottinghill Melbourne Victoria 3168 Australia Tel (3) 558-9999 Fax (3) 558-9998 National does not assume any responsibility for use of any circuitry described no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications