74LS163A

54LS161A DM54LS161A DM74LS161A 54LS163A DM54LS163A DM74LS163A Synchronous 4-Bit Binary Counters May 1992 54LS161A DM54LS161A DM74LS161A 54LS163A DM54LS163A DM74LS163A Synchronous 4-Bit Binary Counters General Description These synchronous presettable counters feature an internal carry look-ahead for application in high-speed counting designs The LS161A and LS163A are 4-bit binary counters The carry output is decoded by means of a NOR gate thus preventing spikes during the normal counting mode of operation Synchronous operation is provided by having all flipflops clocked simultaneously so that the outputs change coincident with each other when so instructed by the countenable inputs and internal gating This mode of operation eliminates the output counting spikes which are normally associated with asynchronous (ripple clock) counters A buffered clock input triggers the four flip-flops on the rising (positive-going) edge of the clock input waveform These counters are fully programmable that is the outputs may be preset to either level As presetting is synchronous setting up a low level at the load input disables the counter and causes the outputs to agree with the setup data after the next clock pulse regardless of the levels of the enable input The clear function for the LS161A is asynchronous and a low level at the clear input sets all four of the flip-flop outputs low regardless of the levels of clock load or enable inputs The clear function for the LS163A is synchronous and a low level at the clear inputs sets all four of the flip-flop outputs low after the next clock pulse regardless of the levels of the enable inputs This synchronous clear allows the count length to be modified easily as decoding the maximum count desired can be accomplished with one external NAND gate The gate output is connected to the clear input to synchronously clear the counter to all low outputs The carry look-ahead circuitry provides for cascading counters for n-bit synchronous applications without additional gating Instrumental in accomplishing this function are two count-enable inputs and a ripple carry output Both count-enable inputs (P and T) must be high to count and input T is fed forward to enable the ripple carry output The ripple carry output thus enabled will produce a high-level output pulse with a duration approximately equal to the high-level portion of the QA output This high-level overflow ripple carry pulse can be used to enable successive cascaded stages High-to-low level transitions at the enable P or T inputs may occur regardless of the logic level of the clock These counters feature a fully independent clock circuit Changes made to control inputs (enable P or T or load) that will modify the operating mode have no effect until clocking occurs The function of the counter (whether enabled disabled loading or counting) will be dictated solely by the conditions meeting the stable set-up and hold times Features Y Y Y Y Y Y Y Y Y Y Synchronously programmable Internal look-ahead for fast counting Carry output for n-bit cascading Synchronous counting Load control line Diode-clamped inputs Typical propagation time clock to Q output 14 ns Typical clock frequency 32 MHz Typical power dissipation 93 mW Alternate Military Aerospace device (54LS161 54LS163) is available Contact a National Semiconductor Sales Office Distributor for specificaitons Connection Diagram Dual-In-Line Package Order Numbers 54LS161ADMQB 54LS161AFMQB 54LS161ALMQB 54LS163ADMQB 54LS163AFMQB 54LS163ALMQB DM54LS161AJ DM54LS161AW DM54LS163AJ DM54LS163AW DM74LS161AM DM74LS161AN DM74LS163AM or DM74LS163AN See NS Package Number E20A J16A M16A N16E or W16A TL F 6397 – 1 C1995 National Semiconductor Corporation TL F 6397 RRD-B30M105 Printed in U S A Absolute Maximum Ratings (Note) If Military Aerospace specified devices are required please contact the National Semiconductor Sales Office Distributors for availability and specifications Supply Voltage 7V Input Voltage 7V Operating Free Air Temperature Range b 55 C to a 125 C DM54LS and 54LS DM74LS 0 C to a 70 C Storage Temperature Range b 65 C to a 150 C Note The ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed The device should not be operated at these limits The parametric values defined in the ‘‘Electrical Characteristics’’ table are not guaranteed at the absolute maximum ratings The ‘‘Recommended Operating Conditions’’ table will define the conditions for actual device operation Recommended Operating Conditions Symbol VCC VIH VIL IOH IOL fCLK Parameter Min Supply Voltage High Level Input Voltage Low Level Input Voltage High Level Output Current Low Level Output Current Clock Frequency (Note 1) Clock Frequency (Note 2) tW Pulse Width (Note 1) Pulse Width (Note 2) tSU Setup Time (Note 1) Clock Clear Clock Clear Data Enable P Load Setup Time (Note 2) Data Enable P Load tH Hold Time (Note 1) Hold Time (Note 2) tREL Data Others Data Others 0 0 20 20 25 25 20 25 25 20 30 30 0 0 5 5 20 25 b 55 b3 b3 DM54LS161A Nom 5 Max 55 Min 4 75 2 07 b0 4 DM74LS161A Nom 5 Max 5 25 Units V V 08 b0 4 45 2 V mA mA MHz MHz ns 4 25 20 6 9 0 0 20 20 25 25 8 17 15 20 25 25 20 30 30 0 0 5 5 20 25 125 0 b3 b3 8 25 20 6 9 ns 8 17 15 ns ns ns ns ns ns 70 C Clear Release Time (Note 1) Clear Release Time (Note 2) TA Free Air Operating Temperature Note 1 CL e 15 pF RL e 2 kX TA e 25 C and VCC e 5 5V Note 2 CL e 50 pF RL e 2 kX TA e 25 C and VCC e 5 5V 2 ’LS161 Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted) Symbol VI VOH Parameter Input Clamp Voltage High Level Output Voltage Low Level Output Voltage Conditions VCC e Min II e b18 mA VCC e Min IOH e Max VIL e Max VIH e Min VCC e Min IOL e Max VIL e Max VIH e Min IOL e 4 mA VCC e Min II Input Current Input Voltage Max VCC e Max VI e 7V DM54 DM74 DM54 DM74 DM74 Enable T Clock Load Others IIH High Level Input Current VCC e Max VI e 2 7V Enable T Clock Load Others IIL Low Level Input Current VCC e Max VI e 0 4V Enable T Clock Load Others IOS Short Circuit Output Current Supply Current with Outputs High Supply Current with Outputs Low VCC e Max (Note 2) VCC e Max (Note 3) VCC e Max (Note 4) DM54 DM74 b 20 b 20 Min Typ (Note 1) Max b1 5 Units V V 25 27 34 34 0 25 0 35 0 25 04 05 04 02 02 02 01 40 40 40 20 b0 8 b0 8 b0 8 b0 4 b 100 b 100 VOL V mA mA mA mA ICCH ICCL 18 31 mA mA 19 32 Note 1 All typicals are at VCC e 5V TA e 25 C Note 2 Not more than one output should be shorted at a time and the duration should not exceed one second Note 3 ICCH is measured with the load high then again with the load low with all other inputs high and all outputs open Note 4 ICCL is measured with the clock input high then again with the clock input low with all other inputs low and all outputs open ’LS161 Switching Characteristics at VCC e 5V and TA e 25 C (See Section 1 for Test Waveforms and Output Load) From (Input) To (Output) RL e 2 k X CL e 15 pF Min fMAX tPLH tPHL tPLH tPHL Maximum Clock Frequency Propagation Delay Time Low to High Level Output Propagation Delay Time High to Low Level Output Propagation Delay Time Low to High Level Output Propagation Delay Time High to Low Level Output Clock to Ripple Carry Clock to Ripple Carry Clock to Any Q (Load High) Clock to Any Q (Load High) 25 25 30 22 27 Max CL e 50 pF Min 20 30 38 27 38 Max MHz ns ns ns ns Units Symbol Parameter 3 ’LS161 Switching Characteristics at VCC e 5V and TA e 25 C (See Section 1 for Test Waveforms and Output Load) (Continued) From (Input) To (Output) Clock to Any Q (Load Low) Clock to Any Q (Load Low) Enable T to Ripple Carry Enable T to Ripple Carry Clear to Any Q RL e 2 kX CL e 15 pF Min tPLH tPHL tPLH tPHL tPHL Propagation Delay Time Low to High Level Output Propagation Delay Time High to Low Level Output Propagation Delay Time Low to High Level Output Propagation Delay Time High to Low Level Output Propagation Delay Time High to Low Level Output Max 24 27 14 15 28 CL e 50 pF Min Max 30 38 27 27 45 ns ns ns ns ns Units Symbol Parameter Recommended Operating Conditions Symbol VCC VIH VIL IOH IOL fCLK Parameter Min Supply Voltage High Level Input Voltage Low Level Input Voltage High Level Output Current Low Level Output Current Clock Frequency (Note 1) Clock Frequency (Note 2) tW Pulse Width (Note 1) Pulse Width (Note 2) tSU Setup Time (Note 1) Clock Clear Clock Clear Data Enable P Load Setup Time (Note 2) Data Enable P Load tH Hold Time (Note 1) Hold Time (Note 2) tREL Data Others Data Others 0 0 20 20 25 25 20 25 25 20 30 30 0 0 5 5 20 25 b 55 b3 b3 DM54LS163A Nom 5 Max 55 Min 4 75 2 07 b0 4 DM74LS163A Nom 5 Max 5 25 Units V V 08 b0 4 45 2 V mA mA MHz MHz ns 4 25 20 6 9 0 0 20 20 25 25 8 17 15 20 25 25 20 30 30 0 0 5 5 20 25 125 0 b3 b3 8 25 20 6 9 ns 8 17 15 ns ns ns ns ns ns 70 C Clear Release Time (Note 1) Clear Release Time (Note 2) TA Free Air Operating Temperature Note 1 CL e 15 pF RL e 2 kX TA e 25 C and VCC e 5V Note 2 CL e 50 pF RL e 2 kX TA e 25 C and VCC e 5V 4 ’LS163 Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted) Symbol VI VOH Parameter Input Clamp Voltage High Level Output Voltage Low Level Output Voltage Conditions VCC e Min II e b18 mA VCC e Min IOH e Max VIL e Max VIH e Min VCC e Min IOL e Max VIL e Max VIH e Min IOL e 4 mA VCC e Min II Input Current Input Voltage Max VCC e Max VI e 7V DM54 DM74 DM54 DM74 DM74 Enable T Clock Clear Load Others IIH High Level Input Current VCC e Max VI e 2 7V Enable T Load Clock Clear Others IIL Low Level Input Current VCC e Max VI e 0 4V Enable T Clock Clear Load Others IOS Short Circuit Output Current Supply Current with Outputs High Supply Current with Outputs Low VCC e Max (Note 2) VCC e Max (Note 3) VCC e Max (Note 4) DM54 DM74 b 20 b 20 Min Typ (Note 1) Max b1 5 Units V V 25 27 34 34 0 25 0 35 0 25 04 05 04 02 02 02 01 40 40 40 20 b0 8 b0 8 b0 8 b0 4 b 100 b 100 VOL V mA mA mA mA ICCH ICCL 18 31 mA mA 18 32 Note 1 All typicals are at VCC e 5V TA e 25 C Note 2 Not more than one output should be shorted at a time and the duration should not exceed one second Note 3 ICCH is measured with the load high then again with the load low with all other inputs high and all outputs open Note 4 ICCL is measured with the clock input high then again with the clock input low with all other inputs low and all outputs open ’LS163 Switching Characteristics at VCC e 5V and TA e 25 C (See Section 1 for Test Waveforms and Output Load) From (Input) To (Output) RL e 2 k X CL e 15 pF Min fMAX tPLH tPHL tPLH tPHL Maximum Clock Frequency Propagation Delay Time Low to High Level Output Propagation Delay Time High to Low Level Output Propagation Delay Time Low to High Level Output Propagation Delay Time High to Low Level Output Clock to Ripple Carry Clock to Ripple Carry Clock to Any Q (Load High) Clock to Any Q (Load High) 25 25 30 22 27 Max CL e 50 pF Min 20 30 38 27 38 Max MHz ns ns ns ns Units Symbol Parameter 5 ’LS163 Switching Characteristics at VCC e 5V and TA e 25 C (See Section 1 for Test Waveforms and Output Load) (Continued) From (Input) To (Output) RL e 2 kX CL e 15 pF Min tPLH tPHL tPLH tPHL tPHL Propagation Delay Time Low to High Level Output Propagation Delay Time High to Low Level Output Propagation Delay Time Low to High Level Output Propagation Delay Time High to Low Level Output Propagation Delay Time High to Low Level Output Clock to Any Q (Load Low) Clock to Any Q (Load Low) Enable T to Ripple Carry Enable T to Ripple Carry Clear to Any Q (Note 1) Max 24 27 14 15 28 CL e 50 pF Min Max 30 38 27 27 45 ns ns ns ns ns Units Symbol Parameter Note 1 The propagation delay clear to output is measured from the clock input transition Logic Diagram LS163A TL F 6397 – 2 The LS161A is similar however the clear buffer is connected directly to the flip flops 6 Parameter Measurement Information Switching Time Waveforms TL F 6397 – 3 Note A The input pulses are supplied by generators having the following characteristics PRR s 1 MHz duty cycle s 50% ZOUT Vary PRR to measure fMAX Note B Outputs QD and carry are tested at tn a 16 where tn is the bit time when all outputs are low Note C VREF e 1 5V 50X tr s 10 ns tf s 10 ns Switching Time Waveforms TL F 6397 – 4 Note A The input pulses are supplied by generators having the following characteristics PRR s 1 MHz duty cycle s 50% ZOUT PRR to measure fMAX Note B Enable P and enable T setup times are measured at tn a 0 Note C VREF e 1 3V 50X tr s 6 ns tf s 6 ns Vary 7 Timing Diagram LS161A LS163A Synchronous Binary Counters Typical Clear Preset Count and Inhibit Sequences TL F 6397 – 5 Sequence (1) Clear outputs to zero (2) Preset to binary twelve (3) Count to thirteen fourteen fifteen zero one and two (4) Inhibit 8 9 Physical Dimensions inches (millimeters) Ceramic Leadless Chip Carrier Package (E) Order Numbers 54LS161ALMQB or 54LS163ALMQB NS Package Number E20A 16-Lead Ceramic Dual-In-Line Package (J) Order Numbers 54LS161ADMQB 54LS163ADMQB DM54LS161AJ or DM54LS163AJ NS Package Number J16A 10 Physical Dimensions inches (millimeters) (Continued) 16-Lead Small Outline Molded Package (M) Order Number DM74LS161AM or DM74LS163AM NS Package Number M16A 16-Lead Molded Dual-In-Line Package (N) Order Numbers DM74LS161AN DM74LS163AN NS Package Number N16E 11 54LS161A DM54LS161A DM74LS161A 54LS163A DM54LS163A DM74LS163A Synchronous 4-Bit Binary Counters Physical Dimensions inches (millimeters) (Continued) 16-Lead Ceramic Flat Package (W) Order Numbers 54LS161AFMQB 54LS163AFMQB DM54LS161AN or DM54LS163AW NS Package Number W16A LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION As used herein 1 Life support devices or systems are devices or systems which (a) are intended for surgical implant into the body or (b) support or sustain life and whose failure to perform when properly used in accordance with instructions for use provided in the labeling can be reasonably expected to result in a significant injury to the user National Semiconductor Corporation 1111 West Bardin Road Arlington TX 76017 Tel 1(800) 272-9959 Fax 1(800) 737-7018 2 A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system or to affect its safety or effectiveness National Semiconductor Europe Fax (a49) 0-180-530 85 86 Email cnjwge tevm2 nsc com Deutsch Tel (a49) 0-180-530 85 85 English Tel (a49) 0-180-532 78 32 Fran ais Tel (a49) 0-180-532 93 58 Italiano Tel (a49) 0-180-534 16 80 National Semiconductor Hong Kong Ltd 13th Floor Straight Block Ocean Centre 5 Canton Rd Tsimshatsui Kowloon Hong Kong Tel (852) 2737-1600 Fax (852) 2736-9960 National Semiconductor Japan Ltd Tel 81-043-299-2309 Fax 81-043-299-2408 National does not assume any responsibility for use of any circuitry described no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications