74LVX373MTC

74LVX373 Low Voltage Octal Transparent Latch with TRI-STATE Outputs January 1996 74LVX373 Low Voltage Octal Transparent Latch with TRI-STATE Outputs General Description The LVX373 consists of eight latches with TRI-STATE outputs for bus organized system applications The latches appear transparent to the data when Latch Enable (LE) is HIGH When LE is low the data satisfying the input timing requirements is latched Data appears on the bus when the Output Enable (OE) is LOW When OE is HIGH the bus output is in the high impedance state The inputs tolerate up to 7V allowing interface of 5V systems to 3V systems Features Y Y Y Y Input voltage translation from 5V to 3V Ideal for low power low noise 3 3V applications Available in SOIC JEDEC SOIC EIAJ and TSSOP packages Guaranteed simultaneous switching noise level and dynamic threshold performance Logic Symbols IEEE IEC Connection Diagram Pin Assignment for SOIC and TSSOP TL F 11613–1 TL F 11613 – 4 TL F 11613 – 2 Pin Names D0 – D7 LE OE O 0 – O7 Description Data Inputs Latch Enable Input Output Enable Input TRI-STATE Latch Outputs SOIC JEDEC Order Number See NS Package Number 74LVX373M 74LVX373MX M20B SOIC EIAJ 74LVX373SJ 74LVX373SJX M20D TSSOP 74LVX373MTC 74LVX373MTCX MTC20 TRI-STATE is a registered trademark of National Semiconductor Corporation C1996 National Semiconductor Corporation TL F 11613 RRD-B30M17 Printed in U S A http www national com Functional Description The LVX373 contains eight D-type latches with TRI-STATE standard outputs When the Latch Enable (LE) input is HIGH data on the Dn inputs enters the latches In this condition the latches are transparent i e a latch output will change state each time its D input changes When LE is LOW the latches store the information that was present on the D inputs a setup time preceding the HIGH-to-LOW transition of LE The TRI-STATE standard outputs are controlled by the Output Enable (OE) input When OE is LOW the standard outputs are in the 2-state mode When OE is HIGH the standard outputs are in the high impedance mode but this does not interfere with entering new data into the latches Truth Table Inputs LE X H H L OE H L L L Dn X L H X Outputs On Z L H O0 H e HIGH Voltage Level L e LOW Voltage Level Z e High Impedance X e Immaterial O0 e Previous O0 before HIGH to Low transition of Latch Enable Logic Diagram TL F 11613 – 3 Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays http www national com 2 Absolute Maximum Ratings (Note) If Military Aerospace specified devices are required please contact the National Semiconductor Sales Office Distributors for availability and specifications b 0 5V to a 7 0V Supply Voltage (VCC) DC Input Diode Current (IIK) b 20 mA VI e b0 5V b 0 5V to 7V DC Input Voltage (VI) DC Output Diode Current (IOK) b 20 mA VO e b0 5V a 20 mA VO e VCC a 0 5V b 0 5V to VCC a 0 5V DC Output Voltage (VO) DC Output Source g 25 mA or Sink Current (IO) DC VCC or Ground Current g 75 mA (ICC or IGND) b 65 C to a 150 C Storage Temperature (TSTG) Power Dissipation 180 mW Note The ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed The device should not be operated at these limits The parametric values defined in the ‘‘Electrical Characteristics’’ table are not guaranteed at the absolute maximum ratings The ‘‘Recommended Operating Conditions’’ table will define the conditions for actual device operation Recommended Operating Conditions Supply Voltage (VCC) Input Voltage (VI) Output Voltage (VO) Operating Temperature (TA) Input Rise and Fall Time (Dt DV) 2 0V to 3 6V 0V to 5 5V 0V to VCC b 40 C to a 85 C 0 ns V to 100 ns V DC Electrical Characteristics 74LVX373 Symbol Parameter VCC TA e a 25 C Min VIH High Level Input Voltage Low Level Input Voltage High Level Output Voltage Low Level Output Voltage TRI-STATE Output Off-State Current Input Leakage Current Quiescent Supply Current 20 30 36 20 30 36 20 30 30 20 30 30 36 19 29 2 58 20 30 00 00 01 01 0 36 g 0 25 74LVX373 TA e b 40 C to a 85 C Min 15 20 24 05 08 08 19 29 2 48 01 01 0 44 g2 5 Units Conditions Typ Max Max V 05 08 08 15 20 24 VIL V VIN e VIH or VIL V VIN e VIH or VIL V mA IOH e b50 mA IOH e b50 mA IOH e b4 mA IOL e 50 mA IOL e 50 mA IOL e 4 mA VOH VOL IOZ VIN e VIH or VIL VOUT e VCC or GND IIN 36 g0 1 g1 0 mA VIN e 5 5V or GND ICC 36 40 40 0 mA VIN e VCC or GND 3 http www national com Noise Characteristics 74LVX373 Symbol Parameter VCC (V) 33 33 33 33 TA e 25 C Typ VOLP VOLV VIHD VILD Quiet Output Maximum Dynamic VOL Quiet Output Minimum Dynamic VOL Minimum High Level Dynamic Input Voltage Maximum Low Level Dynamic Input Voltage 05 b0 5 Units CL (pF) Limit 08 b0 8 V V V V 50 50 50 50 20 08 Note Input tr e tf e 3 ns AC Electrical Characteristics 74LVX373 Symbol Parameter VCC (V) Min tPLH tPHL Propagation Delay Time Dn to On 27 TA e a 25 C Typ 77 10 2 3 3 g0 3 tPLH tPHL Propagation Delay Time LE to On 60 85 27 75 10 0 3 3 g0 3 tPZL tPZH TRI-STATE Output Enable Time 58 83 27 77 10 2 3 3 g0 3 tPLZ tPHZ tW tS tH tOSLH tOSHL TRI-STATE Output Disable Time LE Pulse Width HIGH 27 3 3 g0 3 27 3 3 g0 3 Setup Time Dn to LE Hold Time Dn to LE Output to Output Skew (Note 1) 27 3 3 g0 3 27 3 3 g0 3 27 65 50 60 40 10 10 15 60 85 98 82 Max 15 0 18 5 97 13 2 14 5 18 0 93 12 8 15 0 18 5 97 13 2 18 0 12 8 74LVX373 TA e b 40 C to a 85 C Min 10 10 10 10 10 10 10 10 10 10 10 10 10 10 75 50 60 40 10 10 15 ns CL e 50 pF ns ns Max 18 5 22 0 11 5 15 0 17 5 21 0 11 0 14 5 18 5 22 0 11 5 15 0 21 0 14 5 ns ns ns ns ns CL e 15 pF CL e 50 pF CL e 15 pF CL e 50 pF CL e 15 pF CL e 50 pF CL e 15 pF CL e 50 pF CL e 15 pF RL e 1 kX CL e 50 pF RL e 1 kX CL e 15 pF RL e 1 kX CL e 50 pF RL e 1 kX CL e 50 pF RL e 1 kX CL e 50 pF RL e 1 kX Units Conditions Note 1 Parameter guaranteed by design tOSLH e l tPLHm b tPLHn l tOSHL e l tPHLm b tPHLn l http www national com 4 Capacitance 74LVX373 Symbol Parameter Min CIN COUT CPD Input Capacitance Output Capacitance Power Dissipation Capacitance (Note 1) TA e a 25 C Typ 4 6 27 Max 10 74LVX373 TA e b 40 C to a 85 C Min Max 10 pF pF pF Units Note 1 CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load CPD c VCC c fIN a ICC Average operating current can be obtained by the equation ICC(opr ) e 8 (per Latch) 74LVX373 Ordering Information The device number is used to form part of a simplified purchasing code where the package type and temperature range are defined as follows TL F 11613 – 5 5 http www national com Physical Dimensions inches (millimeters) unless otherwise noted 20-Lead Small Outline Integrated Circuit (M) Order Number 74LVX373M or 74LVX373MX NS Package Number M20B http www national com 6 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Small Outline Package EIAJ SOIC (SJ) Order Number 74LVX373SJ or 74LVX373SJX NS Package Number M20D 7 http www national com 74LVX373 Low Voltage Octal Transparent Latch with TRI-STATE Outputs Physical Dimensions All dimensions are in millimeters (Continued) 16-Lead Thin Shrink Small Outline Package JEDEC Order Number 74LVX373MTC or 74LVX373MTCX NS Package Number MTC20 LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION As used herein 1 Life support devices or systems are devices or systems which (a) are intended for surgical implant into the body or (b) support or sustain life and whose failure to perform when properly used in accordance with instructions for use provided in the labeling can be reasonably expected to result in a significant injury to the user National Semiconductor Corporation Americas Tel 1(800) 272-9959 Fax 1(800) 737-7018 Email support nsc com 2 A critical component is any component of a life support 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