ADC08234BIN

ADC08231 ADC08234 ADC08238 8-Bit 2 ms Serial I O A D Converters with MUX Reference and Track Hold December 1994 ADC08231 ADC08234 ADC08238 8-Bit 2 ms Serial I O A D Converters with MUX Reference and Track Hold General Description The ADC08231 ADC08234 ADC08238 are 8-bit successive approximation A D converters with serial I O and configurable input multiplexers with up to 8 channels The serial I O is configured to comply with the NSC MICROWIRE TM serial data exchange standard for easy interface to the COPSTM family of controllers and can easily interface with standard shift registers or microprocessors Designed for high-speed low-power applications the devices are capable of a fast 2 ms conversion when used with a 4 MHz clock All three devices provide a 2 5V band-gap derived reference with guaranteed performance over temperature A track hold function allows the analog voltage at the positive input to vary during the actual A D conversion The analog inputs can be configured to operate in various combinations of single-ended differential or pseudo-differential modes In addition input voltage spans as small as 1V can be accommodated Features Y Y Y Y Y Y Y Y Serial digital data link requires few I O pins Analog input track hold function 4- or 8-channel input multiplexer options with address logic On-chip 2 5V band-gap reference ( g 2% over temperature guaranteed) No zero or full scale adjustment required TTL CMOS input output compatible 0V to 5V analog input range with single 5V power supply Pin compatible with Industry-Standards ADC0831 4 8 Key Specifications Y Y Y Y Y Y Y Y Applications Y Y Y Y Y Y Y High-speed data acquisition Digitizing automotive sensors Process control monitoring Remote sensing in noisy environments Disk drives Portable instrumentation Test systems Resolution 8 Bits Conversion time (fC e 4 MHz) 2 ms (Max) Power dissipation 20 mW (Max) Single supply 5 VDC ( g 5%) g Total unadjusted error LSB and g 1 LSB g Linearity Error (VREF e 2 5V) LSB No missing codes (over temperature) a 2 5V g 1 5% (Max) On-board Reference ADC08238 Simplified Block Diagram TL H 11015 – 4 TRI-STATE is a registered trademark of National Semiconductor Corporation COPSTM microcontrollers and MICROWIRETM are trademarks of National Semiconductor Corporation C1995 National Semiconductor Corporation TL H 11015 RRD-B30M75 Printed in U S A Ordering Information Industrial (b40 C s TA s a 85 C) ADC08231BIN ADC08231CIN ADC08234BIN ADC08234CIN ADC08234CIMF ADC08238BIN ADC08238CIN ADC08231BIWM ADC08231CIWM ADC08234BIWM ADC08234CIWM ADC08238BIWM ADC08238CIWM Package N08E DIP N14A DIP MTB24 TSSOP N20A DIP M14B SO M14B SO M20B SO Connection Diagrams ADC08238 SO and DIP ADC08234 SO and DIP TL H 11015 – 2 TL H 11015–1 ADC08234 TSSOP ADC08231 DIP TL H 11015–3 ADC08231 SO TL H 11015 – 27 TL H 11015–26 2 Absolute Maximum Ratings (Notes 1 3) Operating Ratings (Notes 2 Temperature Range ADC08231BIN ADC08231CIN ADC08234BIN ADC08234CIN ADC08238BIN ADC08238CIN ADC08231BIWM ADC08231CIWM ADC08234BIWM ADC08238BIWM ADC08234CIWM ADC08238CIWM ADC08234CIMF Supply Voltage (VCC) If Military Aerospace specified devices are required please contact the National Semiconductor Sales Office Distributors for availability and specifications Supply Voltage (VCC) 6 5V b 0 3V to VCC a 0 3V Voltage at Inputs and Outputs g 5 mA Input Current at Any Pin (Note 4) g 20 mA Package Input Current (Note 4) Power Dissipation at TA e 25 C (Note 5) 800 mW ESD Susceptibility (Note 6) 1500V Soldering Information N Package (10 sec ) 260 C TSSOP and SO Package (Note 7) Vapor Phase (60 sec ) 215 C Infrared (15 sec ) 220 C b 65 C to a 150 C Storage Temperature 3) TMIN s TA s TMAX b 40 C s TA s a 85 C 4 5 VDC to 6 3 VDC Electrical Characteristics The following specifications apply for VCC e a 5 VDC VREF e a 2 5 VDC and fCLK e 4 MHz RSource e 50X unless otherwise specified Boldface limits apply for TA e TJ e TMIN to TMAX all other limits TA e TJ e 25 C ADC08231 ADC08234 and ADC08238 with BIN CIN BIWM CIWM or CIMF Suffixes Typical (Note 8) CONVERTER AND MULTIPLEXER CHARACTERISTICS Linearity Error BIN BIWM CIN CIMF CIWM Gain Error BIN BIWM CIN CIMF CIWM Zero Error BIN BIWM CIN CIMF CIWM Total Unadjusted Error BIN BIWM CIN CIMF CIWM Differential Linearity RREF Reference Input Resistance VREF e a 2 5 VDC g g1 Symbol Parameter Conditions Units (Limits) Limits (Note 9) LSB (max) LSB (max) LSB (max) LSB (max) LSB (max) LSB (max) LSB (max) LSB (max) Bits (min) kX kX (min) kX (max) V (max) V (min) VREF e a 2 5 VDC g1 g1 VREF e a 2 5 VDC g1 g1 VREF e a 5 VDC (Note 10) VREF e a 2 5 VDC (Note 11) 35 g1 g1 8 13 60 VIN Analog Input Voltage (Note 12) (VCC a 0 05) (GND b 0 05) 3 Electrical Characteristics (Continued) The following specifications apply for VCC e a 5 VDC VREF e a 2 5 VDC and fCLK e 4 MHz Rsource e 50X unless otherwise specified Boldface limits apply for TA e TJ e TMIN to TMAX all other limits TA e TJ e 25 C ADC08231 ADC08234 and ADC08238 with BIN CIN BIWM CIWM or CIMF Suffixes Typical (Note 8) CONVERTER AND MULTIPLEXER CHARACTERISTICS (Continued) DC Common-Mode Error Power Supply Sensitivity On Channel Leakage Current (Note 13) VREF e a 2 5 VDC VCC e a 5V g 5% VREF e a 2 5 VDC On Channel e 5V Off Channel e 0V On Channel e 0V Off Channel e 5V Off Channel Leakage Current (Note 13) On Channel e 5V Off Channel e 0V On Channel e 0V Off Channel e 5V DYNAMIC CHARACTERISTICS (see Typical Converter Performance Characteristics) S NaD Signal-to(Noise a Distortion) Ratio VREF e a 5V Sample Rate e 286 kHz VIN e a 5 Vp-p fIN e 10 kHz fIN e 50 kHz fIN e 100 kHz DIGITAL AND DC CHARACTERISTICS VIN(1) VIN(0) IIN(1) IIN(0) VOUT(1) Logical ‘‘1’’ Input Voltage Logical ‘‘0’’ Input Voltage Logical ‘‘1’’ Input Current Logical ‘‘0’’ Input Current Logical ‘‘1’’ Output Voltage VCC e 5 25V VCC e 4 75V VIN e 5 0V VIN e 0V VCC e 4 75V IOUT e b360 mA IOUT e b10 mA VCC e 4 75V IOUT e 1 6 mA VOUT e 0V VOUT e 5V VOUT e 0V VOUT e VCC CS e HIGH 30 60 mA (max) mA (max) 20 08 1 b1 g g Symbol Parameter Conditions Units (Limits) Limits (Note 9) LSB (max) LSB (max) mA (max) mA (max) mA (max) mA (max) 02 1 b0 2 b1 b0 2 b1 02 1 48 35 48 00 47 40 dB dB dB V (min) V (max) mA (max) mA (max) V (min) V (min) V (max) mA (max) mA (max) mA (min) mA (min) 24 45 04 b3 0 VOUT(0) IOUT ISOURCE ISINK ICC Logical ‘‘0’’ Output Voltage TRI-STATE Output Current Output Source Current Output Sink Current Supply Current ADC08234 ADC08238 ADC08231 (Note 16) 30 b6 5 80 4 Electrical Characteristics (Continued) The following specifications apply for VCC e a 5 VDC and fCLK e 4 MHz unless otherwise specified Boldface limits apply for TA e TJ e TMIN to TMAX all other limits TA e TJ e 25 C ADC08231 ADC08234 and ADC08238 with BIN CIN BIWM CIWM or CIMF Suffixes Typical (Note 8) REFERENCE CHARACTERISTICS VREFOUT Output Voltage BIN BIJ BIWM CIN CIJ CIWM CMJ DVREF DT DVREF DIL Temperature Coefficient Load Regulation (Note 17) Sourcing (0 s IL s a 4 mA) ADC08234 ADC08238 Sourcing (0 s IL s a 2 mA) ADC08231 Sinking (b1 s IL s 0 mA) ADC08234 ADC08238 Sinking (b1 s IL s 0 mA) ADC08231 Line Regulation ISC Short Circuit Current 4 75V s VCC s 5 25V VREF e 0V ADC08234 ADC08238 VREF e 0V ADC08231 TSU DVREF Dt Start-Up Time Long Term Stability VCC 0V x 5V CL e 100 mF 25 g 2% Symbol Parameter Conditions Units (Limits) Limits (Note 9) 2 5 g 1 5% V 2 5 g 3 0% ppm C 25 g 3 5% 40 0 003 01 0 003 01 % mA (max) 02 05 02 05 05 6 mV (max) 8 25 mA (max) 8 20 200 25 ms ppm 1 kHr 5 Electrical Characteristics (Continued) The following specifications apply for VCC e a 5 VDC VREF e a 2 5 VDC and tr e tf e 20 ns unless otherwise specified Boldface limits apply for TA e TJ e TMIN to TMAX all other limits TA e TJ e 25 C Symbol fCLK Parameter Clock Frequency Clock Duty Cycle (Note 14) TC tCA tSELECT tSET-UP tHOLD tpd1 tpd0 Conversion Time (Not Including MUX Addressing Time) Acquisition Time CLK High while CS is High CS Falling Edge or Data Input Valid to CLK Rising Edge Data Input Valid after CLK Rising Edge CLK Falling Edge to Output Data Valid (Note 15) TRI-STATE Delay from Rising Edge of CS to Data Output and SARS Hi-Z Capacitance of Logic Inputs Capacitance of Logic Outputs CL e 100 pF Data MSB First Data LSB First CL e 10 pF RL e 10 kX (see TRI-STATE Test Circuits) CL e 100 pF RL e 2 kX CIN COUT 5 5 50 180 50 25 20 fCLK e 4 MHz Conditions Typical (Note 8) 10 4 40 60 8 2 1 Limits (Note 9) Units (Limits) kHz (min) MHz (max) % (min) % (max) 1 fCLK (max) ms (max) 1 fCLK(max) ns ns (min) ns (min) 250 200 ns (max) ns (max) ns ns (max) pF pF t1H t0H Note 1 Absolute Maximum Ratings indicate limits beyond which damage to the device may occur Note 2 Operating Ratings indicate conditions for which the device is functional These ratings do not guarantee specific performance limits For guaranteed specifications and test conditions see the Electrical Characteristics The guaranteed specifications apply only for the test conditions listed Some performance characteristics may degrade when the device is not operated under the listed test conditions Note 3 All voltages are measured with respect to AGND e DGND e 0 VDC unless otherwise specified Note 4 When the input voltage (VIN) at any pin exceeds the power supplies (VIN k (AGND or DGND) or VIN l AVCC ) the current at that pin should be limited to 5 mA The 20 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 5 mA to four pins Note 5 The maximum power dissipation must be derated at elevated temperatures and is dictated by TJMAX iJA and the ambient temperature TA The maximum allowable power dissipation at any temperature is PD e (TJMAX b TA) iJA or the number given in the Absolute Maximum Ratings whichever is lower For devices with suffixes BIN CIN BIJ CIJ BIWM and CIWM TJMAX e 125 C For devices with suffix CMJ TJMAX e 150 C The typical thermal resistances (iJA) of these parts when board mounted follow ADC08231 with BIN and CIN suffixes 120 C W ADC08234 with BIN and CIN suffixes 95 C W ADC08234 with CIMF suffix 167 C W ADC08238 with BIN and CIN suffixes 80 C W ADC08231 with BIWM and CIWM suffixes 140 C W ADC08234 with BIWM and CIWM suffixes 140 C W ADC08238 with BIWM and CIWM suffixes 91 C W Note 6 Human body model 100 pF capacitor discharged through a 1 5 kX resistor Note 7 See AN450 ‘‘Surface Mounting Methods and Their Effect on Product Reliability’’ or Linear Data Book section ‘‘Surface Mount’’ for other methods of soldering surface mount devices Note 8 Typicals are at TJ e 25 C and represent the most likely parametric norm Note 9 Guaranteed to National’s AOQL (Average Outgoing Quality Level) Note 10 Total unadjusted error includes zero full-scale linearity and multiplexer error Total unadjusted error with VREF e a 5V only applies to the ADC08234 and ADC08238 See Note 16 Note 11 Cannot be tested for the ADC08231 Note 12 For VIN(b) t VIN( a ) the digital code will be 0000 0000 Two on-chip diodes are tied to each analog input (see Block Diagram) which will forward-conduct for analog input voltages one diode drop below ground or one diode drop greater than VCC supply During testing at low VCC levels (e g 4 5V) high level analog inputs (e g 5V) can cause an input diode to conduct especially at elevated temperatures This will cause errors for analog inputs near full-scale The specification allows 50 mV forward bias of either diode this means that as long as the analog VIN does not exceed the supply voltage by more than 50 mV the output code will be correct Exceeding this range on an unselected channel will corrupt the reading of a selected channel Achievement of an absolute 0 VDC to 5 VDC input voltage range will therefore require a minimum supply voltage of 4 950 VDC over temperature variations initial tolerance and loading Note 13 Channel leakage current is measured after a single-ended channel is selected and the clock is turned off For off channel leakage current the following two cases are considered one with the selected channel tied high (5 VDC) and the remaining off channels tied low (0 VDC) total current flow through the off channels is measured two with the selected channel tied low and the off channels tied high total current flow through the off channels is again measured The two cases considered for determining on channel leakage current are the same except total current flow through the selected channel is measured Note 14 A 40% to 60% duty cycle range insures proper operation at all clock frequencies In the case that an available clock has a duty cycle outside of these limits the minimum time the clock is high or low must be at least 120 ns The maximum time the clock can be high or low is 100 ms Note 15 Since data MSB first is the output of the comparator used in the successive approximation loop an additional delay is built in (see Block Diagram) to allow for comparator response time Note 16 For the ADC08231 VREFIN is internally tied to the on chip 2 5V band-gap reference output therefore the supply current is larger because it includes the reference current (700 mA typical 2 mA maximum) Note 17 Load regulation test conditions and specifications for the ADC08231 differ from those of the ADC08234 and ADC08238 because the ADC08231 has the on-board reference as a permanent load 6 Typical Performance Characteristics Linearity Error vs Reference Voltage Linearity Error vs Temperature Linearity Error vs Clock Frequency Power Supply Current vs Temperature (ADC08238 ADC08234) Output Current vs Temperature Power Supply Current vs Clock Frequency Note For ADC08231 add IREF (Note 16) TL H 11015 – 5 Spectral Response with 10 kHz Sine Wave Input Spectral Response with 50 kHz Sine Wave Input Spectral Response with 100 kHz Sine Wave Input Signal-to-Noise a Distortion Ratio vs Input Frequency TL H 11015 – 6 7 Typical Reference Performance Characteristics Load Regulation Line Regulation (3 Typical Parts) Output Drift vs Temperature (3 Typical Parts) Available Output Current vs Supply Voltage TL H 11015 – 7 8 TRI-STATE Test Circuits and Waveforms t1H t1H t0H t0H TL H 11015 – 8 TL H 11015 – 9 Timing Diagrams Data Input Timing TL H 11015 – 10 To reset these devices CLK and CS must be simultaneously high for a period of tSELECT or greater Data Output Timing TL H 11015 – 11 ADC08231 Start Conversion Timing TL H 11015 – 12 9 Timing Diagrams (Continued) ADC08231 Timing TL H 11015 – 13 LSB first output not available on ADC08231 LSB information is maintained for remainder of clock periods until CS goes high To reset the ADC08231 CLK and CS must be simultaneusly high for a period of tSELECT or greater The ADC08231 also has one extra clock period for sampling the analog signal (tca) Otherwise it is compatible with the ADC0831 ADC08234 Timing TL H 11015 – 14 To reset the ADC08234 CLK and CS must be simultaneously high for a period of tSELECT or greater The ADC08234 also has one extra clock period for sampling the analog signal (tca) Otherwise it is compatible with the ADC0834 10 Timing Diagrams (Continued) ADC08238 Timing 11 TL H 11015 – 15 Make sure clock edge 19 clocks in the LSB before SE is taken low To reset the ADC08238 CLK and CS must be simultaneously high for a period of tSELECT or greater The ADC08238 also has one extra clock period for sampling the analog signal (tca) Otherwise it is compatible with the ADC0838 ADC08238 Functional Block Diagram 12 TL H 11015 – 16 Some of these functions pins are not available with other options Note 1 For the ADC08234 the ‘‘SEL 1’’ Flip-Flop is bypassed For the ADC08231 VREFOUT and VREFIN are internally tied together Functional Description 1 0 MULTIPLEXER ADDRESSING The design of these converters utilizes a comparator structure with built-in sample-and-hold which provides for a differential analog input to be converted by a successiveapproximation routine The actual voltage converted is always the difference between an assigned ‘‘ a ’’ input terminal and a ‘‘b’’ input terminal The polarity of each input terminal of the pair indicates which line the converter expects to be the most positive If the assigned ‘‘ a ’’ input voltage is less than the ‘‘b’’ input voltage the converter responds with an all zeros output code A unique input multiplexing scheme has been utilized to provide multiple analog channels with software-configurable single-ended differential or pseudo-differential (which will convert the difference between the voltage at any analog input and a common terminal) operation The analog signal conditioning required in transducer-based data acquisition systems is significantly simplified with this type of input flexibility One converter package can now handle ground referenced inputs and true differential inputs as well as signals with some arbitrary reference voltage A particular input configuration is assigned during the MUX addressing sequence prior to the start of a conversion The MUX address selects which of the analog inputs are to be enabled and whether this input is single-ended or differential Differential inputs are restricted to adjacent channel pairs For example channel 0 and channel 1 may be selected as a differential pair but channel 0 or 1 cannot act differentially with any other channel In addition to selecting differential mode the polarity may also be selected Channel 0 may be selected as the positive input and channel 1 as the negative input or vice versa This programmability is best illustrated by the MUX addressing codes shown in the following tables for the various product options The MUX address is shifted into the converter via the DI line Because the ADC08231 contains only one differential input channel with a fixed polarity assignment it does not require addressing The common input line (COM) on the ADC08238 can be used as a pseudo-differential input In this mode the voltage on this pin is treated as the ‘‘ b’’ input for any of the other input channels This voltage does not have to be analog ground it can be any reference potential which is common to all of the inputs This feature is most useful in single-supply applications where the analog circuitry may be biased up to a potential other than ground and the output signals are all referred to this potential TABLE I Multiplexer Package Options Part Number ADC08231 ADC08234 ADC08238 Number of Analog Channels Single-Ended 1 4 8 Differential 1 2 4 Number of Package Pins 8 14 20 TABLE II MUX Addressing ADC08238 Single-Ended MUX Mode MUX Address START 1 1 1 1 1 1 1 1 SGL DIF 1 1 1 1 1 1 1 1 ODD SIGN 0 0 0 0 1 1 1 1 SELECT 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 a a a a a a a a b b b b b b b b Analog Single-Ended Channel 0 1 2 3 4 5 6 7 COM 13 Functional Description (Continued) TABLE II MUX Addressing ADC08238 (Continued) Differential MUX Mode MUX Address START 1 1 1 1 1 1 1 1 SGL DIF 0 0 0 0 0 0 0 0 ODD SIGN 0 0 0 0 1 1 1 1 SELECT 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 b a b a b a b a Analog Differential Channel-Pair 0 0 a 1 1 b a b a 2 3 4 5 6 3 7 2 b a b TABLE III MUX Addressing ADC08234 Single-Ended MUX Mode MUX Address START 1 1 1 1 SGL DIF 1 1 1 1 ODD SIGN 0 0 1 1 SELECT 1 0 1 0 1 a a COM is internally tied to AGND Channel 0 a a 1 2 3 Differential MUX Mode MUX Address START 1 1 1 1 SGL DIF 0 0 0 0 ODD SIGN 0 0 1 1 SELECT 1 0 1 0 1 b a b a a b a b Channel 0 1 2 3 14 Functional Description (Continued) Since the input configuration is under software control it can be modified as required before each conversion A channel can be treated as a single-ended ground referenced input for one conversion then it can be reconfigured as part of a differential channel for another conversion Figure 1 illustrates the input flexibility which can be achieved The analog input voltages for each channel can range from 50mV below ground to 50mV above VCC (typically 5V) without degrading conversion accuracy 2 0 THE DIGITAL INTERFACE A most important characteristic of these converters is their serial data link with the controlling processor Using a serial communication format offers two very significant system improvements it allows many functions to be included in a small package and it can eliminate the transmission of low level analog signals by locating the converter right at the analog sensor transmitting highly noise immune digital data back to the host processor 8 Single-Ended To understand the operation of these converters it is best to refer to the Timing Diagrams and Functional Block Diagram and to follow a complete conversion sequence For clarity a separate timing diagram is shown for each device 1 A conversion is initiated by pulling the CS (chip select) line low This line must be held low for the entire conversion The converter is now waiting for a start bit and its MUX assignment word 2 On each rising edge of the clock the status of the data in (DI) line is clocked into the MUX address shift register The start bit is the first logic ‘‘1’’ that appears on this line (all leading zeros are ignored) Following the start bit the converter expects the next 2 to 4 bits to be the MUX assignment word 8 Pseudo-Differential 4 Differential Mixed Mode TL H 11015 – 17 FIGURE 1 Analog Input Multiplexer Options for the ADC08238 15 Functional Description (Continued) 3 When the start bit has been shifted into the start location of the MUX register the input channel has been assigned and a conversion is about to begin An interval of 1 clock periods is automatically inserted to allow for sampling the analog input The SARS line goes high at the end of this time to signal that a conversion is now in progress and the DI line is disabled (it no longer accepts data) 4 The data out (DO) line now comes out of TRI-STATE and provides a leading zero 5 During the conversion the output of the SAR comparator indicates whether the analog input is greater than (high) or less than (low) a series of successive voltages generated internally from a ratioed capacitor array (first 5 bits) and a resistor ladder (last 3 bits) After each comparison the comparator’s output is shipped to the DO line on the falling edge of CLK This data is the result of the conversion being shifted out (with the MSB first) and can be read by the processor immediately 6 After 8 clock periods the conversion is completed The SARS line returns low to indicate this clock cycle later 7 The stored data in the successive approximation register is loaded into an internal shift register If the programmer prefers the data can be provided in an LSB first format this makes use of the shift enable (SE) control line On the ADC08238 the SE line is brought out and if held high the value of the LSB remains valid on the DO line When SE is forced low the data is clocked out LSB first On devices which do not include the SE control line the data LSB first is automatically shifted out the DO line after the MSB first data stream The DO line then goes low and stays low until CS is returned high The ADC08231 is an exception in that its data is only output in MSB first format 8 All internal registers are cleared when the CS line is high and the tSELECT requirement is met See Data Input Timing under Timing Diagrams If another conversion is desired CS must make a high to low transition followed by address information The DI and DO lines can be tied together and controlled through a bidirectional processor I O bit with one wire This is possible because the DI input is only ‘‘looked-at’’ during the MUX addressing interval while the DO line is still in a high impedance state 3 0 REFERENCE CONSIDERATIONS The VREFIN pin on these converters is the top of a resistor divider string and capacitor array used for the successive approximation conversion The voltage applied to this reference input defines the voltage span of the analog input (the difference between VIN(MAX) and VIN(MIN) over which the 256 possible output codes apply) The reference source must be capable of driving the reference input resistance which can be as low as 1 3 kX For absolute accuracy where the analog input varies between specific voltage limits the reference input must be biased with a stable voltage source The ADC08234 and the ADC08238 provide the output of a 2 5V band-gap reference at VREFOUT This voltage does not vary appreciably with temperature supply voltage or load current (see Reference Characteristics in the Electrical Characteristics tables) and can be tied directly to VREFIN for an analog input span of 0V to 2 5V This output can also be used to bias external circuits and can therefore be used as the reference in ratiometric applications Bypassing VREFOUT with a 100 mF capacitor is recommended For the ADC08231 the output of the on-board reference is internally tied to the reference input Consequently the analog input span for this device is set at 0V to 2 5V The pin VREFC is provided for bypassing purposes and biasing external circuits as suggested above The maximum value of the reference is limited to the VCC supply voltage The minimum value however can be quite small (see Typical Performance Characteristics) to allow direct conversions of transducer outputs providing less than a 5V output span Particular care must be taken with regard to noise pickup circuit layout and system error voltage sources when operating with a reduced span due to the increased sensitivity of the converter (1 LSB equals VREF 256) TL H 11015 – 19 TL H 11015–18 a) Ratiometric FIGURE 2 Reference Examples 16 b) Absolute Functional Description (Continued) 4 0 THE ANALOG INPUTS The most important feature of these converters is that they can be located right at the analog signal source and through just a few wires can communicate with a controlling processor with a highly noise immune serial bit stream This in itself greatly minimizes circuitry to maintain analog signal accuracy which otherwise is most susceptible to noise pickup However a few words are in order with regard to the analog inputs should the input be noisy to begin with or possibly riding on a large common-mode voltage The differential input of these converters actually reduces the effects of common-mode input noise a signal common to both selected ‘‘ a ’’ and ‘‘b’’ inputs for a conversion (60 Hz is most typical) The time interval between sampling the ‘‘ a ’’ input and then the ‘‘b’’ input is of a clock period The change in the common-mode voltage during this short time interval can cause conversion errors For a sinusoidal common-mode signal this error is Verror(max) e VPEAK(2qfCM) The zero error of the A D converter relates to the location of the first riser of the transfer function and can be measured by grounding the VIN (b) input and applying a small magnitude positive voltage to the VIN ( a ) input Zero error is the difference between the actual DC input voltage which is necessary to just cause an output digital code transition from 0000 0000 to 0000 0001 and the ideal LSB value ( LSB e 9 8mV for VREF e 5 000VDC) 5 2 Full Scale A full-scale adjustment can be made by applying a differential input voltage which is 1 LSB down from the desired analog full-scale voltage range and then adjusting the magnitude of the VREFIN input for a digital output code which is just changing from 1111 1110 to 1111 1111 (See figure entitled ‘‘Span Adjust 0V s VIN s 3V’’) This is possible only with the ADC08234 and ADC08238 (The reference is internally connected to VREFIN of the ADC08231) 5 3 Adjusting for an Arbitrary Analog Input Voltage Range If the analog zero voltage of the A D is shifted away from ground (for example to accommodate an analog input signal which does not go to ground) this new zero reference should be properly adjusted first A VIN ( a ) voltage which equals this desired zero reference plus LSB (where the LSB is calculated for the desired analog span using 1 LSB e analog span 256) is applied to selected ‘‘ a ’’ input and the zero reference voltage at the corresponding ‘‘ b’’ input should then be adjusted to just obtain the 00HEX to 01HEX code transition The full-scale adjustment should be made with the proper VIN (b) voltage applied by forcing a voltage to the VIN ( a ) input which is given by VIN ( a ) fs adj e VMAX b 1 5 (VMAX b VMIN) 256 where fCM is the frequency of the common-mode signal VPEAK is its peak voltage value and fCLK is the A D clock frequency For a 60Hz common-mode signal to generate a LSB error ( 5mV) with the converter running at 250kHz its peak value would have to be 6 63V which would be larger than allowed as it exceeds the maximum analog input limits Source resistance limitation is important with regard to the DC leakage currents of the input multiplexer While operating near or at maximum speed bypass capacitors should not be used if the source resistance is greater than 1kX The worst-case leakage current of g 1mA over temperature will create a 1mV input error with a 1kX source resistance An op amp RC active low pass filter can provide both impedance buffering and noise filtering should a high impedance signal source be required 5 0 OPTIONAL ADJUSTMENTS 5 1 Zero Error The zero of the A D does not require adjustment If the minimum analog input voltage value VIN(MIN) is not ground a zero offset can be done The converter can be made to output 0000 0000 digital code for this minimum input voltage by biasing any VIN (b) input at this VIN(MIN) value This utilizes the differential mode operation of the A D f J 05 CLK where VMAX e the high end of the analog input range and VMIN e the low end (the offset zero) of the analog range (Both are ground referenced ) The VREFIN (or VCC) voltage is then adjusted to provide a code change from FEHEX to FFHEX This completes the adjustment procedure ( 17 Applications A ‘‘Stand-Alone’’ Hook-Up for ADC08238 Evaluation Pinouts shown for ADC08238 For all other products tie to pin functions as shown Low-Cost Remote Temperature Sensor TL H 11015 – 21 18 Applications (Continued) Protecting the Input Diodes are 1N914 TL H 11015 – 22 Operating with Ratiometric Transducers VIN( b ) e 0 15 VREF 15% of VREF s VXDR s 85% of VREF TL H 11015 – 23 Span Adjust 0V s VIN s 3V TL H 11015 – 24 19 Applications (Continued) Zero-Shift and Span Adjust 2V s VIN s 5V TL H 11015 – 25 20 Physical Dimensions inches (millimeters) Order Number ADC08231BIWM ADC08231CIWM ADC08234BIWM or ADC08234CIWM NS Package Number M14B Order Number ADC08238BIWM or ADC08238CIWM NS Package Number M20B 21 Physical Dimensions inches (millimeters) (Continued) TSSOP Molded Package Order Number ADC08234CIMF NS Package Number MTB24 Order Number ADC08231BIN or ADC08231CIN NS Package Number N08E 22 Physical Dimensions inches (millimeters) (Continued) Molded Dual-In-Line Package (N) Order Number ADC08234BIN or ADC08234CIN NS Package Number N14A 23 ADC08231 ADC08234 ADC08238 8-Bit 2 ms Serial I O A D Converters with MUX Reference and Track Hold Physical Dimensions inches (millimeters) (Continued) Molded Dual-In-Line Package (N) Order Number ADC08238CIN or ADC08238BIN NS Package Number N20A LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION As used herein 1 Life support devices or systems are devices or systems which (a) are intended for surgical implant into the body or (b) support or sustain life and whose failure to perform when properly used in accordance with instructions for use provided in the labeling can be reasonably expected to result in a significant injury to the user National Semiconductor Corporation 2900 Semiconductor Drive P O Box 58090 Santa Clara CA 95052-8090 Tel 1(800) 272-9959 TWX (910) 339-9240 National Semiconductor GmbH Livry-Gargan-Str 10 D-82256 F4urstenfeldbruck Germany Tel (81-41) 35-0 Telex 527649 Fax (81-41) 35-1 National Semiconductor Japan Ltd Sumitomo Chemical Engineering Center Bldg 7F 1-7-1 Nakase Mihama-Ku Chiba-City Ciba Prefecture 261 Tel (043) 299-2300 Fax (043) 299-2500 2 A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system or to affect its safety or effectiveness National Semiconductor Hong Kong Ltd 13th Floor Straight Block Ocean Centre 5 Canton Rd Tsimshatsui Kowloon Hong Kong Tel (852) 2737-1600 Fax (852) 2736-9960 National Semiconductores Do Brazil Ltda Rue Deputado Lacorda Franco 120-3A Sao Paulo-SP Brazil 05418-000 Tel (55-11) 212-5066 Telex 391-1131931 NSBR BR Fax (55-11) 212-1181 National Semiconductor (Australia) Pty Ltd Building 16 Business Park Drive Monash Business Park Nottinghill Melbourne Victoria 3168 Australia Tel (3) 558-9999 Fax (3) 558-9998 National does not assume any responsibility for use of any circuitry described no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications