ADC08500CIYB

ADC08500 High Performance, Low Power 8-Bit, 500 MSPS A/D Converter April 21, 2009 ADC08500 High Performance, Low Power 8-Bit, 500 MSPS A/D Converter General Description The ADC08500 is a low power, high performance CMOS analog-to-digital converter that digitizes signals to 8 bits resolution at sampling rates up to 500 MSPS. Consuming a typical 0.8 Watts at 500 MSPS from a single 1.9 Volt supply, this device is guaranteed to have no missing codes over the full operating temperature range. The unique folding and interpolating architecture, the fully differential comparator design, the innovative design of the internal sample-and-hold amplifier and the self-calibration scheme enable a very flat response of all dynamic parameters beyond Nyquist, producing a high 7.5 ENOB with a 250 MHz input signal and a 500 MHz sample rate while providing a 10-18 B.E.R. Output formatting is offset binary and the LVDS digital outputs are compatible with IEEE 1596.3-1996, with the exception of an adjustable common mode voltage between 0.8V and 1.2V. The converter has a 1:2 demultiplexer that feeds two LVDS buses and reduces the output data rate on each bus to half the sampling rate. The converter typically consumes less than 3.5 mW in the Power Down Mode and is available in a 128-lead, thermally enhanced exposed pad LQFP and operates over the Industrial (-40°C ≤ TA ≤ +85°C) temperature range. Features ■ ■ ■ ■ ■ ■ ■ ■ Internal Sample-and-Hold Single +1.9V ±0.1V Operation Choice of SDR or DDR output clocking Multiple ADC Synchronization Capability Guaranteed No Missing Codes Serial Interface for Extended Control Fine Adjustment of Input Full-Scale Range and Offset Duty Cycle Corrected Sample Clock Key Specifications ■ ■ ■ ■ ■ ■ ■ Resolution Max Conversion Rate Bit Error Rate ENOB @ 250 MHz Input DNL Power Consumption — Operating — Power Down Mode 8 Bits 500 MSPS (min) 10-18 (typ) 7.5 Bits (typ) ±0.15 LSB (typ) 0.8 W (typ) 3.5 mW (typ) Applications ■ ■ ■ ■ ■ Direct RF Down Conversion Digital Oscilloscopes Satellite Set-top boxes Communications Systems Test Instrumentation Block Diagram 20206453 © 2009 National Semiconductor Corporation 202064 www.national.com ADC08500 Ordering Information Industrial Temperature Range (-40°C < TA < +85°C) ADC08500CIYB ADC08500DEV NS Package 128-Pin Exposed Pad LQFP Development Board Pin Configuration 20206401 * Exposed pad on back of package must be soldered to ground plane to ensure rated performance. www.national.com 2 ADC08500 Pin Descriptions and Equivalent Circuits Pin Functions Pin No. Symbol Equivalent Circuit Description Output Voltage Amplitude and Serial Interface Clock. Tie this pin high for normal differential DCLK and data amplitude. Ground this pin for a reduced differential output amplitude and reduced power consumption. See1.1.6 The LVDS Outputs. When the extended control mode is enabled, this pin functions as the SCLK input which clocks in the serial data. See 1.2 NORMAL/EXTENDED CONTROL for details on the extended control mode. See 1.3 THE SERIAL INTERFACE for description of the serial interface. 3 OutV / SCLK 4 OutEdge / DDR / SDATA DCLK Edge Select, Double Data Rate Enable and Serial Data Input. This input sets the output edge of DCLK+ at which the output data transitions. When this pin is floating or connected to 1/2 the supply voltage, DDR clocking is enabled. See1.1.5.2 Double Data Rate. When the extended control mode is enabled, this pin functions as the SDATA input. See 1.2 NORMAL/EXTENDED CONTROL for details on the extended control mode. See 1.3 THE SERIAL INTERFACE for description of the serial interface. DCLK Reset. A positive pulse on this pin is used to reset and synchronize the DCLK outs of multiple converters. See 1.5 MULTIPLE ADC SYNCHRONIZATION for detailed description. Power Down Pin. A logic high on the PD pin puts the entire device into the Power Down Mode. Calibration Cycle Initiate. A minimum tCAL_L input clock cycles logic low followed by a minimum of tCAL_H input clock cycles high on this pin initiates the self calibration sequence. See 2.4.2 Self Calibration for an overview of self-calibration and 2.4.2.2 On-Command Calibration for a description of oncommand calibration. Full Scale Range Select and Extended Control Enable. In nonextended control mode, a logic low on this pin sets the fullscale differential input range to a reduced VIN input level . A logic high on this pin sets the full-scale differential input range to a higher VIN input level. See Converter Electrical Characteristics. To enable the extended control mode, whereby the serial interface and control registers are employed, allow this pin to float or connect it to a voltage equal to VA/2. See 1.2 NORMAL/EXTENDED CONTROL for information on the extended control mode. 15 DCLK_RST 26 PD 30 CAL 14 FSR/ECE 3 www.national.com ADC08500 Pin Functions Pin No. Symbol Equivalent Circuit Description 127 CalDly / SCS Calibration Delay and Serial Interface Chip Select. With a logic high or low on pin 14, this pin functions as Calibration Delay and sets the number of clock cycles after power up before calibration begins. See 1.1.1 Self-Calibration. With pin 14 floating, this pin acts as the enable pin for the serial interface input and the CalDly value becomes "0" (short delay with no provision for a long power-up calibration delay). 18 19 CLK+ CLK- LVDS Clock input pins for the ADC. The differential clock signal must be a.c. coupled to these pins. The input signal is sampled on the falling edge of CLK+. See1.1.2 Acquiring the Input for a description of acquiring the input and 2.3 THE CLOCK INPUTS for an overview of the clock inputs. 11 10 VIN+ VIN− Analog signal inputs to the ADC. The differential full-scale input range of this input is programmable using the FSR pin 14 in normal mode and the Input Full-Scale Voltage Adjust register in the extended control mode. Refer to the VIN specification in the Converter Electrical Characteristics for the full-scale input range in the normal mode. Refer to 1.4 REGISTER DESCRIPTION for the full-scale input range in the extended control mode. 7 VCMO Common Mode Voltage. This pin is the common mode output in d.c. coupling mode and also serves as the a.c. coupling mode select pin. When d.c. coupling is used, the voltage output at this pin is required to be the common mode input voltage at VIN+ and VIN− when d.c. coupling is used. This pin should be grounded when a.c. coupling is used at the analog inputs. This pin is capable of sourcing or sinking 100 μA. See 2.2 THE ANALOG INPUT. Bandgap output voltage capable of 100 μA source/sink. 31   VBG   126 CalRun Calibration Running indication. This pin is at a logic high when calibration is running. www.national.com 4 ADC08500 Pin Functions Pin No. Symbol Equivalent Circuit Description 32 REXT External bias resistor connection. Nominal value is 3.3 kOhms (±0.1%) to ground. See 1.1.1 Self-Calibration. 34 35 83 84 85 86 89 90 91 92 93 94 95 96 100 101 102 103 104 105 106 107 111 112 113 114 115 116 117 118 122 123 124 125 Tdiode_P Tdiode_N D7D7+ D6D6+ D5D5+ D4D4+ D3D3+ D2D2+ D1D1+ D0D0+ Dd7Dd7+ Dd6Dd6+ Dd5Dd5+ Dd4Dd4+ Dd3Dd3+ Dd2Dd2+ Dd1Dd1+ Dd0Dd0+ Temperature Diode Positive (Anode) and Negative (Cathode). These pins may be used for die temperature measurements, however no specified accuracy is implied or guaranteed. See 2.6.2 Thermal Management. Input channel LVDS Data Outputs that are not delayed in the output demultiplexer. Compared with the Dd outputs, these outputs represent the later time samples. These outputs should always be terminated with a 100Ω differential resistor. Input channel LVDS Data Outputs that are delayed by one CLK cycle in the output demultiplexer. Compared with the D outputs, these outputs represent the earlier time sample. These outputs should always be terminated with a 100Ω differential resistor. 5 www.national.com ADC08500 Pin Functions Pin No. Symbol Equivalent Circuit Description Out Of Range output. A differential high at these pins indicates that the differential input is out of range (outside the range ±VIN/2 as programmed by the FSR pin in non-extended control mode or the Input Full-Scale Voltage Adjust register setting in the extended control mode). Differential Clock outputs used to latch the output data. Delayed and non-delayed data outputs are supplied synchronous to this signal. This signal is at 1/2 the input clock rate in SDR mode and at 1/4 the input clock rate in the DDR mode. The DCLK outputs are not active during a calibration cycle, therefore this is not recommended as a system clock. 79 80 OR+ OR- 82 81 DCLK+ DCLK- 2, 5, 8, 13, 16, 17, 20, 25, 28, 33, 128 40, 51 ,62, 73, 88, 99, 110, 121 1, 6, 9, 12, 21, 24, 27, 41 42, 53, 64, 74, 87, 97, 108, 119 22, 23, 29, 36–39, 43–50, 52, 54–61, 63, 65–72, 75–78, 98, 109, 120 VA Analog power supply pins. Bypass these pins to ground. VDR Output Driver power supply pins. Bypass these pins to DR GND. GND Ground return for VA. DR GND Ground return for VDR. NC No Connection. Make no connection to these pins. www.national.com 6 ADC08500 Absolute Maximum Ratings (Notes 1, 2) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage (VA, VDR) Supply Difference VDR - VA Voltage on Any Input Pin (Except VIN+, VIN- ) Voltage on VIN+, VIN(Maintaining Common Mode) Ground Difference |GND - DR GND| Input Current at Any Pin (Note 3) Package Input Current (Note 3) Power Dissipation at TA = 85°C ESD Susceptibility (Note 4) Human Body Model Machine Model Storage Temperature 2.2V 0V to 100 mV −0.15V to (VA +0.15V) -0.15V to 2.5V 0V to 100 mV ±25 mA ±50 mA 2.0 W   2500V 250V −65°C to +150°C Operating Ratings Ambient Temperature Range (Notes 1, 2) −40°C ≤ TA ≤ +85°C +1.8V to +2.0V +1.8V to VA VCMO ±50 mV 0V to 2.15V (100% duty cycle) 0V to 2.5V (10% duty cycle) 0V 0V to VA 0.4VP-P to 2.0VP-P θJC (Top of Package) Supply Voltage (VA) Driver Supply Voltage (VDR) Analog Input Common Mode Voltage VIN+, VIN- Voltage Range (Maintaining Common Mode) Ground Difference (|GND - DR GND|) CLK Pins Voltage Range Differential CLK Amplitude Package Thermal Resistance Package 128-Lead Exposed Pad LQFP θJA 25°C / W θJ-PAD (Thermal Pad) 10°C / W 2.8°C / W Soldering process must comply with National Semiconductor's Reflow Temperature Profile specifications. Refer to www.national.com/packaging. (Note 5) The following specifications apply after calibration for VA = VDR = +1.9VDC, OutV = 1.9V, VIN FSR (a.c. coupled) = differential 870 mVP-P, CL = 10 pF, Differential, a.c. coupled Sinewave Input Clock, fCLK = 500 MHz at 0.5VP-P with 50% duty cycle, VBG = Floating, Non-Extended Control Mode, SDR Mode, REXT = 3300Ω ±0.1%, Analog Signal Source Impedance = 100Ω Differential. Boldface limits apply for TA = TMIN to TMAX. All other limits TA = 25°C, unless otherwise noted. (Notes 6, 7) Symbol Parameter Conditions Typical (Note 8) Limits (Note 8) Units (Limits) Converter Electrical Characteristics STATIC CONVERTER CHARACTERISTICS INL DNL Integral Non-Linearity Differential Non-Linearity Resolution with No Missing Codes VOFF Offset Error Extended Control Mode -0.5 ±45 ±25 ±25 Extended Control Mode ±20 1.7 10-18 d.c. to 500 MHz fIN = 50 MHz, VIN = FSR − 0.5 dB ENOB Effective Number of Bits fIN = 124 MHz, VIN = FSR − 0.5 dB fIN = 248 MHz, VIN = FSR − 0.5 dB fIN = 50 MHz, VIN = FSR − 0.5 dB SINAD Signal-to-Noise Plus Distortion Ratio fIN = 124 MHz, VIN = FSR − 0.5 dB fIN = 248 MHz, VIN = FSR − 0.5 dB ±0.5 7.5 7.5 7.5 47 47 47 44.5 44.5 7.1 7.1 ±15 DC Coupled, 1MHz Sine Wave OverRanged DC Coupled, 1MHz Sine Wave Over Ranged ±0.3 ±0.15 ±0.9 ±0.6 8 −1.5 0.5 LSB (max) LSB (max) Bits LSB (min) LSB (max) mV mV (max) mV (max) %FS GHz Error/Sample dBFS Bits Bits (min) Bits (min) dB dB (min) dB (min) VOFF_ADJ Input Offset Adjustment Range PFSE NFSE FS_ADJ FPBW B.E.R. Positive Full-Scale Error (Note 9) Negative Full-Scale Error (Note 9) Full-Scale Adjustment Range Full Power Bandwidth Bit Error Rate Gain Flatness DYNAMIC CONVERTER CHARACTERISTICS 7 www.national.com ADC08500 Symbol Parameter Conditions fIN = 50 MHz, VIN = FSR − 0.5 dB Typical (Note 8) 48 47.5 47.5 -55 -56 -56 −60 −60 −60 −65 −65 −65 55 56 56 -50 Limits (Note 8) 45.3 45.3 −47.5 −47.5 Units (Limits) dB dB (min) dB (min) dB dB (max) dB (max) dB dB dB dB dB dB dB SNR Signal-to-Noise Ratio fIN = 124 MHz, VIN = FSR − 0.5 dB fIN = 248 MHz, VIN = FSR − 0.5 dB fIN = 50 MHz, VIN = FSR − 0.5 dB THD Total Harmonic Distortion fIN = 124 MHz, VIN = FSR − 0.5 dB fIN = 248 MHz, VIN = FSR − 0.5 dB fIN = 50 MHz, VIN = FSR − 0.5 dB 2nd Harm Second Harmonic Distortion fIN = 124 MHz, VIN = FSR − 0.5 dB fIN = 248 MHz, VIN = FSR − 0.5 dB fIN = 50 MHz, VIN = FSR − 0.5 dB 3rd Harm Third Harmonic Distortion fIN = 124 MHz, VIN = FSR − 0.5 dB fIN = 248 MHz, VIN = FSR − 0.5 dB fIN = 50 MHz, VIN = FSR − 0.5 dB SFDR Spurious-Free dynamic Range fIN = 124 MHz, VIN = FSR − 0.5 dB fIN = 248 MHz, VIN = FSR − 0.5 dB fIN1 = 121 MHz, VIN = FSR − 7 dB fIN2 = 126 MHz, VIN = FSR − 7 dB (VIN+) − (VIN−) > + Full Scale (VIN+) − (VIN−) < − Full Scale 47.5 47.5 dB (min) dB (min) dB IMD Intermodulation Distortion Out of Range Output Code (In addition to OR Output high) 255 0 570 730 790 950 VCMO − 50 VCMO + 50 mVP-P (min) mVP-P (max) mVP-P (min) mVP-P (max) mV (min) mV (max) pF pF 94 106 0.95 1.45 Ω (min) Ω (max) V (min) V (max) V V ppm/°C 80 pF V (min) V (max) ppm/°C 80 pF ANALOG INPUT AND REFERENCE CHARACTERISTICS FSR pin 14 Low VIN Full Scale Analog Differential Input Range FSR pin 14 High VCMI CIN RIN Analog Input Common Mode Voltage Analog Input Capacitance, Normal operation (Notes 10, 11) Differential Input Resistance Differential Each input pin to ground 870 VCMO 0.02 1.6 100 650 ANALOG OUTPUT CHARACTERISTICS VCMO VCMO_LVL TC VCMO CLOAD VCMO VBG TC VBG CLOAD VBG Common Mode Output Voltage VCMO input threshold to set DC Coupling mode Common Mode Output Voltage Temperature Coefficient Maximum VCMO load Capacitance Bandgap Reference Output Voltage Bandgap Reference Voltage Temperature Coefficient Maximum Bandgap Reference Load Capacitance IBG = ±100 µA TA = −40°C to +85°C IBG = ±100 µA 1.26 28 ICMO = ±100 µA VA = 1.8V VA = 2.0V TA = −40°C to +85°C 1.26 0.60 0.66 118 1.20 1.33 www.national.com 8 ADC08500 Symbol Parameter Conditions Typical (Note 8) Limits (Note 8) Units (Limits) TEMPERATURE DIODE CHARACTERISTICS 192 µA vs. 12 µA, TJ = 25°C 192 µA vs. 12 µA, TJ = 85°C 71.23 85.54 mV mV ΔVBE Temperature Diode Voltage CHANNEL-TO-CHANNEL CHARACTERISTICS Offset Error Match Positive Full-Scale Error Match Negative Full-Scale Error Match Phase Matching (I, Q) CLOCK INPUT CHARACTERISTICS Sine Wave Clock VID Differential Clock Input Level Square Wave Clock II CIN Input Current Input Capacitance (Notes 10, 11) VIN = 0 or VIN = VA Differential Each input to ground (Note 12) (Note 12) Each input to ground Measured differentially, OutV = VA, VBG = Floating, (Note 15) Measured differentially, OutV = GND, VBG = Floating, (Note 15) 1.2 400 920 280 720 0.6 ±1 0.02 1.5 0.85 x VA 0.15 x VA 0.6 0.4 2.0 0.4 2.0 VP-P (min) VP-P (max) VP-P (min) VP-P (max) µA pF pF V (min) V (max) pF mVP-P (min) mVP-P (max) mVP-P (min) mVP-P (max) mV mV mV mV mA Ohms 1.5 0.3 408 157 1.0 V V mA (max) mA mA (max) mA W (max) mW dB dB Zero offset selected in Control Register Zero offset selected in Control Register FIN = 1.0 GHz 1 1 1