ADC08D1020NOPB

ADC08D1020 Low Power, 8-Bit, Dual 1.0 GSPS or Single 2.0 GSPS A/D Converter November 22, 2009 ADC08D1020 Low Power, 8-Bit, Dual 1.0 GSPS or Single 2.0 GSPS A/D Converter General Description The ADC08D1020 is a dual, low power, high performance, CMOS analog-to-digital converter that builds upon the ADC08D1000 platform. The ADC08D1020 digitizes signals to 8 bits of resolution at sample rates up to 1.3 GSPS. It has expanded features compared to the ADC08D1000, which include a test pattern output for system debug, a clock phase adjust, and selectable output demultiplexer modes. Consuming a typical 1.6 Watts in non-demultiplex mode at 1 GSPS from a single 1.9 Volt supply, this device is guaranteed to have no missing codes over the full operating temperature range. The unique folding and interpolating architecture, the fully differential comparator design, the innovative design of the internal sample-and-hold amplifier and the calibration schemes enable a very flat response of all dynamic parameters beyond Nyquist, producing a high 7.4 Effective Number of Bits (ENOB) with a 498 MHz input signal and a 1 GHz sample rate while providing a 10−18 Code Error Rate (C.E.R.) Output formatting is offset binary and the Low Voltage Differential Signaling (LVDS) digital outputs are compatible with IEEE 1596.3-1996, with the exception of an adjustable common mode voltage between 0.8V and 1.2V. Each converter has a selectable output demultiplexer which feeds two LVDS buses. If the 1:2 demultiplexed mode is selected, the output data rate is reduced to half the input sample rate on each bus. When non-demultiplexed mode is selected, that output data rate on channels DI and DQ are at the same rate as the input sample clock. The two converters can be interleaved and used as a single 2 GSPS ADC. The converter typically consumes less than 3.5 mW in the Power Down Mode and is available in a leaded or lead-free 128-lead, thermally enhanced, exposed pad, LQFP and operates over the Industrial (-40°C ≤ TA ≤ +85°C) temperature range. Features ■ ■ ■ ■ ■ ■ ■ ■ ■ Single +1.9V ±0.1V Operation Interleave Mode for 2x Sample Rate Multiple ADC Synchronization Capability Adjustment of Input Full-Scale Range, Offset, and Clock Phase Adjust Choice of SDR or DDR output clocking 1:1 or 1:2 Selectable Output Demux Second DCLK output Duty Cycle Corrected Sample Clock Test pattern Key Specifications ■ ■ ■ ■ ■ ■ Resolution 8 Bits Max Conversion Rate 1 GSPS (min) Code Error Rate 10−18 (typ) ENOB @ 498 MHz Input (Normal Mode) 7.4 Bits (typ) DNL ±0.15 LSB (typ) Power Consumption 1.6 W (typ) — Operating in Non-demux Output 1.7 W (typ) — Operating in 1:2 Demux Output 3.5 mW (typ) — Power Down Mode Applications ■ ■ ■ ■ ■ Direct RF Down Conversion Digital Oscilloscopes Satellite Set-top boxes Communications Systems Test Instrumentation Ordering Information Industrial Temperature Range (-40°C < TA < +85°C) ADC08D1020CIYB ADC08D1020CIYB/NOPB ADC08D1020DEV NS Package Leaded 128-Pin Exposed Pad LQFP Lead-free 128-Pin Exposed Pad LQFP Development Board © 2009 National Semiconductor Corporation 202062 www.national.com ADC08D1020 Block Diagram 20206253 www.national.com 2 ADC08D1020 Pin Configuration 20206201 Note: The exposed pad on the bottom of the package must be soldered to a ground plane to ensure rated performance. 3 www.national.com ADC08D1020 Pin Descriptions and Equivalent Circuits Pin Functions Pin No. Symbol Equivalent Circuit Description Output Voltage Amplitude and Serial Interface Clock. Tie this pin high for normal differential DCLK and data amplitude. Ground this pin for a reduced differential output amplitude and reduced power consumption. See 1.1.6 The LVDS Outputs. When the extended control mode is enabled, this pin functions as the SCLK input which clocks in the serial data. See 1.2 NORMAL/EXTENDED CONTROL for details on the extended control mode. See 1.3 THE SERIAL INTERFACE for description of the serial interface. Power Down Pins. A logic high on the PD pin puts the entire device into the Power Down Mode. DCLK Edge Select, Double Data Rate Enable and Serial Data Input. This input sets the output edge of DCLK+ at which the output data transitions. (See 1.1.5.2 OutEdge and Demultiplex Control Setting). When this pin is floating or connected to 1/2 the supply voltage, DDR clocking is enabled. When the extended control mode is enabled, this pin functions as the SDATA input. See 1.2 NORMAL/ EXTENDED CONTROL for details on the extended control mode. See 1.3 THE SERIAL INTERFACE for description of the serial interface. DCLK Reset. When single-ended DCLK_RST is selected by floating or setting pin 52 logic high, a positive pulse on this pin is used to reset and synchronize the DCLK outputs of multiple converters. See 1.5 MULTIPLE ADC SYNCHRONIZATION for detailed description. When differential DCLK_RST is selected by setting pin 52 logic low, this pin receives the positive polarity of a differential pulse signal used to reset and synchronize the DCLK outputs of multiple converters. A logic high on the PDQ pin puts only the "Q" ADC into the Power Down mode. Calibration Cycle Initiate. A minimum 1280 input clock cycles logic low followed by a minimum of 1280 input clock cycles high on this pin initiates the calibration sequence. See 2.4.2 Calibration for an overview of calibration and 2.4.2.2 OnCommand Calibration for a description of on-command calibration. 3 OutV / SCLK 29 PDQ 4 OutEdge / DDR / SDATA 15 DCLK_RST / DCLK_RST+ 26 PD 30 CAL www.national.com 4 ADC08D1020 Pin Functions Pin No. Symbol Equivalent Circuit Description Full Scale Range Select, Alternate Extended Control Enable and DCLK_RST-. This pin has three functions. It can conditionally control the ADC full-scale voltage, enable the extended control mode, or become the negative polarity signal of a differential pair in differential DCLK_RST mode. If pin 52 and pin 41 are floating or at logic high, this pin can be used to set the full-scale-range or can be used as an alternate extended control enable pin . When used as the FSR pin, a logic low on this pin sets the full-scale differential input range to a reduced VIN input level. A logic high on this pin sets the full-scale differential input range to a higher VIN input level. See Converter Electrical Characteristics. To enable the extended control mode, whereby the serial interface and control registers are employed, allow this pin to float or connect it to a voltage equal to VA/2. See 1.2 NORMAL/EXTENDED CONTROL for information on the extended control mode. Note that pin 41 overrides the extended control enable of this pin. When pin 52 is held at logic low, this pin acts as the DCLK_RST- pin. When in differential DCLK_RST mode, there is no pin-controlled FSR and the full-scale-range is defaulted to the higher VIN input level. Calibration Delay, Dual Edge Sampling and Serial Interface Chip Select. With a logic high or low on pin 14, this pin functions as Calibration Delay and sets the number of input clock cycles after power up before calibration begins (See 1.1.1 Calibration). With pin 14 floating, this pin acts as the enable pin for the serial interface input and the CalDly value becomes "0" (short delay with no provision for a long powerup calibration delay). When this pin is floating or connected to a voltage equal to VA/2, DES (Dual Edge Sampling) mode is selected where the "I" input is sampled at twice the input clock rate and the "Q" input is ignored. See 1.1.5.1 DualEdge Sampling. 14 FSR/ALT_ECE/ DCLK_RST- 127 CalDly / DES / SCS 18 19 CLK+ CLK− LVDS Clock input pins for the ADC. The differential clock signal must be a.c. coupled to these pins. The input signal is sampled on the falling edge of CLK+. See 1.1.2 Acquiring the Input for a description of acquiring the input and 2.3 THE CLOCK INPUTS for an overview of the clock inputs. VINI+ VINI− 11 10 22 23 VINQ+ VINQ− Analog signal inputs to the ADC. The differential full-scale input range of this input is programmable using the FSR pin 14 in normal mode and the Input Full-Scale Voltage Adjust register in the extended control mode. Refer to the VIN specification in the Converter Electrical Characteristics for the full-scale input range in the normal mode. Refer to 1.4 REGISTER DESCRIPTION for the full-scale input range in the extended control mode. 5 www.national.com ADC08D1020 Pin Functions Pin No. Symbol Equivalent Circuit Description Common Mode Voltage. This pin is the common mode output in d.c. coupling mode and also serves as the a.c. coupling mode select pin. When d.c. coupling is used, the voltage output at this pin is required to be the common mode input voltage at VIN+ and VIN− when d.c. coupling is used. This pin should be grounded when a.c. coupling is used at the analog inputs. This pin is capable of sourcing or sinking 100 μA. See 2.2 THE ANALOG INPUT. Bandgap output voltage capable of 100 μA source/sink and can drive a load up to 80 pF. 7 VCMO 31 VBG 126 CalRun Calibration Running indication. This pin is at a logic high when calibration is running. 32 REXT External bias resistor connection. Nominal value is 3.3 kΩ (±0.1%) to ground. See 1.1.1 Calibration. 34 35 Tdiode_P Tdiode_N Temperature Diode Positive (Anode) and Negative (Cathode). These pins may be used for die temperature measurements, however no specified accuracy is implied or guaranteed. Noise coupling from adjacent output data signals has been shown to affect temperature measurements using this feature. See 2.6.2 Thermal Management. Extended Control Enable. This pin always enables and disables Extended Control Enable. When this pin is set logic high, the extended control mode is inactive and all control of the device must be through control pins only . When it is set logic low, the extended control mode is active. This pin overrides the Extended Control Enable signal set using pin 14. DCLK_RST select. This pin selects whether the DCLK is reset using a single-ended or differential signal. When this pin is floating or logic high, the DCLK_RST operation is single-ended and pin 14 functions as FSR/ALT_ECE. When this pin is logic low, the DCLK_RST operation becomes differential with functionality on pin 15 (DCLK_RST+) and pin 14 (DCLK_RST-). When in differential DCLK_RST mode, there is no pin-controlled FSR and the full-scale-range is defaulted to the higher VIN input level. When pin 41 is set logic low, the extended control mode is active and the FullScale Voltage Adjust registers can be programmed. 41 ECE 52 DRST_SEL www.national.com 6 ADC08D1020 Pin Functions Pin No. 83 / 78 84 / 77 85 / 76 86 / 75 89 / 72 90 / 71 91 / 70 92 / 69 93 / 68 94 / 67 95 / 66 96 / 65 100 / 61 101 / 60 102 / 59 103 / 58 104 / 57 105 / 56 106 / 55 107 / 54 111 / 50 112 / 49 113 / 48 114 / 47 115 / 46 116 / 45 117 / 44 118 / 43 122 / 39 123 / 38 124 / 37 125 / 36 Symbol DI7− / DQ7− DI7+ / DQ7+ DI6− / DQ6− DI6+ / DQ6+ DI5− / DQ5− DI5+ / DQ5+ DI4− / DQ4− DI4+ / DQ4+ DI3− / DQ3− DI3+ / DQ3+ DI2− / DQ2− DI2+ / DQ2+ DI1− / DQ1− DI1+ / DQ1+ DI0− / DQ0− DI0+ / DQ0+ DId7− / DQd7− DId7+ / DQd7+ DId6− / DQd6− DId6+ / DQd6+ DId5− / DQd5− DId5+ / DQd5+ DId4− / DQd4− DId4+ / DQd4+ DId3− / DQd3− DId3+ / DQd3+ DId2− / DQd2− DId2+ / DQd2+ DId1− / DQd1− DId1+ / DQd1+ DId0− / DQd0− DId0+ / DQd0+ Equivalent Circuit Description I and Q channel LVDS Data Outputs that are not delayed in the output demultiplexer. Compared with the DId and DQd outputs, these outputs represent the later time samples. These outputs should always be terminated with a 100 Ω differential resistor. I and Q channel LVDS Data Outputs that are delayed by one CLK cycle in the output demultiplexer. Compared with the DI/DQ outputs, these outputs represent the earlier time sample. These outputs should be terminated with a 100 Ω differential resistor when enabled. In non-demultiplexed mode, these outputs are disabled and are high impedance when enabled. When disabled, these outputs must be left floating. 79 80 OR+/DCLK2+ OR-/DCLK2- Out Of Range output. A differential high at these pins indicates that the differential input is out of range (outside the range ±VIN/2 as programmed by the FSR pin in nonextended control mode or the Input Full-Scale Voltage Adjust register setting in the extended control mode). DCLK2 is the exact mirror of DCLK and should output the same signal at the same rate. Data Clock. Differential Clock outputs used to latch the output data. Delayed and non-delayed data outputs are supplied synchronous to this signal. In 1:2 demultiplexed mode, this signal is at 1/2 the input clock rate in SDR mode and at 1/4 the input clock rate in the DDR mode. By default, the DCLK outputs are not active during the termination resistor trim section of the calibration cycle. If a system requires DCLK to run continuously during a calibration cycle, the termination resistor trim portion of the cycle can be disabled by setting the Resistor Trim Disable (RTD) bit to logic high in the Extended Configuration Register (address 9h). This disables all subsequent termination resistor trims after the initial trim which occurs during the power on calibration. Therefore, this output is not recommended as a system clock unless the resistor trim is disabled. When the device is in the non-demultiplexed mode, DCLK can only be in DDR mode and the signal is at 1/2 the input clock rate. 7 www.national.com 82 81 DCLK+ DCLK- ADC08D1020 Pin Functions Pin No. 2, 5, 8, 13, 16, 17, 20, 25, 28, 33, 128 40, 51, 62, 73, 88, 99, 110, 121 1, 6, 9, 12, 21, 24, 27 42, 53, 64, 74, 87, 97, 108, 119 63, 98, 109, 120 Symbol Equivalent Circuit Description VA Analog power supply pins. Bypass these pins to ground. VDR GND Output Driver power supply pins. Bypass these pins to DR GND. Ground return for VA. Ground return for VDR. No Connection. Make no connection to these pins. DR GND NC www.national.com 8 ADC08D1020 Absolute Maximum Ratings (Note 1, Note 2) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage (VA, VDR) Supply Difference VDR - VA Voltage on Any Input Pin (Except VIN+, VIN- ) Voltage on VIN+, VIN(Maintaining Common Mode) Ground Difference |GND - DR GND| Input Current at Any Pin (Note 3) Package Input Current (Note 3) Power Dissipation at TA ≤ 85°C ESD Susceptibility (Note 4) Human Body Model Machine Model Charged Device Model Storage Temperature 2.2V 0V to 100 mV −0.15V to (VA +0.15V) -0.15 to 2.5V 0V to 100 mV ±25 mA ±50 mA 2.3 W   2500V 250V 1000V −65°C to +150°C Operating Ratings Ambient Temperature Range Supply Voltage (VA) Driver Supply Voltage (VDR) Common Mode Input Voltage VIN+, VIN− Voltage Range (Maintaining Common Mode) (Note 1, Note 2) −40°C ≤ TA ≤ +85°C +1.8V to +2.0V +1.8V to VA VCMO ± 50 mV 0V to 2.15V (100% duty cycle) 0V to 2.5V (10% duty cycle) 0V 0V to VA 0.4VP-P to 2.0VP-P θJC Top of Package 10°C / W θJC Thermal Pad 2.8°C / W Ground Difference (|GND − DR GND|) CLK Pins Voltage Range Differential CLK Amplitude Package Thermal Resistance Package 128-Lead, Exposed Pad LQFP θJA 26°C / W Soldering process must comply with National Semiconductor’s Reflow Temperature Profile specifications. Refer to www.national.com/packaging. (Note 5) Converter Electrical Characteristics The following specifications apply after calibration for VA = VDR = 1.9V; OutV = 1.9V; VIN FSR (a.c. coupled) = differential 870 mVP-P; CL = 10 pF; Differential, a.c. coupled Sine Wave Input Clock, fCLK = 1 GHz at 0.5 VP-P with 50% duty cycle; VBG = Floating; Non-Extended Control Mode; SDR Mode; REXT = 3300 Ω ±0.1%; Analog Signal Source Impedance = 100 Ω Differential; 1:2 Output Demultiplex; Duty Cycle Stabilizer on. Boldface limits apply for TA = TMIN to TMAX. All other limits TA = 25°C, unless otherwise noted. (Note 6, Note 7) Symbol Parameter Conditions Typical (Note 8) Limits (Note 8) Units (Limits) STATIC CONVERTER CHARACTERISTICS INL DNL Integral Non-Linearity (Best fit) Differential Non-Linearity Resolution with No Missing Codes VOFF VOFF_ADJ PFSE NFSE FS_ADJ FPBW C.E.R. Offset Error Input Offset Adjustment Range Extended Control Mode Positive Full-Scale Error Negative Full-Scale Error Full-Scale Adjustment Range Full Power Bandwidth Code Error Rate Gain Flatness ENOB SINAD Effective Number of Bits d.c. to 498 MHz d.c. to 1 GHz fIN = 248 MHz, VIN = FSR − 0.5 dB fIN = 498 MHz, VIN = FSR − 0.5 dB (Note 9) (Note 9) Extended Control Mode Normal Mode ±20 2.0 10−18 ±0.8 ±1.0 7.4 7.4 46.5 46.5 7.0 7.0 43.9 43.9 −0.45 ±45 ±25 ±25 ±15 DC Coupled, 1 MHz Sine Wave Overanged DC Coupled, 1 MHz Sine Wave Overanged ±0.3 ±0.15 ±0.9 ±0.6 8 LSB (max) LSB (max) Bits LSB (min) LSB (max) mV mV (max) mV (max) %FS GHz Error/Sample dBFS dBFS Bits (min) Bits (min) dB (min) dB (min) NORMAL MODE (Non DES) DYNAMIC CONVERTER CHARACTERISTICS, 1:2 DEMUX MODE Signal-to-Noise Plus Distortion fIN = 248 MHz, VIN = FSR − 0.5 dB Ratio fIN = 498 MHz, VIN = FSR − 0.5 dB 9 www.national.com ADC08D1020 Symbol SNR THD 2nd Harm 3rd Harm SFDR IMD Parameter Signal-to-Noise Ratio Total Harmonic Distortion Second Harmonic Distortion Third Harmonic Distortion Spurious-Free dynamic Range Intermodulation Distortion Conditions fIN = 248 MHz, VIN = FSR − 0.5 dB fIN = 498 MHz, VIN = FSR − 0.5 dB fIN = 248 MHz, VIN = FSR − 0.5 dB fIN = 498 MHz, VIN = FSR − 0.5 dB fIN = 248 MHz, VIN = FSR − 0.5 dB fIN = 498 MHz, VIN = FSR − 0.5 dB fIN = 248 MHz, VIN = FSR − 0.5 dB fIN = 498 MHz, VIN = FSR − 0.5 dB fIN = 248 MHz, VIN = FSR − 0.5 dB fIN = 498 MHz, VIN = FSR − 0.5 dB fIN1 = 250 MHz, VIN = FSR − 7 dB fIN2 = 260 MHz, VIN = FSR − 7 dB Typical (Note 8) 46.8 46.8 −58 −58 −63 −63 −65 −65 58 58 -50 Limits (Note 8) 45.1 45.1 -50 -50 Units (Limits) dB (min) dB (min) dB (max) dB (max) dB dB dB dB 50 50 dB (min) dB (min) dB (VIN+) − (VIN−) > + Full Scale Out of Range Output Code (In addition to OR Output high) (VIN+) − (VIN−) < − Full Scale NORMAL MODE (Non DES) DYNAMIC CONVERTER CHARACTERISTICS, 1:1 DEMUX MODE ENOB SINAD SNR THD 2nd Harm 3rd Harm SFDR Effective Number of Bits fIN = 248 MHz, VIN = FSR − 0.5 dB fIN = 498 MHz, VIN = FSR − 0.5 dB 7.3 7.3 45.7 45.7 46 46 -57 -57 -63 -63 -64 -64 57 57 1.3 7.3 46 46.3 −58 −58 −66 57 255 0 Bits Bits dB dB dB dB dB dB dB dB dB dB dB dB GHz 6.7 42.1 43.8 -47 Bits (min) dB dB (min) dB (max) dB dB 47 580 720 800 940 VCMO − 0.05 VCMO + 0.05 dB (min) mVP-P (min) mVP-P (max) mVP-P (min) mVP-P (max) V (min) V (max) Signal-to-Noise Plus Distortion fIN = 248 MHz, VIN = FSR − 0.5 dB Ratio fIN = 498 MHz, VIN = FSR − 0.5 dB Signal-to-Noise Ratio Total Harmonic Distortion Second Harmonic Distortion Third Harmonic Distortion Spurious-Free dynamic Range fIN = 248 MHz, VIN = FSR − 0.5 dB fIN = 498 MHz, VIN = FSR − 0.5 dB fIN = 248 MHz, VIN = FSR − 0.5 dB fIN = 498 MHz, VIN = FSR − 0.5 dB fIN = 248 MHz, VIN = FSR − 0.5 dB fIN = 498 MHz, VIN = FSR − 0.5 dB fIN = 248 MHz, VIN = FSR − 0.5 dB fIN = 498 MHz, VIN = FSR − 0.5 dB fIN = 248 MHz, VIN = FSR − 0.5 dB fIN = 498 MHz, VIN = FSR − 0.5 dB Dual Edge Sampling Mode fIN = 498 MHz, VIN = FSR − 0.5 dB INTERLEAVE MODE (DES Pin 127=Float) - DYNAMIC CONVERTER CHARACTERISTICS, 1:4 DEMUX MODE FPBW ENOB SINAD SNR THD 2nd Harm 3rd Harm SFDR Full Power Bandwidth Effective Number of Bits Signal to Noise Plus Distortion fIN = 498 MHz, VIN = FSR − 0.5 dB Ratio Signal to Noise Ratio Total Harmonic Distortion Second Harmonic Distortion Third Harmonic Distortion fIN = 498 MHz, VIN = FSR − 0.5 dB fIN = 498 MHz, VIN = FSR − 0.5 dB fIN = 498 MHz, VIN = FSR − 0.5 dB fIN = 498 MHz, VIN = FSR − 0.5 dB Spurious Free Dynamic Range fIN = 498 MHz, VIN = FSR − 0.5 dB ANALOG INPUT AND REFERENCE CHARACTERISTICS FSR pin 14 Low VIN Full Scale Analog Differential Input Range FSR pin 14 High VCMI Common Mode Input Voltage 870 VCMO 650 www.national.com 10 ADC08D1020 Symbol Parameter Analog Input Capacitance, Normal operation (Note 10, Note 11) Differential Conditions Typical (Note 8) 0.02 1.6 0.08 2.2 100 Limits (Note 8) Units (Limits) pF pF pF pF Ω (min) Ω (max) CIN Each input pin to ground Differential Analog Input Capacitance, DES Mode (Note 10, Note 11) Each input pin to ground RIN Differential Input Resistance ANALOG OUTPUT CHARACTERISTICS VCMO Common Mode Output Voltage Common Mode Output Voltage Temperature Coefficient ICMO = ±100 µA 1.26 0.95 1.45 V (min) V (max) ppm/°C V V 80 IBG = ±100 µA TA = −40°C to +85°C, IBG = ±100 µA 1.26 28 80 1.20 1.33 pF V (min) V (max) ppm/°C pF TC VCMO TA = −40°C to +85°C 118 0.60 0.66 VCMO_LVL CLOAD VCMO VBG TC VBG CLOAD VBG VCMO input threshold to set DC VA = 1.8V Coupling mode VA = 2.0V Maximum VCMO load Capacitance Bandgap Reference Output Voltage Bandgap Reference Voltage Temperature Coefficient Maximum Bandgap Reference load Capacitance Offset Match Positive Full-Scale Match Negative Full-Scale Match Phase Matching (I, Q) Zero offset selected in Control Register Zero offset selected in Control Register fIN = 1.0 GHz CHANNEL-TO-CHANNEL CHARACTERISTICS 1 1 1