ADC10732

ADC10731/ADC10732/ADC10734/ADC10738 10-Bit Plus Sign Serial I/O A/D Converters with Mux, Sample/Hold and Reference April 2006 ADC10731/ADC10732/ADC10734/ADC10738 10-Bit Plus Sign Serial I/O A/D Converters with Mux, Sample/Hold and Reference General Description The ADC12731, ADC12732 and ADC12734 are obsolete or on lifetime buy and included for reference only. This series of CMOS 10-bit plus sign successive approximation A/D converters features versatile analog input multiplexers, sample/hold and a 2.5V band-gap reference. The 1-, 2-, 4-, or 8-channel multiplexers can be software configured for single-ended or differential mode of operation. An input sample/hold is implemented by a capacitive reference ladder and sampled-data comparator. This allows the analog input to vary during the A/D conversion cycle. In the differential mode, valid outputs are obtained even when the negative inputs are greater than the positive because of the 10-bit plus sign output data format. The serial I/O is configured to comply with the NSC MICROWIRE™ serial data exchange standard for easy interface to the COPS™ and HPC™ families of controllers, and can easily interface with standard shift registers and microprocessors. Features n n n n n n n n 0V to analog supply input range Serial I/O (MICROWIRE compatible) Software or hardware power down Analog input sample/hold function Ratiometric or absolute voltage referencing No zero or full scale adjustment required No missing codes over temperature TTL/CMOS input/output compatible Key Specifications n n n n n n n Resolution Single supply Power consumption In power down mode Conversion time Sampling rate Band-gap reference 10 bits plus sign 5V 37 mW (Max) 18 µW 5µs (Max) 74 kHz (Max) 2.5V ± 2% (Max) Applications n Medical instruments n Portable and remote instrumentation n Test equipment ADC10738 Simplified Block Diagram 01139001 COPS™, HPC™ and MICROWIRE™ are trademarks of National Semiconductor Corporation. © 2006 National Semiconductor Corporation DS011390 www.national.com ADC10731/ADC10732/ADC10734/ADC10738 Connection Diagrams The ADC12731, ADC12732 and ADC12734 are obsolete in all packages. They are in this data sheet for reference only. 01139002 Top View See NS Package Number M16B 01139004 Top View See NS Package Number M20B 01139003 Top View See NS Package Number M20B 01139005 Top View See NS Package Number M24B SSOP Package 01139034 See NS Package Number MSA20 www.national.com 2 ADC10731/ADC10732/ADC10734/ADC10738 Ordering Information Industrial Temperature Range −40˚C ≤ TA ≤ +85˚C ADC10731CIWM * ADC10732CIWM * ADC10734CIMSA * ADC10734CIWM * ADC10738CIWM * These products are obsolete or on lifetime buy and shown for reference only. M16B M20B MSA20 M20B M24B Package Pin Descriptions CLK The clock applied to this input controls the successive approximation conversion time interval, the acquisition time and the rate at which the serial data exchange occurs. The rising edge loads the information on the DI pin into the multiplexer address shift register. This address controls which channel of the analog input multiplexer (MUX) is selected. The falling edge shifts the data resulting from the A/D conversion out on DO. CS enables or disables the above functions. The clock frequency applied to this input can be between 5 kHz and 3 MHz. This is the serial data input pin. The data applied to this pin is shifted by CLK into the multiplexer address register. Tables 1, 2, 3 show the multiplexer address assignment. The data output pin. The A/D conversion result (DB0-SIGN) are clocked out by the failing edge of CLK on this pin. This is the chip select input pin. When a logic low is applied to this pin, the rising edge of CLK shifts the data on DI into the address register. This low also brings DO out of TRI-STATE after a conversion has been completed. This is the power down input pin. When a logic high is applied to this pin the A/D is powered down. When a low is applied the A/D is powered up. This is the successive approximation register status output pin. When CS is high this pin is in TRI-STATE. With CS low this pin is active high when a conversion is in progress and active low at all other times. CH0–CH7 These are the analog inputs of the MUX. A channel input is selected by the address information at the DI pin, which is loaded on the rising edge of CLK into the address register (see Tables 1, 2, 3). The voltage applied to these inputs should not exceed AV+ or go below GND by more than 50 mV. Exceeding this range on an unselected channel will corrupt the reading of a selected channel. This pin is another analog input pin. It can be used as a “pseudo ground” when the analog multiplexer is single-ended. This is the positive analog voltage reference input. In order to maintain accuracy, the voltage range VREF (VREF = VREF+–VREF−) is 0.5 VDCto 5.0 VDC and the voltage at VREF+ cannot exceed AV+ +50 mV. The negative voltage reference input. In order to maintain accuracy, the voltage at this pin must not go below GND − 50 mV or exceed AV+ + 50 mV. These are the analog and digital power supply pins. These pins should be tied to the same power supply and bypassed separately. The operating voltage range of AV+ and DV+ is 4.5 VDC to 5.5 VDC. This is the digital ground pin. This is the analog ground pin. DI COM VREF+ DO CS VREF− PD AV+, DV+ SARS DGND AGND 3 www.national.com ADC10731/ADC10732/ADC10734/ADC10738 Absolute Maximum Ratings (Notes 1, 2) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage (V+ = AV+ = DV+) Total Reference Voltage (VREF+–VREF−) Voltage at Inputs and Outputs Input Current at Any Pin (Note 4) Package Input Current (Note 4) Package Dissipation at TA = 25˚C (Note 5) ESD Susceptibility (Note 6) Human Body Model Machine Model Soldering Information N packages (10 seconds) SO Package (Note 7) Vapor Phase (60 seconds) Infrared (15 seconds) Storage Temperature 215˚C 220˚C −40˚C to +150˚C 260˚C 2500V 150V 500 mW + Operating Ratings (Notes 3, 2) Operating Temperature Range Supply Voltage (V+ = AV+ = DV+) VREF+ VREF− 6.5V VREF (VREF+–VREF−) + TMIN ≤ TA ≤ TMAX −40˚C ≤ TA ≤ +85˚C +4.5V to +5.5V AV +50 mV to −50 mV AV+ +50 mV to −50 mV +0.5V to V+ 6.5V V + 0.3V to −0.3V 30 mA 120 mA Electrical Characteristics The following specifications apply for V+ = AV+ = DV+ = +5.0 VDC, VREF+ = 2.5 VDC, VREF− = GND, VIN− = 2.5V for Signed Characteristics, VIN− = GND for Unsigned Characteristics and fCLK = 2.5 MHz unless otherwise specified. Boldface limits apply for TA = TJ = TMIN to TMAX; all other limits TA = TJ = +25˚C. (Notes 8, 9, 10) Symbol Parameter Conditions Typical (Note 11) Limits (Note 12) 10 + Sign Units (Limits) Bits LSB (max) LSB (max) LSB (max) LSB (max) LSB (max) LSB (max) LSB (max) LSB (max) LSB 10 VREF+ = 4.096V VREF+ = 4.096V VREF+ = 4.096V VREF+ = 4.096V V+ = +5.0V ± 10% VREF+ = 4.096V Bits LSB LSB SIGNED STATIC CONVERTER CHARACTERISTICS Resolution with No Missing Codes TUE INL Total Unadjusted Error (Note 13) Positive and Negative Integral Linearity Error Positive and Negative Full-Scale Error Offset Error Power Supply Sensitivity Offset Error + Full-Scale Error − Full-Scale Error DC Common Mode Error (Note 14) Multiplexer Chan to Chan Matching UNSIGNED STATIC CONVERTER CHARACTERISTICS Resolution with No Missing Codes TUE INL Total Unadjusted Error (Note 13) Integral Linearity Error Full-Scale Error Offset Error Power Supply Sensitivity Offset Error Full-Scale Error VIN+ = VIN− = VIN where 5.0V ≥ VIN ≥ 0V V+ = +5.0V ± 10% ± 2.0 ± 1.25 ± 1.5 ± 1.5 ± 0.2 ± 0.2 ± 0.1 ± 0.1 ± 0.1 ± 1.0 ± 1.0 ± 0.75 ± 0.33 ± 0.75 ± 0.50 ± 1.25 ± 1.25 ± 0.1 ± 0.1 LSB (max) LSB (max) LSB LSB www.national.com 4 ADC10731/ADC10732/ADC10734/ADC10738 Electrical Characteristics (Continued) The following specifications apply for V+ = AV+ = DV+ = +5.0 VDC, VREF+ = 2.5 VDC, VREF− = GND, VIN− = 2.5V for Signed Characteristics, VIN− = GND for Unsigned Characteristics and fCLK = 2.5 MHz unless otherwise specified. Boldface limits apply for TA = TJ = TMIN to TMAX; all other limits TA = TJ = +25˚C. (Notes 8, 9, 10) Parameter Conditions Typical (Note 11) Limits (Note 12) Units (Limits) Symbol UNSIGNED STATIC CONVERTER CHARACTERISTICS DC Common Mode Error (Note 14) Multiplexer Channel to Channel Matching VIN+ = VIN− = VIN where +5.0V ≥ VIN ≥ 0V VREF+ = 4.096V ± 0.1 ± 0.1 LSB LSB DYNAMIC SIGNED CONVERTER CHARACTERISTICS S/(N+D) ENOB THD IMD Signal-to-Noise Plus Distortion Ratio Effective Number of Bits Total Harmonic Distortion Intermodulation Distortion Full-Power Bandwidth Multiplexer Chan to Chan Crosstalk VIN = 4.85 VPP, and fIN = 1 kHz to 15 kHz VIN = 4.85 VPP, and fIN = 1 kHz to 15 kHz VIN = 4.85 VPP, and fIN = 1 kHz to 15 kHz VIN = 4.85 VPP, and fIN = 1 kHz to 15 kHz VIN = 4.85 VPP, where S/(N + D) Decreases 3 dB fIN = 15 kHz VREF+ = 4.096V, VIN = 4.0 VPP, and fIN =1 kHz to 15 kHz VREF+ = 4.096V, VIN = 4.0 VPP, and fIN = 1 kHz to 15 kHz VREF+ = 4.096V, VIN = 4.0 VPP, and fIN = 1 kHz to 15 kHz VREF+ = 4.096V, VIN = 4.0 VPP, and fIN = 1 kHz to 15 kHz VIN = 4.0 VPP, VREF+ = 4.096V, where S/(N+D) decreases 3 dB fIN = 15 kHz, VREF+ = 4.096V 67 10.8 −78 −85 380 −80 dB Bits dB dB kHz dB DYNAMIC UNSIGNED CONVERTER CHARACTERISTIC S/(N+D) Signal-to-Noise Plus Distortion Ratio 60 dB ENOB Effective Bits 9.8 Bits THD Total Harmonic Distortion −70 dB IMD Intermodulation Distortion −73 dB Full-Power Bandwidth 380 kHz Multiplexer Chan to Chan Crosstalk −80 dB REFERENCE INPUT AND MULTIPLEXER CHARACTERISTICS 7 Reference Input Resistance CREF Reference Input Capacitance MUX Input Voltage CIM MUX Input Capacitance Off Channel Leakage Current (Note 15) On Channel = 5V and Off Channel = 0V On Channel = 0V and Off Channel = 5V 47 −0.4 0.4 −3.0 3.0 70 −50 AV+ + 50mV 5.0 9.5 kΩ kΩ(min) kΩ(max) pF mV (min) (max) pF µA (max) µA (max) 5 www.national.com ADC10731/ADC10732/ADC10734/ADC10738 Electrical Characteristics (Continued) The following specifications apply for V+ = AV+ = DV+ = +5.0 VDC, VREF+ = 2.5 VDC, VREF− = GND, VIN− = 2.5V for Signed Characteristics, VIN− = GND for Unsigned Characteristics and fCLK = 2.5 MHz unless otherwise specified. Boldface limits apply for TA = TJ = TMIN to TMAX; all other limits TA = TJ = +25˚C. (Notes 8, 9, 10) Parameter Conditions Typical (Note 11) Limits (Note 12) Units (Limits) Symbol REFERENCE INPUT AND MULTIPLEXER CHARACTERISTICS On Channel Leakage Current (Note 15) REFERENCE CHARACTERISTICS VREFOut ∆VREF/∆T Reference Output Voltage VREFOut Temperature Coefficient 0 mA ≤ IL ≤ +4 mA 0 mA ≤ IL ≤ −1 mA 5V ± 10% VREFOut = 0V 10 Hz to 10 kHz, CL = 100 µF CL = 100 µF V+ = 5.5V V+ = 4.5V VIN = 5.0V VIN = 0V V+ = 4.5V, IOUT = −360 µA V = 4.5V, IOUT = −10 µA V+ = 4.5V, IOUT = 1.6 mA VOUT = 0V VOUT = 5V VOUT = 0V, V+ = 4.5V VOUT= V+ = 4.5V CS = HIGH, Power Up ID+ Digital Supply Current (Note 17) CS = HIGH, Power Down CS = HIGH, Power Down, and CLK Off CS = HIGH, Power Up CS = HIGH, Power Down VREF+ = +2.5V and CS = HIGH, Power Up 3.0 5 −0.1 +0.1 −30 30 0.9 0.2 0.5 2.7 3 + On Channel = 5V and Off Channel = 0V On Channel = 0V and Off Channel = 5V 0.4 −0.4 3.0 −3.0 µA (max) µA (max) 2.5V ± 0.5% 2.5V ± 2% V (max) ppm/˚C %/mA (max) %/mA (max) mV (max) mA (max) µV ppm/kHr ms ± 40 ± 0.003 ± 0.2 ± 0.3 13 5 ∆VREF/∆IL Load Regulation, Sourcing ∆VREF/∆IL Load Regulation, Sinking Line Regulation ISC Short Circuit Current Noise Voltage ∆VREF/∆t tSU VIN(1) VIN(0) IIN(1) IIN(0) VOUT(1) VOUT(0) Long-term Stability Start-Up Time Logical “1” Input Voltage Logical “0” Input Voltage Logical “1” Input Current Logical “0” Input Current Logical “1” Output Voltage Logical “0” Output Voltage ± 0.05 ± 0.6 ± 2.5 22 ± 120 100 2.0 0.8 0.005 −0.005 +2.5 −2.5 2.4 4.5 0.4 −3.0 +3.0 −15 15 1.3 0.4 50 6.0 15 0.6 DIGITAL AND DC CHARACTERISTICS V (min) V (max) µA (max) µA (max) V (min) V (min) V (min) µA (max) µA (max) mA(min) mA (min) mA (max) mA (max) µA (max) mA (max) µA (max) mA (max) IOUT +ISC −ISC TRI-STATE Output Current Output Short Circuit Source Current Output Short Circuit Sink Current IA+ IREF Analog Supply Current (Note 17) Reference Input Current AC CHARACTERISTICS fCLK Clock Frequency Clock Duty Cycle tC tA Conversion Time Acquisition Time 12 5 4.5 2 2.5 40 60 12 5 4.5 2 MHz (max) kHz (min) %(min) %(max) Clock Cycles µs (max) Clock Cycles µs (max) www.national.com 6 ADC10731/ADC10732/ADC10734/ADC10738 Electrical Characteristics (Continued) The following specifications apply for V+ = AV+ = DV+ = +5.0 VDC, VREF+ = 2.5 VDC, VREF− = GND, VIN− = 2.5V for Signed Characteristics, VIN− = GND for Unsigned Characteristics and fCLK = 2.5 MHz unless otherwise specified. Boldface limits apply for TA = TJ = TMIN to TMAX; all other limits TA = TJ = +25˚C. (Notes 8, 9, 10) Parameter Conditions Typical (Note 11) 14 (1 tCLK − 14 ns) 16 Limits (Note 12) 30 (1 tCLK − 30 ns) 25 Units (Limits) ns (min) (max) Symbol AC CHARACTERISTICS tSCS CS Set-Up Time, Set-Up Time from Falling Edge of CS to Rising Edge of Clock DI Set-Up Time, Set-Up Time from Data Valid on DI to Rising Edge of Clock DI Hold Time, Hold Time of DI Data from Rising Edge of Clock to Data not Valid on DI DO Access Time from Rising Edge of CLK When CS is “Low” during a Conversion DO or SARS Access Time from CS , Delay from Falling Edge of CS to Data Valid on DO or SARS Delay from Rising Edge of Clock to Falling Edge of SARS when CS is “Low” DO Hold Time, Hold Time of Data on DO after Falling Edge of Clock DO Access Time from Clock, Delay from Falling Edge of Clock to Valid Data of DO Delay from Rising Edge of CS to DO or SARS TRI-STATE Delay from Falling Edge of Clock to Falling Edge of CS CS “HIGH” Time for A/D Reset after Reading of Conversion Result ADC10731 Minimum CS “Low” Time to Start a Conversion Time from End of Conversion to CS Going “Low” Delay from Power-Down command to 10% of Operating Current Delay from Power-Up Command to Ready to Start a New Conversion Capacitance of Logic Inputs Capacitance of Logic Outputs tSDI ns (min) tHDI 2 25 ns (min) tAT 30 50 ns (min) tAC 30 70 ns (max) tDSARS 100 200 ns (max) tHDO 20 35 ns (max) tAD 40 80 ns (max) t1H, t0H tDCS tCS(H) tCS(L) tSC tPD tPC CIN COUT 40 20 1 CLK 1 CLK 5 CLK 1 10 7 12 50 30 1 CLK 1 CLK 5 CLK ns (max) ns (min) cycle (min) cycle (min) cycle (min) µs µs pF pF Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Note 2: All voltages are measured with respect to GND, unless otherwise specified. Note 3: Operating Ratings indicate conditions for which the device is functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions. Note 4: When the input voltage (VIN) at any pin exceeds the power supplies (VIN < GND or VIN > AV+ or DV+), the current at that pin should be limited to 30 mA. The 120 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 30 mA to four. Note 5: The maximum power dissipation must be derated at elevated temperatures and is dictated by TJmax, θJA and the ambient temperature, TA. The maximum allowable power dissipation at any temperature is PD = (TJmax − TA)/θJA or the number given In the Absolute Maximum Ratings, whichever is lower. For this device, TJmax = 150˚C. The typical thermal resistance (θJA) of these Paris when board mounted can be found in the following table: 7 www.national.com ADC10731/ADC10732/ADC10734/ADC10738 Electrical Characteristics (Continued) Thermal Resistance 90˚C/W 80˚C/W 134˚C/W 80˚C/W 75˚C/W Package Type M16B M20B MSA20 M20B M24B Part Number ADC10731CIWM ADC10732CIWM ADC10734CIMSA ADC10734CIWM ADC10738CIWM Note 6: The human body model is a 100 pF capacitor discharged through a 1.5 kΩ resistor into each pin. The machine model is a 200 pF capacitor discharged directly into each pin. Note 7: See AN-450 “Surface Mounting Methods and Their Effect on Product Reliability” or the section titled “Surface Mount” found in any post 1986 National Semiconductor Linear Data Book for other methods of soldering surface mount devices. Note 8: Two on-chip diodes are tied to each analog input as shown below. They will forward-conduct for analog input voltages one diode drop below ground or one diode drop greater than V+ supply. Be careful during testing at low V+ levels (+4.5V), as high level analog inputs (+5V) can cause an input diode to conduct, especially at elevated temperatures, which will cause errors In the conversion result. The specification allows 50 mV forward bias of either diode; this means that as long as the analog VIN does not exceed the supply voltage by more than 50 mV, the output code will be correct. Exceeding this range on an unselected channel will corrupt the reading of a selected channel. If AV+ and DV+ are minimum (4.5 VDC) and full scale must be ≤+4.55 VDC. 01139006 Note 9: No connection exists between AV and DV on the chip. To guarantee accuracy, it is required that the AV+ and DV+ be connected together to a power supply with separate bypass filter at each V+ pin. Note 10: One LSB is referenced to 10 bits of resolution. Note 11: Typicals are at TJ = TA = 25˚C and represent most likely parametric norm. Note 12: Tested limits are guaranteed to National’s AOQL (Average Outgoing Quality Level). Note 13: Total unadjusted error includes offset, full-scale, linearity, multiplexer, and hold step errors. Note 14: The DC common-mode error is measured in the differential multiplexer mode with the assigned positive and negative input channels shorted together. Note 15: Channel leakage current is measured after the channel selection. Note 16: All the timing specifications are tested at the TTL logic levels, VIL = 0.8V for a falling edge and VIH = 2.0V for a rising. TRl-STATE voltage level is forced to 1.4V. Note 17: The voltage applied to the digital inputs will affect the current drain during power down. These devices are tested with CMOS logic levels (logic Low = 0V and logic High = 5V). TTL levels increase the current, during power down, to about 300 µA. + + www.national.com 8 ADC10731/ADC10732/ADC10734/ADC10738 01139008 FIGURE 1. Transfer Characteristic 01139026 FIGURE 2. Simplified Error Curve vs. Output Code 9 www.national.com ADC10731/ADC10732/ADC10734/ADC10738 Test Circuit Leakage Current Test Circuit 01139009 Typical Performance Characteristics Analog Supply Current (IA+) vs. Temperature Analog Supply Current (IA+) vs. Clock Frequency 01139035 01139036 Digital Supply Current (ID+) vs. Temperature Digital Supply Current (ID+) vs. Clock Frequency 01139037 01139038 www.national.com 10 ADC10731/ADC10732/ADC10734/ADC10738 Typical Performance Characteristics Offset Error vs. Reference Voltage (Continued) Offset Error vs. Temperature 01139039 01139040 Linearity Error vs. Clock Frequency Linearity Error vs. Reference Voltage 01139041 01139042 Linearity Error vs. Temperature 10-Bit Unsigned Signal-to-Noise + THD Ratio vs. Input Signal Level 01139043 01139044 11 www.national.com ADC10731/ADC10732/ADC10734/ADC10738 Typical Performance Characteristics Spectral Response with 34 kHz Sine Wave (Continued) Power Bandwidth Response with 380 kHz Sine Wave 01139045 01139046 Typical Reference Performance Characteristics Load Regulation Line Regulation 01139048 01139047 Output Drift vs. Temperature (3 Typical Parts) Available Output Current vs. Supply Voltage 01139049 01139050 www.national.com 12 ADC10731/ADC10732/ADC10734/ADC10738 TRI-STATE Test Circuits and Waveforms 01139010 01139013 01139011 01139012 Timing Diagrams 01139014 FIGURE 3. DI Timing 13 www.national.com ADC10731/ADC10732/ADC10734/ADC10738 Timing Diagrams (Continued) 01139015 FIGURE 4. DO Timing 01139016 FIGURE 5. Delayed DO Timing 01139017 FIGURE 6. Hardware Power Up/Down Sequence www.national.com 14 ADC10731/ADC10732/ADC10734/ADC10738 Timing Diagrams (Continued) 01139018 FIGURE 7. Software Power Up/Down Sequence 01139019 Note: If CS is low during power up of the power supply voltages (AV+ and DV+) then CS needs to go high for tCS(H). The data output after the first conversion is invalid. The ADC10731 is obsolete. Information shown for reference only. FIGURE 8. ADC10731 CS Low during Conversion 15 www.national.com ADC10731/ADC10732/ADC10734/ADC10738 (Continued) www.national.com 01139020 Timing Diagrams 16 Note: If CS is low during power up of the power supply voltages (AV+ and DV+) then CS needs to go high for tCS(H). The data output after the first conversion is not valid. The ADC10732 and the ADC10734 are obsolete. Information shown for reference only. FIGURE 9. ADC10732, ADC10734 and ADC10738 CS Low during Conversion Timing Diagrams (Continued) ADC10731/ADC10732/ADC10734/ADC10738 17 01139021 Note: If CS is low during power up of the power supply voltages (AV+ and DV+) then CS needs to go high for tCS(H). The data output after the first conversion is not valid. The ADC10731 is obsolete. Information shown for reference only. FIGURE 10. ADC10731 Using CS to Delay Output of Data after a Conversion has Completed www.national.com ADC10731/ADC10732/ADC10734/ADC10738 (Continued) www.national.com 01139022 Timing Diagrams 18 Note: If CS is low during power up of the power supply voltages (AV+ and DV+) then CS needs to go high for tCS(H). The data output after the first conversion is not valid. The ADC10732 and the ADC10734 are obsolete. Information shown for reference only. FIGURE 11. ADC10732, ADC10734 and ADC10738 Using CS to Delay Output of Data after a Conversion has Completed ADC10731/ADC10732/ADC10734/ADC10738 TABLE 1. ADC10738 Multiplexer Address Assignment MUX Address MA0 PU 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 MA1 SING/ DIFF 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 X MA2 ODD/ SIGN 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 X 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 X 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 X − + − + − + − + + − + − + − + − Differential + + + + + + + + − − − − − − − − Single-Ended MA3 SEL1 MA4 SEL0 CH0 CH1 CH2 Channel Number CH3 CH4 CH5 CH6 CH7 COM MUX MODE Power Down (All Channels Disconnected) TABLE 2. ADC10734 (Obsolete) Multiplexer Address Assignment MUX Address MA0 PU 1 1 1 1 1 1 1 1 0 MA1 SING/ DIFF 1 1 1 1 0 0 0 0 X MA2 ODD/ SIGN 0 0 1 1 0 0 1 1 X 0 0 0 0 0 0 0 0 X 0 1 0 1 0 1 0 1 X − + − + Power Down (All Channels Disconnected) + − + − Differential + + + + − − − − Single-Ended MA3 SEL1 MA4 SEL0 CH0 Channel Number CH1 CH2 CH3 COM MUX MODE TABLE 3. ADC10732 (Obsolete) Multiplexer Address Assignment MUX Address MA0 PU 1 1 1 1 0 MA1 SlNG/DIFF 1 1 0 0 X MA2 ODD/SIGN 0 1 0 1 X MA3 SEL1 0 0 0 0 X MA4 SEL0 0 0 0 0 X + − + + − + Power Down (All Channels Disconnected) − − Differential Single-Ended CH0 Channel Number CH1 COM MUX MODE 19 www.national.com ADC10731/ADC10732/ADC10734/ADC10738 Applications Hints The ADC10731, ADC10732 and ADC10734 are obsolete and discussed here for reference only. The ADC10731/2/4/8 use successive approximation to digitize an analog input voltage. The DAC portion of the A/D converters uses a capacitive array and a resistive ladder structure. The structure of the DAC allows a very simple switching scheme to provide a versatile analog input multiplexer. This structure also provides a sample/hold. The ADC10731/2/4/8 have a 2.5V CMOS bandgap reference. The serial digital I/O interfaces to MICROWIRE and MICROWIRE+. 1.0 DIGITAL INTERFACE There are two modes of operation. The fastest throughput rate is obtained when CS is kept low during a conversion. The timing diagrams in Figures 8, 9 show the operation of the devices in this mode. CS must be taken high for at least tCS(H) (1 CLK) between conversions. This is necessary to reset the internal logic. Figures 10, 11 show the operation of the devices when CS is taken high while the ADC10731/2/ 4/8 is converting. CS may be taken high during the conversion and kept high indefinitely to delay the output data. This mode simplifies the interface to other devices while the ADC10731/2/4/8 is busy converting. 1.1 Getting Started with a Conversion The ADC10731/2/4/8 need to be initialized after the power supply voltage is applied. If CS is low when the supply voltage is applied then CS needs to be taken high for at least tCS(H)(1 clock period). The data output after the first conversion is not valid. 1.2 Software and Hardware Power Up/Down These devices have the capability of software or hardware power down. Figures 6, 7 show the timing diagrams for hardware and software power up/down. In the case of hardware power down note that CS needs to be high for tPC after PD is taken low. When PD is high the device is powered down. The total quiescent current, when powered down, is typically 200 µA with the clock at 2.5 MHz and 3 µA with the clock off. The actual voltage level applied to a digital input will effect the power consumption of the device during power down. CMOS logic levels will give the least amount of current drain (3 µA). TTL logic levels will increase the total current drain to 200 µA. These devices have resistive reference ladders which draw 600 µA with a 2.5V reference voltage. The internal band gap reference voltage shuts down when power down is activated. If an external reference voltage is used, it will have to be shut down to minimize the total current drain of the device. 2.0 ARCHITECTURE Before a conversion is started, during the analog input sampling period, (tA), the sampled data comparator is zeroed. As the comparator is being zeroed the channel assigned to be the positive input is connected to the A/D’s input capacitor. (The assignment procedure is explained in the Pin Descriptions section.) This charges the input 32C capacitor of the DAC to the positive analog input voltage. The switches shown in the DAC portion of Figure 12 are set for this zeroing/acquisition period. The voltage at the input and output of the comparator are at equilibrium at this time. When the conversion is started, the comparator feedback switches are opened and the 32C input capacitor is then switched to the assigned negative input voltage. When the comparator feedback switch opens, a fixed amount of charge is trapped on the common plates of the capacitors. The voltage at the input of the comparator moves away from equilibrium when the 32C capacitor is switched to the assigned negative input voltage, causing the output of the comparator to go high (“1”) or low (“0”). The SAR next goes through an algorithm, controlled by the output state of the comparator, that redistributes the charge on the capacitor array by switching the voltage on one side of the capacitors in the array. The objective of the SAR algorithm is to return the voltage at the input of the comparator as close as possible to equilibrium. The switch position information at the completion of the successive approximation routine is a direct representation of the digital output. This data is then available to be shifted on the DO pin. www.national.com 20 Applications Hints (Continued) ADC10731/ADC10732/ADC10734/ADC10738 21 01139028 FIGURE 12. Detailed Diagram of the ADC10738 DAC and Analog Multiplexer Stages www.national.com ADC10731/ADC10732/ADC10734/ADC10738 Applications Hints 3.1 Multiplexer Configuration (Continued) 3.0 APPLICATIONS INFORMATION The design of these converters utilizes a sampled-data comparator structure, which allows a differential analog input to be converted by the successive approximation routine. The actual voltage converted is always the difference between an assigned “+” input terminal and a “−” input terminal. The polarity of each input terminal or pair of input terminals being converted indicates which line the converter expects to be the most positive. A unique input multiplexing scheme has been utilized to provide multiple analog channels. The input channels can be software configured into three modes: differential, singleended, or pseudo-differential. Figure 13 illustrates the three modes using the 4-channel MUX of the ADC10734. The eight inputs of the ADC10738 can also be configured in any of the three modes. The single-ended mode has CH0–CH3 assigned as the positive input with COM serving as the negative input. In the differential mode, the ADC10734 channel inputs are grouped in pairs, CH0 with CH1 and CH2 with CH3. The polarity assignment of each channel in the pair is interchangeable. Finally, in the pseudo-differential mode CH0–CH3 are positive inputs referred to COM which is now a pseudo-ground. This pseudo-ground input can be set to any potential within the input common-mode range of the converter. The analog signal conditioning required in transducer-based data acquisition systems is significantly simplified with this type of input flexibility. One converter package can now handle ground-referred inputs and true differential inputs as well as signals referred to a specific voltage. The analog input voltages for each channel can range from 50 mV below GND to 50 mV above V+ = DV+ = AV+ without degrading conversion accuracy. If the voltage on an unselected channel exceeds these limits it may corrupt the reading of the selected channel. 3.2 Reference Considerations The voltage difference between the VREF+ and VREF− inputs defines the analog input voltage span (the difference between VIN(Max) and VIN(Min)) over which 1023 positive and 1024 negative possible output codes apply. The value of the voltage on the VREF+ or VREF− inputs can be anywhere between AV+ + 50 mV and −50 mV, so long as VREF+ is greater than VREF−. The ADC10731/2/4/8 can be used in either ratiometric applications or in systems requiring absolute accuracy. The reference pins must be connected to a voltage source capable of driving the minimum reference input resistance of 5 kΩ. The internal 2.5V bandgap reference in the ADC10731/2/4/8 is available as an output on the VREFOut pin. To ensure optimum performance this output needs to be bypassed to ground with 100 µF aluminum electrolytic or tantalum capacitor. The reference output can be unstable with capacitive loads greater than 100 pF and less than 100 µF. Any capacitive loading less than 100 pF and greater than 100 µF will not cause oscillation. Lower output noise can be obtained by increasing the output capacitance. A 100 µF capacitor will yield a typical noise floor of . The pseudo-differential and differential multiplexer modes allow for more flexibility in the analog input voltage range since the “zero” reference voltage is set by the actual voltage applied to the assigned negative input pin. In a ratiometric system (Figure 14), the analog input voltage is proportional to the voltage used for the A/D reference. This voltage may also be the system power supply, so VREF+ can also be tied to AV+. This technique relaxes the stability requirements of the system reference as the analog input and A/D reference move together maintaining the same output code for a given input condition. For absolute accuracy (Figure 15), where the analog input varies between very specific voltage limits, the reference pin can be biased with a time- and temperature-stable voltage source that has excellent initial accuracy. The LM4040, LM4041 and LM185 references are suitable for use with the ADC10731/2/4/8. The minimum value of VREF (VREF = VREF+–VREF−) can be quite small (see Typical Performance Characteristics) to allow direct conversion of transducer outputs providing less than a 5V output span. Particular care must be taken with regard to noise pickup, circuit layout and system error voltage sources when operating with a reduced span due to the increased sensitivity of the converter (1 LSB equals VREF/ 1024). 3.3 The Analog Inputs Due to the sampling nature of the analog inputs, at the clock edges short duration spikes of current will be seen on the selected assigned negative input. Input bypass capacitors should not be used if the source resistance is greater than 1 kΩ since they will average the AC current and cause an effective DC current to flow through the analog input source resistance. An op amp RC active lowpass filter can provide both impedance buffering and noise filtering should a high impedance signal source be required. Bypass capacitors may be used when the source impedance is very low without any degradation in performance. In a true differential input stage, a signal that is common to both “+” and “−” inputs is canceled. For the ADC10731/2/4/8, the positive input of a selected channel pair is only sampled once before the start of a conversion during the acquisition time (tA). The negative input needs to be stable during the complete conversion sequence because it is sampled before each decision in the SAR sequence. Therefore, any AC common-mode signal present on the analog inputs will not be completely canceled and will cause some conversion errors. For a sinusoid common-mode signal this error is: VERROR(max) = VPEAK (2 π fCM) (tC) where fCM is the frequency of the common-mode signal, VPEAK is its peak voltage value, and tC is the A/D’s conversion time (tC = 12/fCLK). For example, for a 60 Hz commonmode signal to generate a 1⁄4 LSB error (0.61 mV) with a 4.8 µs conversion time, its peak value would have to be approximately 337 mV. www.national.com 22 ADC10731/ADC10732/ADC10734/ADC10738 Applications Hints (Continued) 4 Single-Ended 01139051 2 Differential 01139052 4 PsuedoDifferential 01139053 2 Single-Ended and 1 Differential 01139054 FIGURE 13. Analog Input Multiplexer Options 23 www.national.com ADC10731/ADC10732/ADC10734/ADC10738 Applications Hints (Continued) Ratiometric Using the Internal Reference 01139029 FIGURE 14. Absolute Using a 4.096V Span 01139030 FIGURE 15. Different Reference Configurations 3.4 Optional Adjustments 3.4.1 Zero Error The zero error of the A/D converter relates to the location of the first riser of the transfer function (see Figures 1, 2) and can be measured by grounding the minus input and applying a small magnitude voltage to the plus input. Zero error is the difference between actual DC input voltage which is necessary to just cause an output digital code transition from 000 0000 0000 to 000 0000 0001 and the ideal 1⁄2 LSB value (1⁄2 LSB = 1.22 mV for VREF = + 2.500V). The zero error of the A/D does not require adjustment. If the minimum analog input voltage value, VIN(Min), is not ground, the effective “zero” voltage can be adjusted to a convenient value. The converter can be made to output an all zeros digital code for this minimum input voltage by biasing any minus input to VIN(Min). This is useful for either the differential or pseudo-differential input channel configurations. 3.4.2 Full-Scale The full-scale adjustment can be made by applying a differential input voltage which is 11⁄2 LSB down from the desired analog full-scale voltage range and then adjusting the VREF 24 www.national.com ADC10731/ADC10732/ADC10734/ADC10738 Applications Hints (Continued) voltage (VREF = VREF+– VREF−) for a digital output code changing from 011 1111 1110 to 011 1111 1111. In bipolar signed operation this only adjusts the positive full scale error. 3.4.3 Adjusting for an Arbitrary Analog Input Voltage Range If the analog zero voltage of the A/D is shifted away from ground (for example, to accommodate an analog input signal which does not go to ground), this new zero reference should be properly adjusted first. A plus input voltage which equals this desired zero reference plus 1⁄2 LSB is applied to selected plus input and the zero reference voltage at the corresponding minus input should then be adjusted to just obtain the 000 0000 0000 to 000 0000 0001 code transition. The full-scale adjustment should be made [with the proper minus input voltage applied] by forcing a voltage to the plus input which is given by: This acquisition window of 4.5 clock cycles is available to allow the voltage on the capacitor array to settle to the positive analog input voltage. Any change in the analog voltage on a selected positive input before or after the acquisition window will not effect the A/D conversion result. In the simplest case, the array’s acquisition time is determined by the RON (3 kΩ) of the multiplexer switches, the stray input capacitance CS1 (3.5 pF) and the total array (CL) and stray (CS2) capacitance (48 pF). For a large source resistance the analog input can be modeled as an RC network as shown in Figure 16. The values shown yield an acquisition time of about 1.1 µs for 10-bit unipolar or 10-bit plus sign accuracy with a zero-to-full-scale change in the input voltage. External source resistance and capacitance will lengthen the acquisition time and should be accounted for. Slowing the clock will lengthen the acquisition time, thereby allowing a larger external source resistance. where VMAX equals the high end of the analog input range, VMIN equals the low end (the offset zero) of the analog range. Both VMAX and VMIN are ground referred. The VREF (VREF = VREF+ − VREF−) voltage is then adjusted to provide a code change from 011 1111 1110 to 011 1111 1111. Note, when using a pseudo-differential or differential multiplexer mode where VREF+ and VREF− are placed within the V+ and GND range, the individual values of VREF and VREF− do not matter, only the difference sets the analog input voltage span. This completes the adjustment procedure. 3.5 The Input Sample and Hold The ADC10731/2/4/8’s sample/hold capacitor is implemented in the capacitor array. After the channel address is loaded, the array is switched to sample the selected positive analog input. The sampling period for the assigned positive input is maintained for the duration of the acquisition time (tA) 4.5 clock cycles. 01139025 FIGURE 16. Analog Input Model The signal-to-noise ratio of an ideal A/D is the ratio of the RMS value of the full scale input signal amplitude to the value of the total error amplitude (including noise) caused by the transfer function of the ideal A/D. An ideal 10-bit plus sign A/D converter with a total unadjusted error of 0 LSB would have a signal-to-(noise + distortion) ratio of about 68 dB, which can be derived from the equation: S/(N + D) = 6.02(n) + 1.76 where S/(N + D) is in dB and n is the number of bits. 01139031 Note: Diodes are 1N914. Note: The protection diodes should be able to withstand the output current of the op amp under current limit. FIGURE 17. Protecting the Analog Inputs 25 www.national.com ADC10731/ADC10732/ADC10734/ADC10738 Applications Hints (Continued) 01139032 *1% resistors FIGURE 18. Zero-Shift and Span-Adjust for Signed or Unsigned, Single-Ended Multiplexer Assignment, Signed Analog Input Range of 0.5V ≤ VIN ≤ 4.5V www.national.com 26 ADC10731/ADC10732/ADC10734/ADC10738 Physical Dimensions inches (millimeters) unless otherwise noted Order Number ADC10731CIWM NS Package Number M16B 27 www.national.com ADC10731/ADC10732/ADC10734/ADC10738 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) Order Number ADC10732CIWM and ADC10734CIWM NS Package Number M20B Order Number ADC10738CIWM NS Package Number M24B www.national.com 28 ADC10731/ADC10732/ADC10734/ADC10738 10-Bit Plus Sign Serial I/O A/D Converters with Mux, Sample/Hold and Reference Physical Dimensions inches (millimeters) unless otherwise noted (Continued) Order Number ADC10734CIMSA NS Package Number MSA20 National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications. 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