ADC121S051

ADC121S051 Single Channel, 200 to 500 ksps, 12-Bit A/D Converter February 2006 ADC121S051 Single Channel, 200 to 500 ksps, 12-Bit A/D Converter General Description The ADC121S051 is a low-power, single channel CMOS 12-bit analog-to-digital converter with a high-speed serial interface. Unlike the conventional practice of specifying performance at a single sample rate only, the ADC121S051 is fully specified over a sample rate range of 200 ksps to 500 ksps. The converter is based upon a successiveapproximation register architecture with an internal trackand-hold circuit. The output serial data is straight binary, and is compatible with several standards, such as SPI™, QSPI™, MICROWIRE, and many common DSP serial interfaces. The ADC121S051 operates with a single supply that can range from +2.7V to +5.25V. Normal power consumption using a +3.6V or +5.25V supply is 1.7 mW and 8.7 mW, respectively. The power-down feature reduces the power consumption to as low as 2.6 µW using a +5.25V supply. The ADC121S051 is packaged in 6-lead LLP and SOT-23 packages. Operation over the industrial temperature range of −40˚C to +85˚C is guaranteed. Features n n n n n Specified over a range of sample rates. 6-lead LLP and SOT-23 packages Variable power management Single power supply with 2.7V - 5.25V range SPI™/QSPI™/MICROWIRE/DSP compatible Key Specifications n n n n DNL INL SNR Power Consumption — 3.6V Supply — 5.25V Supply +0.5/-0.25 LSB (typ) +0.45/-0.40 LSB (typ) 72.0 dB (typ) 1.7 mW (typ) 8.7 mW (typ) Applications n Portable Systems n Remote Data Acquisition n Instrumentation and Control Systems Pin-Compatible Alternatives by Resolution and Speed All devices are fully pin and function compatible. Resolution 50 to 200 ksps 12-bit 10-bit 8-bit ADC121S021 ADC101S021 ADC081S021 Specified for Sample Rate Range of: 200 to 500 ksps ADC121S051 ADC101S051 ADC081S051 500 ksps to 1 Msps ADC121S101 ADC101S101 ADC081S101 Connection Diagram 20144605 Ordering Information Order Code ADC121S051CISD ADC121S051CISDX ADC121S051CIMF ADC121S051CIMFX ADC121S051EVAL TRI-STATE ® is a trademark of National Semiconductor Corporation QSPI™ and SPI™ are trademarks of Motorola, Inc. Temperature Range −40˚C to +85˚C −40˚C to +85˚C −40˚C to +85˚C −40˚C to +85˚C Description 6-Lead LLP Package 6-Lead LLP Package, Tape and Reel 6-Lead SOT-23 Package 6-Lead SOT-23 Package, Tape & Reel SOT-23 Evaluation Board Top Mark X4C X4C X13C X13C © 2006 National Semiconductor Corporation DS201446 www.national.com ADC121S051 Block Diagram 20144607 Pin Descriptions and Equivalent Circuits Pin No. ANALOG I/O 3 DIGITAL I/O 4 5 6 POWER SUPPLY 1 2 PAD VA GND GND Positive supply pin. This pin should be connected to a quiet +2.7V to +5.25V source and bypassed to GND with a 1 µF capacitor and a 0.1 µF monolithic capacitor located within 1 cm of the power pin. The ground return for the supply and signals. For package suffix CISD(X) only, it is recommended that the center pad should be connected to ground. SCLK SDATA CS Digital clock input. This clock directly controls the conversion and readout processes. Digital data output. The output samples are clocked out of this pin on falling edges of the SCLK pin. Chip select. On the falling edge of CS, a conversion process begins. VIN Analog input. This signal can range from 0V to VA. Symbol Description www.national.com 2 ADC121S051 Absolute Maximum Ratings (Notes 1, 2) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Analog Supply Voltage VA Voltage on Any Digital Pin to GND Voltage on Any Analog Pin to GND Input Current at Any Pin (Note 3) Package Input Current (Note 3) Power Consumption at TA = 25˚C ESD Susceptibility (Note 5) Human Body Model Machine Model Junction Temperature Storage Temperature −0.3V to 6.5V −0.3V to 6.5V −0.3V to (VA +0.3V) Operating Ratings (Notes 1, 2) Operating Temperature Range VA Supply Voltage Digital Input Pins Voltage Range (regardless of supply voltage) Analog Input Pins Voltage Range Clock Frequency Sample Rate −40˚C ≤ TA ≤ +85˚C +2.7V to +5.25V −0.3V to +5.25V 0V to VA 1 MHz to 10 MHz up to 500 ksps ± 10 mA ± 20 mA See (Note 4) 3500V 300V +150˚C −65˚C to +150˚C Package Thermal Resistance Package 6-lead LLP 6-lead SOT-23 θJA 94˚C / W 265˚C / W Soldering process must comply with National Semiconductor’s Reflow Temperature Profile specifications. Refer to www.national.com/packaging. (Note 6) ADC121S051 Converter Electrical Characteristics (Notes 7, 9) The following specifications apply for VA = +2.7V to 5.25V, fSCLK = 4 MHz to 10 MHz, fSAMPLE = 200 ksps to 500 ksps, CL = 15 pF, unless otherwise noted. Boldface limits apply for TA = TMIN to TMAX: all other limits TA = 25˚C. Symbol Parameter Conditions Typical Limits (Note 9) 12 VA = +2.7V to +3.6V INL Integral Non-Linearity VA = +4.75 to +5.25V VA = +2.7V to +3.6V DNL Differential Non-Linearity VA = +4.75 to +5.25V VOFF GE Offset Error Gain Error VA = +2.7V to +3.6V VA = +4.75 to +5.25V VA = +2.7V to +3.6V VA = +4.75 to +5.25V VA = +2.7V to 5.25V fIN = 100 kHz, −0.02 dBFS VA = +2.7V to 5.25V fIN = 100 kHz, −0.02 dBFS VA = +2.7V to 5.25V fIN = 100 kHz, −0.02 dBFS VA = +2.7V to 5.25V fIN = 100 kHz, −0.02 dBFS VA = +2.7V to 5.25V fIN = 100 kHz, −0.02 dBFS VA = +5.25V fa = 103.5 kHz, fb = 113.5 kHz VA = +5.25V fa = 103.5 kHz, fb = 113.5 kHz +0.45 −0.40 +0.75 −0.45 +0.50 −0.25 +0.80 −0.50 −0.18 +1.9 −0.62 −1.50 +1.0 −0.9 Units STATIC CONVERTER CHARACTERISTICS Resolution with No Missing Codes Bits LSB (max) LSB (min) LSB (max) LSB (min) LSB (max) LSB (min) LSB (max) LSB (min) ± 1.0 ± 1.2 ± 1.5 LSB (max) LSB (max) DYNAMIC CONVERTER CHARACTERISTICS SINAD SNR THD SFDR ENOB Signal-to-Noise Plus Distortion Ratio Signal-to-Noise Ratio Total Harmonic Distortion Spurious-Free Dynamic Range Effective Number of Bits Intermodulation Distortion, Second Order Terms Intermodulation Distortion, Third Order Terms 72 72 −83 84 11.7 −83 −82 11.3 70 70.8 dB (min) dB (min) dB dB Bits (min) dB dB IMD 3 www.national.com ADC121S051 ADC121S051 Converter Electrical Characteristics (Notes 7, 9) (Continued) The following specifications apply for VA = +2.7V to 5.25V, fSCLK = 4 MHz to 10 MHz, fSAMPLE = 200 ksps to 500 ksps, CL = 15 pF, unless otherwise noted. Boldface limits apply for TA = TMIN to TMAX: all other limits TA = 25˚C. Parameter Conditions Typical Limits (Note 9) Units Symbol DYNAMIC CONVERTER CHARACTERISTICS FPBW -3 dB Full Power Bandwidth VA = +5V VA = +3V 11 8 0 to VA MHz MHz V ANALOG INPUT CHARACTERISTICS VIN IDCL CINA Input Range DC Leakage Current Input Capacitance Track Mode Hold Mode VA = +5.25V VA = +3.6V VA = +5V VA = +3V VIN = 0V or VA 30 4 2.4 2.1 0.8 0.4 ±1 µA (max) pF pF V (min) V (min) V (max) V (max) µA (max) pF (max) V (min) V V (max) V DIGITAL INPUT CHARACTERISTICS VIH VIL IIN CIND Input High Voltage Input Low Voltage Input Current Digital Input Capacitance ISOURCE = 200 µA ISOURCE = 1 mA ISINK = 200 µA ISINK = 1 mA ± 0.1 2 VA − 0.07 VA − 0.1 0.03 0.1 ±1 4 VA − 0.2 0.4 DIGITAL OUTPUT CHARACTERISTICS VOH VOL IOZH, IOZL COUT Output High Voltage Output Low Voltage TRI-STATE ® Leakage Current TRI-STATE ® Output Capacitance Output Coding POWER SUPPLY CHARACTERISTICS VA Supply Voltage VA = +5.25V, fSAMPLE = 200 ksps VA = +3.6V, fSAMPLE = 200 ksps VA = +5.25V, fSCLK = 0 MHz, fSAMPLE = 0 ksps VA = +5.25V, fSCLK = 10 MHz, fSAMPLE = 0 ksps VA = +5.25V VA = +3.6V VA = +5.25V, fSCLK = 0 MHz, fSAMPLE = 0 ksps VA = +5.25V, fSCLK = 10 MHz, fSAMPLE = 0 ksps 1.66 0.46 500 60 8.7 1.7 2.6 315 15.8 4.7 2.7 5.25 3.0 1.3 V (min) V (max) mA (max) mA (max) nA µA mW (max) mW (max) µW µW ± 0.1 2 ± 10 4 µA (max) pF (max) Straight (Natural) Binary Supply Current, Normal Mode (Operational, CS low) IA Supply Current, Shutdown (CS high) Power Consumption, Normal Mode (Operational, CS low) PD Power Consumption, Shutdown (CS high) AC ELECTRICAL CHARACTERISTICS fSCLK fS tCONV Clock Frequency Sample Rate Conversion Time (Note 8) (Note 8) 4 10 200 500 16 MHz (min) MHz (max) ksps (min) ksps (max) SCLK cycles www.national.com 4 ADC121S051 ADC121S051 Converter Electrical Characteristics (Notes 7, 9) (Continued) The following specifications apply for VA = +2.7V to 5.25V, fSCLK = 4 MHz to 10 MHz, fSAMPLE = 200 ksps to 500 ksps, CL = 15 pF, unless otherwise noted. Boldface limits apply for TA = TMIN to TMAX: all other limits TA = 25˚C. Parameter Conditions Typical Limits (Note 9) 40 60 400 Acquisition Time + Conversion Time 3 30 20 50 Units Symbol AC ELECTRICAL CHARACTERISTICS DC tACQ tQUIET tAD tAJ SCLK Duty Cycle Track/Hold Acquisition Time Throughput Time (Note 10) Aperture Delay Aperture Jitter fSCLK = 10 MHz 50 % (min) % (max) ns (max) SCLK cycles ns (min) ns ps ADC121S051 Timing Specifications The following specifications apply for VA = +2.7V to 5.25V, GND = 0V, fSCLK = 4.0 MHz to 10.0 MHz, CL = 25 pF, fSAMPLE = 200 ksps to 500 ksps, Boldface limits apply for TA = TMIN to TMAX: all other limits TA = 25˚C. Symbol tCS tSU tEN tACC tCL tCH tH Parameter Minimum CS Pulse Width CS to SCLK Setup Time Delay from CS Until SDATA TRI-STATE ® Disabled (Note 11) Data Access Time after SCLK Falling Edge (Note 12) SCLK Low Pulse Width SCLK High Pulse Width SCLK to Data Valid Hold Time VA = +2.7V to +3.6V VA = +4.75V to +5.25V VA = +2.7V to +3.6V VA = +4.75V to +5.25V 1 VA = +2.7V to +3.6V VA = +4.75V to +5.25V Conditions Typical Limits 10 10 20 40 20 0.4 x tSCLK 0.4 x tSCLK 7 5 25 6 25 5 Units ns (min) ns (min) ns (max) ns (max) ns (max) ns (min) ns (min) ns (min) ns (min) ns (max) ns (min) ns (max) ns (min) µs tDIS SCLK Falling Edge to SDATA High Impedance (Note 13) Power-Up Time from Full Power-Down tPOWER-UP Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions. Note 2: All voltages are measured with respect to GND = 0V, unless otherwise specified. Note 3: When the input voltage at any pin exceeds the power supply (that is, VIN < GND or VIN > VA), the current at that pin should be limited to 10 mA. The 20 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 10 mA to two. The Absolute Maximum Rating specification does not apply to the VA pin. The current into the VA pin is limited by the Analog Supply Voltage specification. Note 4: The absolute maximum junction temperature (TJmax) for this device is 150˚C. The maximum allowable power dissipation is dictated by TJmax, the junction-to-ambient thermal resistance (θJA), and the ambient temperature (TA), and can be calculated using the formula PDmax = (TJmax − TA) / θJA. The values for maximum power dissipation listed above will be reached only when the device is operated in a severe fault condition (e.g. when input or output pins are driven beyond the power supply voltages, or the power supply polarity is reversed). Obviously, such conditions should always be avoided. Note 5: Human body model is 100 pF capacitor discharged through a 1.5 kΩ resistor. Machine model is 220 pF discharged through zero ohms. Note 6: Reflow temperature profiles are different for lead-free and non-lead-free packages. Note 7: Tested limits are guaranteed to National’s AOQL (Average Outgoing Quality Level). Note 8: This is the frequency range over which the electrical performance is guaranteed. The device is functional over a wider range which is specified under Operating Ratings. Note 9: Data sheet min/max specification limits are guaranteed by design, test, or statistical analysis. Note 10: Minimum Quiet Time required by bus relinquish and the start of the next conversion. Note 11: Measured with the timing test circuit shown in Figure 1 and defined as the time taken by the output signal to cross 1.0V. Note 12: Measured with the timing test circuit shown in Figure 1 and defined as the time taken by the output signal to cross 1.0V or 2.0V. Note 13: tDIS is derived from the time taken by the outputs to change by 0.5V with the timing test circuit shown in Figure 1. The measured number is then adjusted to remove the effects of charging or discharging the output capacitance. This means that tDIS is the true bus relinquish time, independent of the bus loading. 5 www.national.com ADC121S051 Timing Diagrams 20144608 FIGURE 1. Timing Test Circuit 20144606 FIGURE 2. ADC121S051 Serial Timing Diagram www.national.com 6 ADC121S051 Specification Definitions ACQUISITION TIME is the time required to acquire the input voltage. That is, it is time required for the hold capacitor to charge up to the input voltage. APERTURE DELAY is the time between the fourth falling SCLK edge of a conversion and the time when the input signal is acquired or held for conversion. APERTURE JITTER (APERTURE UNCERTAINTY) is the variation in aperture delay from sample to sample. Aperture jitter manifests itself as noise in the output. CONVERSION TIME is the time required, after the input voltage is acquired, for the ADC to convert the input voltage to a digital word. DIFFERENTIAL NON-LINEARITY (DNL) is the measure of the maximum deviation from the ideal step size of 1 LSB. DUTY CYCLE is the ratio of the time that a repetitive digital waveform is high to the total time of one period. The specification here refers to the SCLK. EFFECTIVE NUMBER OF BITS (ENOB, or EFFECTIVE BITS) is another method of specifying Signal-to-Noise and Distortion or SINAD. ENOB is defined as (SINAD − 1.76) / 6.02 and says that the converter is equivalent to a perfect ADC of this (ENOB) number of bits. FULL POWER BANDWIDTH is a measure of the frequency at which the reconstructed output fundamental drops 3 dB below its low frequency value for a full scale input. GAIN ERROR is the deviation of the last code transition (111...110) to (111...111) from the ideal (VREF − 1.5 LSB), after adjusting for offset error. INTEGRAL NON-LINEARITY (INL) is a measure of the deviation of each individual code from a line drawn from negative full scale (1⁄2 LSB below the first code transition) through positive full scale (1⁄2 LSB above the last code transition). The deviation of any given code from this straight line is measured from the center of that code value. INTERMODULATION DISTORTION (IMD) is the creation of additional spectral components as a result of two sinusoidal frequencies being applied to the ADC input at the same time. It is defined as the ratio of the power in the second and third order intermodulation products to the sum of the power in both of the original frequencies. IMD is usually expressed in dB. MISSING CODES are those output codes that will never appear at the ADC outputs. The ADC121S051 is guaranteed not to have any missing codes. OFFSET ERROR is the deviation of the first code transition (000...000) to (000...001) from the ideal (i.e. GND + 0.5 LSB). SIGNAL TO NOISE RATIO (SNR) is the ratio, expressed in dB, of the rms value of the input signal to the rms value of the sum of all other spectral components below one-half the sampling frequency, not including harmonics or d.c. SIGNAL TO NOISE PLUS DISTORTION (S/N+D or SINAD) Is the ratio, expressed in dB, of the rms value of the input signal to the rms value of all of the other spectral components below half the clock frequency, including harmonics but excluding d.c. SPURIOUS FREE DYNAMIC RANGE (SFDR) is the difference, expressed in dB, between the desired signal amplitude to the amplitude of the peak spurious spectral component, where a spurious spectral component is any signal present in the output spectrum that is not present at the input and may or may not be a harmonic. TOTAL HARMONIC DISTORTION (THD) is the ratio, expressed in dB or dBc, of the rms total of the first five harmonic components at the output to the rms level of the input signal frequency as seen at the output. THD is calculated as where Af1 is the RMS power of the input frequency at the output and Af2 through Af6 are the RMS power in the first 5 harmonic frequencies. THROUGHPUT TIME is the minimum time required between the start of two successive conversion. It is the acquisition time plus the conversion time. 7 www.national.com ADC121S051 Typical Performance Characteristics TA = +25˚C, fSAMPLE = 200 ksps to 500 ksps, fSCLK = 4 MHz to 10 MHz, fIN = 100 kHz unless otherwise stated. DNL fSCLK = 4 MHz INL fSCLK = 4 MHz 20144620 20144621 DNL fSCLK = 10 MHz INL fSCLK = 10 MHz 20144660 20144661 DNL vs. Clock Frequency INL vs. Clock Frequency 20144665 20144666 www.national.com 8 ADC121S051 Typical Performance Characteristics TA = +25˚C, fSAMPLE = 200 ksps to 500 ksps, fSCLK = 4 MHz to 10 MHz, fIN = 100 kHz unless otherwise stated. (Continued) SNR vs. Clock Frequency SINAD vs. Clock Frequency 20144663 20144664 SFDR vs. Clock Frequency THD vs. Clock Frequency 20144667 20144668 Spectral Response, VA = 5.25V fSCLK = 4 MHz Spectral Response, VA = 5.25V fSCLK = 10 MHz 20144669 20144670 9 www.national.com ADC121S051 Typical Performance Characteristics TA = +25˚C, fSAMPLE = 200 ksps to 500 ksps, fSCLK = 4 MHz to 10 MHz, fIN = 100 kHz unless otherwise stated. (Continued) Power Consumption vs. Throughput, fSCLK = 10 MHz 20144655 www.national.com 10 ADC121S051 Applications Information 1.0 ADC121S051 OPERATION The ADC121S051 is a successive-approximation analog-todigital converters designed around a charge-redistribution digital-to-analog converter core. Simplified schematics of the ADC121S051 in both track and hold modes are shown in Figure 3 and Figure 4, respectively. In Figure 3, the device is in track mode: switch SW1 connects the sampling capacitor to the input, and SW2 balances the comparator inputs. The device is in this state until CS is brought low, at which point the device moves to the hold mode. Figure 4 shows the device in hold mode: switch SW1 connects the sampling capacitor to ground, maintaining the sampled voltage, and switch SW2 unbalances the comparator. The control logic then instructs the charge-redistribution DAC to add or subtract fixed amounts of charge from the sampling capacitor until the comparator is balanced. When the comparator is balanced, the digital word supplied to the DAC is the digital representation of the analog input voltage. The device moves from hold mode to track mode on the 13th rising edge of SCLK. 20144609 FIGURE 3. ADC121S051 in Track Mode 20144610 FIGURE 4. ADC121S051 in Hold Mode 2.0 USING THE ADC121S051 The serial interface timing diagram for the ADC121S051 is shown in Figure 2. CS is chip select, which initiates conversions on the ADC121S051 and frames the serial data transfers. SCLK (serial clock) controls both the conversion process and the timing of serial data. SDATA is the serial data out pin, where a conversion result is found as a serial data stream. Basic operation of the ADC121S051 begins with CS going low, which initiates a conversion process and data transfer. Subsequent rising and falling edges of SCLK will be labelled with reference to the falling edge of CS; for example, "the third falling edge of SCLK" shall refer to the third falling edge of SCLK after CS goes low. At the fall of CS, the SDATA pin comes out of TRI-STATE, and the converter moves from track mode to hold mode. The input signal is sampled and held for conversion on the falling edge of CS. The converter moves from hold mode to track mode on the 13th rising edge of SCLK (see Figure 2). The SDATA pin will be placed back into TRI-STATE after the 16th falling edge of SCLK, or at the rising edge of CS, whichever occurs first. After a conversion is completed, the quiet time (tQUIET) must be satisfied before bringing CS low again to begin another conversion. Sixteen SCLK cycles are required to read a complete sample from the ADC121S051. The sample bits (including leading zeroes) are clocked out on falling edges of SCLK, and are intended to be clocked in by a receiver on subsequent falling edges of SCLK. The ADC121S051 will produce three leading zero bits on SDATA, followed by twelve data bits, most significant first. If CS goes low before the rising edge of SCLK, an additional (fourth) zero bit may be captured by the next falling edge of SCLK. 11 www.national.com ADC121S051 Applications Information 3.0 ADC121S051 TRANSFER FUNCTION (Continued) 5.0 ANALOG INPUTS An equivalent circuit for the ADC121S051’s input is shown in Figure 7. Diodes D1 and D2 provide ESD protection for the analog inputs. At no time should the analog input go beyond (VA + 300 mV) or (GND − 300 mV), as these ESD diodes will begin conducting, which could result in erratic operation. The capacitor C1 in Figure 7 has a typical value of 4 pF, and is mainly the package pin capacitance. Resistor R1 is the on resistance of the track / hold switch, and is typically 500 ohms. Capacitor C2 is the ADC121S051 sampling capacitor and is typically 26 pF. The ADC121S051 will deliver best performance when driven by a low-impedance source to eliminate distortion caused by the charging of the sampling capacitance. This is especially important when using the ADC121S051 to sample AC signals. Also important when sampling dynamic signals is an anti-aliasing filter. The output format of the ADC121S051 is straight binary. Code transitions occur midway between successive integer LSB values. The LSB width for the ADC121S051 is VA/4096. The ideal transfer characteristic is shown in Figure 5. The transition from an output code of 0000 0000 0000 to a code of 0000 0000 0001 is at 1/2 LSB, or a voltage of VA/8192. Other code transitions occur at steps of one LSB. 20144611 20144614 FIGURE 5. Ideal Transfer Characteristic 4.0 TYPICAL APPLICATION CIRCUIT A typical application of the ADC121S051 is shown in Figure 6. Power is provided in this example by the National Semiconductor LP2950 low-dropout voltage regulator, available in a variety of fixed and adjustable output voltages. The power supply pin is bypassed with a capacitor network located close to the ADC121S051. Because the reference for the ADC121S051 is the supply voltage, any noise on the supply will degrade device noise performance. To keep noise off the supply, use a dedicated linear regulator for this device, or provide sufficient decoupling from other circuitry to keep noise off the ADC121S051 supply pin. Because of the ADC121S051’s low power requirements, it is also possible to use a precision reference as a power supply to maximize performance. The three-wire interface is shown connected to a microprocessor or DSP. FIGURE 7. Equivalent Input Circuit 6.0 DIGITAL INPUTS AND OUTPUTS The ADC121S051 digital inputs (SCLK and CS) are not limited by the same maximum ratings as the analog inputs. The digital input pins are instead limited to +5.25V with respect to GND, regardless of VA, the supply voltage. This allows the ADC121S051 to be interfaced with a wide range of logic levels, independent of the supply voltage. 7.0 MODES OF OPERATION The ADC121S051 has two possible modes of operation: normal mode, and shutdown mode. The ADC121S051 enters normal mode (and a conversion process is begun) when CS is pulled low. The device will enter shutdown mode if CS is pulled high before the tenth falling edge of SCLK after CS is pulled low, or will stay in normal mode if CS remains low. Once in shutdown mode, the device will stay there until CS is brought low again. By varying the ratio of time spent in the normal and shutdown modes, a system may trade-off throughput for power consumption, with a sample rate as low as zero. 7.1 Normal Mode The fastest possible throughput is obtained by leaving the ADC121S051 in normal mode at all times, so there are no power-up delays. To keep the device in normal mode continuously, CS must be kept low until after the 10th falling edge of SCLK after the start of a conversion (remember that a conversion is initiated by bringing CS low). If CS is brought high after the 10th falling edge, but before the 16th falling edge, the device will remain in normal mode, but the current conversion will be aborted, and SDATA will return to TRI-STATE (truncating the output word). Sixteen SCLK cycles are required to read all of a conversion word from the device. After sixteen SCLK cycles have 12 20144613 FIGURE 6. Typical Application Circuit www.national.com ADC121S051 Applications Information (Continued) elapsed, CS may be idled either high or low until the next conversion. If CS is idled low, it must be brought high again before the start of the next conversion, which begins when CS is again brought low. After sixteen SCLK cycles, SDATA returns to TRI-STATE. Another conversion may be started, after tQUIET has elapsed, by bringing CS low again. 7.2 Shutdown Mode Shutdown mode is appropriate for applications that either do not sample continuously, or it is acceptable to trade throughput for power consumption. When the ADC121S051 is in shutdown mode, all of the analog circuitry is turned off. To enter shutdown mode, a conversion must be interrupted by bringing CS high anytime between the second and tenth falling edges of SCLK, as shown in Figure 8. Once CS has been brought high in this manner, the device will enter shutdown mode; the current conversion will be aborted and SDATA will enter TRI-STATE. If CS is brought high before the second falling edge of SCLK, the device will not change mode; this is to avoid accidentally changing mode as a result of noise on the CS line. 20144616 FIGURE 8. Entering Shutdown Mode 20144617 FIGURE 9. Entering Normal Mode To exit shutdown mode, bring CS back low. Upon bringing CS low, the ADC121S051 will begin powering up (power-up time is specified in the Timing Specifications table). This power-up delay results in the first conversion result being unusable. The second conversion performed after power-up, however, is valid, as shown in Figure 9. If CS is brought back high before the 10th falling edge of SCLK, the device will return to shutdown mode. This is done to avoid accidentally entering normal mode as a result of noise on the CS line. To exit shutdown mode and remain in normal mode, CS must be kept low until after the 10th falling edge of SCLK. The ADC121S051 will be fully powered-up after 16 SCLK cycles. 8.0 POWER MANAGEMENT The ADC121S051 takes time to power-up, either after first applying VA, or after returning to normal mode from shutdown mode. This corresponds to one "dummy" conversion for any SCLK frequency within the specifications in this document. After this first dummy conversion, the ADC121S051 will perform conversions properly. Note that the tQUIET time must still be included between the first dummy conversion and the second valid conversion. 13 When the VA supply is first applied, the ADC121S051 may power up in either of the two modes: normal or shutdown. As such, one dummy conversion should be performed after start-up, as described in the previous paragraph. The part may then be placed into either normal mode or the shutdown mode, as described in Sections 7.1 and 7.2. When the ADC121S051 is operated continuously in normal mode, the maximum throughput is fSCLK / 20. Throughput may be traded for power consumption by running fSCLK at its maximum specified rate and performing fewer conversions per unit time, raising the ADC121S051 CS line after the 10th and before the 15th fall of SCLK of each conversion. A plot of typical power consumption versus throughput is shown in the Typical Performance Curves section. To calculate the power consumption for a given throughput, multiply the fraction of time spent in the normal mode by the normal mode power consumption and add the fraction of time spent in shutdown mode multiplied by the shutdown mode power consumption. Note that the curve of power consumption vs. throughput is essentially linear. This is because the power consumption in the shutdown mode is so small that it can be ignored for all practical purposes. www.national.com ADC121S051 Applications Information (Continued) 9.0 POWER SUPPLY NOISE CONSIDERATIONS The charging of any output load capacitance requires current from the power supply, VA. The current pulses required from the supply to charge the output capacitance will cause voltage variations on the supply. If these variations are large enough, they could degrade SNR and SINAD performance of the ADC. Furthermore, discharging the output capacitance when the digital output goes from a logic high to a logic low will dump current into the die substrate, which is resistive. Load discharge currents will cause "ground bounce" noise in the substrate that will degrade noise performance if that current is large enough. The larger the output capacitance, the more current flows through the die substrate and the greater is the noise coupled into the analog channel, degrading noise performance. To keep noise out of the power supply, keep the output load capacitance as small as practical. It is good practice to use a 100 Ω series resistor at the ADC output, located as close to the ADC output pin as practical. This will limit the charge and discharge current of the output capacitance and improve noise performance. www.national.com 14 ADC121S051 Physical Dimensions inches (millimeters) unless otherwise noted 6-Lead LLP Order Number ADC121S051CISD or ADC121S051CISDX NS Package Number SDB06A 6-Lead SOT-23 Order Number ADC121S051CIMF, ADC121S051CIMFX NS Package Number MF06A 15 www.national.com ADC121S051 Single Channel, 200 to 500 ksps, 12-Bit A/D Converter Notes National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications. For the most current product information visit us at www.national.com. LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. 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