ADC124S051

ADC124S051 4 Channel, 500 kSPS, 12-Bit A/D Converter April 2005 ADC124S051 4 Channel, 500 kSPS, 12-Bit A/D Converter General Description The ADC124S051 is a low-power, four-channel CMOS 12-bit analog-to-digital converter with a high-speed serial interface. Unlike the conventional practice of specifying performance at a single sample rate only, the ADC124S051 is fully specified over a sample rate range of 200 kSPS to 500 kSPS. The converter is based on a successive-approximation register architecture with an internal track-and-hold circuit. It can be configured to accept up to four input signals at inputs IN1 through IN4. The output serial data is straight binary, and is compatible with several standards, such as SPI™, QSPI™, MICROWIRE and many common DSP serial interfaces. The ADC124S051 operates with a single supply that can range from +2.7V to +5.25V. Normal power consumption using a +3V or +5V supply is 3.0 mW and 10.0 mW, respectively. The power-down feature reduces the power consumption to just 0.14 µW using a +3V supply, or 0.32 µW using a +5V supply. The ADC124S051 is packaged in a 10-lead MSOP package. Operation over the industrial temperature range of −40˚C to +85˚C is guaranteed. Features n n n n Specified over a range of sample rates. Four input channels Variable power management Single power supply with 2.7V - 5.25V range Key Specifications n n n n DNL INL SNR Power Consumption — 3V Supply — 5V Supply +0.7 / −0.4 LSB (typ) ± 0.5 LSB (typ) 72.5 dB (typ) 3.0 mW (typ) 10.0 mW (typ) Applications n Portable Systems n Remote Data Aquisitions n Instrumentation and Control Systems Pin-Compatible Alternatives by Resolution and Speed All devices are fully pin and function compatible. Resolution 50 to 200 kSPS 12-bit 10-bit 8-bit ADC124S021 ADC104S021 ADC084S021 Specified for a Sample Rate Range of: 200 to 500 kSPS ADC124S051 ADC104S051 ADC084S051 500 kSPS to 1 MSPS ADC122S101 ADC102S101 ADC082S101 Connection Diagram 20111305 TRI-STATE ® is a trademark of National Semiconductor Corporation QSPI™ and SPI™ are trademarks of Motorola, Inc. © 2005 National Semiconductor Corporation DS201113 www.national.com ADC124S051 Ordering Information Order Code ADC124S051CIMM ADC124S051CIMMX ADC124S051EVAL Temperature Range −40˚C to +85˚C −40˚C to +85˚C Description 10-Lead MSOP Package 10-Lead MSOP Package, Tape & Reel Evaluation Board Top Mark X12C X12C Block Diagram 20111307 Pin Descriptions and Equivalent Circuits Pin No. ANALOG I/O 4-7 DIGITAL I/O 10 9 8 1 POWER SUPPLY Positive supply pin. This pin should be connected to a quiet +2.7V to +5.25V source and bypassed to GND with a 1 µF tantalum capacitor and a 0.1 µF ceramic monolithic capacitor located within 1 cm of the power pin. The ground return for the analog supply and signals. SCLK DOUT DIN CS Digital clock input. This clock directly controls the conversion and readout processes. Digital data output. The output samples are clocked out of this pin on falling edges of the SCLK pin. Digital data input. The ADC124S051’s Control Register is loaded through this pin on rising edges of the SCLK pin. Chip select. On the falling edge of CS, a conversion process begins. Conversions continue as long as CS is held low. IN1 to IN4 Analog inputs. These signals can range from 0V to VA. Symbol Description 2 VA 3 GND www.national.com 2 ADC124S051 Absolute Maximum Ratings (Notes 1, 2) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage VA Voltage on Any Pin to GND Input Current at Any Pin (Note 3) Package Input Current(Note 3) Power Consumption at TA = 25˚C ESD Susceptibility (Note 5) Human Body Model Machine Model Junction Temperature Storage Temperature −0.3V to 6.5V −0.3V to VA +0.3V Operating Ratings (Notes 1, 2) Operating Temperature Range VA Supply Voltage Digital Input Pins Voltage Range Clock Frequency Analog Input Voltage −40˚C ≤ TA ≤ +85˚C +2.7V to +5.25V −0.3V to VA 0.8 MHz to 8 MHz 0V to VA ± 10 mA ± 20 mA See (Note 4) 2500V 250V +150˚C −65˚C to +150˚C Package Thermal Resistance Package 10-lead MSOP θJA 190˚C / W Soldering process must comply with National Semiconductor’s Reflow Temperature Profile specifications. Refer to www.national.com/packaging. (Note 6) (Note 9) The following specifications apply for VA = +2.7V to 5.25V, GND = 0V, fSCLK = 3.2 MHz to 8 MHz, fSAMPLE = 200 to 500 kSPS, CL = 35 pF, unless otherwise noted. Boldface limits apply for TA = TMIN to TMAX: all other limits TA = 25˚C. Symbol Parameter Conditions Typical Limits (Note 7) 12 Units ADC124S051 Converter Electrical Characteristics STATIC CONVERTER CHARACTERISTICS Resolution with No Missing Codes INL DNL VOFF OEM FSE FSEM Integral Non-Linearity Differential Non-Linearity Offset Error Channel to Channel Offset Error Match Full Scale Error Channel to Channel Full-Scale Error Match VA = +2.7 to 5.25V fIN = 40.2 kHz, −0.02 dBFS VA = +2.7 to 5.25V fIN = 40.2 kHz, −0.02 dBFS VA = +2.7 to 5.25V fIN = 40.2 kHz, −0.02 dBFS VA = +2.7 to 5.25V fIN = 40.2 kHz, −0.02 dBFS VA = +2.7 to 5.25V VA = +5.25V fIN = 40.2 kHz VA = +5.25V fa = 40.161 kHz, fb = 41.015 kHz VA = +5.25V fa = 40.161 kHz, fb = 41.015 kHz VA = +5V VA = +3V Bits LSB (max) LSB (max) LSB (min) LSB (max) LSB (max) LSB (max) LSB (max) ± 0.5 +0.7 −0.4 +0.3 ± 1.1 +1.3 −1.0 ± 1.3 ± 1.0 ± 1.5 ± 1.0 ± 0.1 −0.5 +0.1 DYNAMIC CONVERTER CHARACTERISTICS SINAD SNR THD SFDR ENOB Signal-to-Noise Plus Distortion Ratio Signal-to-Noise Ratio Total Harmonic Distortion Spurious-Free Dynamic Range Effective Number of Bits Channel-to-Channel Crosstalk Intermodulation Distortion, Second Order Terms Intermodulation Distortion, Third Order Terms -3 dB Full Power Bandwidth 72 72.5 −84 86 11.7 −86 −87 −88 11 8 69.2 70.6 −75 76 11.2 dB (min) dB (min) dB (max) dB (min) Bits (min) dB dB dB MHz MHz IMD FPBW 3 www.national.com ADC124S051 ADC124S051 Converter Electrical Characteristics (Note 9) (Continued) The following specifications apply for VA = +2.7V to 5.25V, GND = 0V, fSCLK = 3.2 MHz to 8 MHz, fSAMPLE = 200 to 500 kSPS, CL = 35 pF, unless otherwise noted. Boldface limits apply for TA = TMIN to TMAX: all other limits TA = 25˚C. Parameter Conditions Typical Limits (Note 7) Units Symbol ANALOG INPUT CHARACTERISTICS VIN IDCL CINA Input Range DC Leakage Current Input Capacitance Track Mode Hold Mode VA = +5.25V VA = +3.6V VIN = 0V or VA 0 to VA V ± 0.02 33 3 ±1 µA (max) pF pF DIGITAL INPUT CHARACTERISTICS VIH VIL IIN CIND Input High Voltage Input Low Voltage Input Current Digital Input Capacitance ISOURCE = 200 µA ISOURCE = 1 mA ISINK = 200 µA ISINK = 1 mA 2.4 2.1 0.8 V (min) V (min) V (max) µA (max) pF (max) V (min) V 0.4 V (max) V ± 0.02 2 VA − 0.03 VA − 0.10 0.02 0.1 0.005 2 ± 10 4 VA − 0.5 DIGITAL OUTPUT CHARACTERISTICS VOH VOL IOZH, IOZL COUT Output High Voltage Output Low Voltage TRI-STATE ® Leakage Current TRI-STATE ® Output Capacitance Output Coding POWER SUPPLY CHARACTERISTICS (CL = 10 pF) VA Supply Voltage VA = +5.25V, fSAMPLE = 500 kSPS, fIN = 40 kHz VA = +3.6V, fSAMPLE = 500 kSPS, fIN = 40 kHz VA = +5.25V, fSAMPLE = 0 kSPS VA = +3.6V, fSAMPLE = 0 kSPS VA = +5.25V VA = +3.6V VA = +5.25V VA = +3.6V 1.9 0.84 60 38 10 3.0 0.32 0.14 3.2 8 200 500 13 fSCLK = 8 MHz Full-Scale Step Input Acquisition Time + Conversion Time 50 30 70 3 16 12.6 4.3 2.7 5.25 2.4 1.2 V (min) V (max) mA (max) mA (max) nA nA mW (max) mW (max) µW µW MHz (min) MHz (max) kSPS (min) kSPS (max) SCLK cycles % (min) % (max) SCLK cycles SCLK cycles ±1 4 µA (max) pF (max) Straight (Natural) Binary Supply Current, Normal Mode (Operational, CS low) IA Supply Current, Shutdown (CS high) PD Power Consumption, Normal Mode (Operational, CS low) Power Consumption, Shutdown (CS high) AC ELECTRICAL CHARACTERISTICS fSCLK fS tCONV DC tACQ Maximum Clock Frequency Sample Rate Conversion Time SCLK Duty Cycle Track/Hold Acquisition Time Throughput Time (Note 8) (Note 8) www.national.com 4 ADC124S051 ADC124S051 Timing Specifications The following specifications apply for VA = +2.7V to 5.25V, GND = 0V, fSCLK = 3.2 MHz to 8 MHz, fSAMPLE = 200 to 500 kSPS, CL = 35 pF, Boldface limits apply for TA = TMIN to TMAX: all other limits TA = 25˚C. Symbol tCSU tCLH tEN tACC tSU tH tCH tCL Parameter Setup Time SCLK High to CS Falling Edge Hold time SCLK Low to CS Falling Edge Delay from CS Until DOUT active Data Access Time after SCLK Falling Edge Data Setup Time Prior to SCLK Rising Edge Data Valid SCLK Hold Time SCLK High Pulse Width SCLK Low Pulse Width Output Falling tDIS CS Rising Edge to DOUT High-Impedance Output Rising VA = +3.0V VA = +5.0V VA = +3.0V VA = +5.0V (Note 10) (Note 10) Conditions VA = +3.0V VA = +5.0V VA = +3.0V VA = +5.0V VA = +3.0V VA = +5.0V VA = +3.0V VA = +5.0V Typical −3.5 −0.5 +4.5 +1.5 +4 +2 +14.5 +13 +3 +3 0.5 x tSCLK 0.5 x tSCLK 1.8 1.3 1.0 1.0 20 ns (max) Limits (Note 7) 10 10 30 30 10 10 0.3 x tSCLK 0.3 x tSCLK Units ns (min) ns (min) ns (max) ns (max) ns (min) ns (min) ns (min) ns (min) Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions. Note 2: All voltages are measured with respect to GND = 0V, unless otherwise specified. Note 3: When the input voltage at any pin exceeds the power supply (that is, VIN < GND or VIN > VA), the current at that pin should be limited to 10 mA. The 20 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 10 mA to two. The Absolute Maximum Rating specification does not apply to the VA pin. The current into the VA pin is limited by the Analog Supply Voltage specification. Note 4: The absolute maximum junction temperature (TJmax) for this device is 150˚C. The maximum allowable power dissipation is dictated by TJmax, the junction-to-ambient thermal resistance (θJA), and the ambient temperature (TA), and can be calculated using the formula PDMAX = (TJmax − TA)/θJA. The values for maximum power dissipation listed above will be reached only when the device is operated in a severe fault condition (e.g. when input or output pins are driven beyond the power supply voltages, or the power supply polarity is reversed). Obviously, such conditions should always be avoided. Note 5: Human body model is 100 pF capacitor discharged through a 1.5 kΩ resistor. Machine model is 220 pF discharged through zero ohms. Note 6: Reflow temperature profiles are different for lead-free and non-lead-free packages. Note 7: Tested limits are guaranteed to National’s AOQL (Average Outgoing Quality Level). Note 8: This is the frequency range over which the electrical performance is guaranteed. The device is functional over a wider range which is specified under Operating Ratings. Note 9: Data sheet min/max specification limits are guaranteed by design, test, or statistical analysis. Note 10: Clock may be in any state (high or low) when CS is asserted, with the restrictions on setup and hold time given by tCSU and tCLH. 5 www.national.com ADC124S051 Timing Diagrams 20111351 ADC124S051 Operational Timing Diagram 20111308 Timing Test Circuit 20111306 ADC124S051 Serial Timing Diagram 20111350 SCLK and CS Timing Parameters www.national.com 6 ADC124S051 Specification Definitions ACQUISITION TIME is the time required to acquire the input voltage. That is, it is time required for the hold capacitor to charge up to the input voltage. APERTURE DELAY is the time between the fourth falling SCLK edge of a conversion and the time when the input signal is acquired or held for conversion. CONVERSION TIME is the time required, after the input voltage is acquired, for the ADC to convert the input voltage to a digital word. CROSSTALK is the coupling of energy from one channel into the other channel, or the amount of signal energy from one analog input that appears at the measured analog input. DIFFERENTIAL NON-LINEARITY (DNL) is the measure of the maximum deviation from the ideal step size of 1 LSB. DUTY CYCLE is the ratio of the time that a repetitive digital waveform is high to the total time of one period. The specification here refers to the SCLK. EFFECTIVE NUMBER OF BITS (ENOB, or EFFECTIVE BITS) is another method of specifying Signal-to-Noise and Distortion or SINAD. ENOB is defined as (SINAD − 1.76) / 6.02 and says that the converter is equivalent to a perfect ADC of this (ENOB) number of bits. FULL POWER BANDWIDTH is a measure of the frequency at which the reconstructed output fundamental drops 3 dB below its low frequency value for a full scale input. GAIN ERROR is the deviation of the last code transition (111...110) to (111...111) from the ideal (VREF − 1.5 LSB), after adjusting for offset error. INTEGRAL NON-LINEARITY (INL) is a measure of the deviation of each individual code from a line drawn from negative full scale (1⁄2 LSB below the first code transition) through positive full scale (1⁄2 LSB above the last code transition). The deviation of any given code from this straight line is measured from the center of that code value. INTERMODULATION DISTORTION (IMD) is the creation of additional spectral components as a result of two sinusoidal frequencies being applied to the ADC input at the same time. It is defined as the ratio of the power in the second and third order intermodulation products to the sum of the power in both of the original frequencies. IMD is usually expressed in dB. MISSING CODES are those output codes that will never appear at the ADC outputs. The ADC124S051 is guaranteed not to have any missing codes. OFFSET ERROR is the deviation of the first code transition (000...000) to (000...001) from the ideal (i.e. GND + 0.5 LSB). SIGNAL TO NOISE RATIO (SNR) is the ratio, expressed in dB, of the rms value of the input signal to the rms value of the sum of all other spectral components below one-half the sampling frequency, not including harmonics or d.c. SIGNAL TO NOISE PLUS DISTORTION (S/N+D or SINAD) Is the ratio, expressed in dB, of the rms value of the input signal to the rms value of all of the other spectral components below half the clock frequency, including harmonics but excluding d.c. SPURIOUS FREE DYNAMIC RANGE (SFDR) is the difference, expressed in dB, between the rms values of the input signal and the peak spurious signal where a spurious signal is any signal present in the output spectrum that is not present at the input, excluding d.c. TOTAL HARMONIC DISTORTION (THD) is the ratio, expressed in dB or dBc, of the rms total of the first five harmonic components at the output to the rms level of the input signal frequency as seen at the output. THD is calculated as where Af1 is the RMS power of the input frequency at the output and Af2 through Af6 are the RMS power in the first 5 harmonic frequencies. THROUGHPUT TIME is the minimum time required between the start of two successive conversion. It is the acquisition time plus the conversion time. In the case of the ADC124S051, this is 16 SCLK periods. 7 www.national.com ADC124S051 Typical Performance Characteristics 8 MHz, fIN = 40.2 kHz unless otherwise stated. DNL - VA = 3.0V TA = +25˚C, fSAMPLE = 200 kSPS to 500 kSPS, fSCLK = 3.2 to INL - VA = 3.0V 20111320 20111321 DNL - VA = 5.0V INL - VA = 5.0V 20111362 20111363 DNL vs. Supply INL vs. Supply 20111322 20111323 www.national.com 8 ADC124S051 Typical Performance Characteristics TA = +25˚C, fSAMPLE = 200 kSPS to 500 kSPS, fSCLK = 3.2 to 8 MHz, fIN = 40.2 kHz unless otherwise stated. (Continued) DNL vs. Clock Frequency INL vs. Clock Frequency 20111324 20111325 DNL vs. Clock Duty Cycle INL vs. Clock Duty Cycle 20111326 20111327 DNL vs. Temperature INL vs. Temperature 20111328 20111329 9 www.national.com ADC124S051 Typical Performance Characteristics TA = +25˚C, fSAMPLE = 200 kSPS to 500 kSPS, fSCLK = 3.2 to 8 MHz, fIN = 40.2 kHz unless otherwise stated. (Continued) SNR vs. Supply THD vs. Supply 20111330 20111335 SNR vs. Clock Frequency THD vs. Clock Frequency 20111331 20111336 SNR vs. Clock Duty Cycle THD vs. Clock Duty Cycle 20111332 20111337 www.national.com 10 ADC124S051 Typical Performance Characteristics TA = +25˚C, fSAMPLE = 200 kSPS to 500 kSPS, fSCLK = 3.2 to 8 MHz, fIN = 40.2 kHz unless otherwise stated. (Continued) SNR vs. Input Frequency THD vs. Input Frequency 20111333 20111338 SNR vs. Temperature THD vs. Temperature 20111334 20111339 SFDR vs. Supply SINAD vs. Supply 20111340 20111345 11 www.national.com ADC124S051 Typical Performance Characteristics TA = +25˚C, fSAMPLE = 200 kSPS to 500 kSPS, fSCLK = 3.2 to 8 MHz, fIN = 40.2 kHz unless otherwise stated. (Continued) SFDR vs. Clock Frequency SINAD vs. Clock Frequency 20111341 20111346 SFDR vs. Clock Duty Cycle SINAD vs. Clock Duty Cycle 20111342 20111347 SFDR vs. Input Frequency SINAD vs. Input Frequency 20111343 20111348 www.national.com 12 ADC124S051 Typical Performance Characteristics TA = +25˚C, fSAMPLE = 200 kSPS to 500 kSPS, fSCLK = 3.2 to 8 MHz, fIN = 40.2 kHz unless otherwise stated. (Continued) SFDR vs. Temperature SINAD vs. Temperature 20111344 20111349 ENOB vs. Supply ENOB vs. Clock Frequency 20111352 20111353 ENOB vs. Clock Duty Cycle ENOB vs. Input Frequency 20111354 20111355 13 www.national.com ADC124S051 Typical Performance Characteristics TA = +25˚C, fSAMPLE = 200 kSPS to 500 kSPS, fSCLK = 3.2 to 8 MHz, fIN = 40.2 kHz unless otherwise stated. (Continued) ENOB vs. Temperature Spectral Response - 3V, 200 kSPS 20111356 20111359 Spectral Response - 5V, 200 kSPS Spectral Response - 3V, 500 kSPS 20111360 20111364 Spectral Response - 5V, 500 kSPS Power Consumption vs. Throughput 20111365 20111361 www.national.com 14 ADC124S051 Applications Information 1.0 ADC124S051 OPERATION The ADC124S051 is a successive-approximation analog-todigital converter designed around a charge-redistribution digital-to-analog converter. Simplified schematics of the ADC124S051 in both track and hold modes are shown in Figures 1, 2, respectively. In Figure 1, the ADC124S051 is in track mode: switch SW1 connects the sampling capacitor to one of four analog input channels through the multiplexer, and SW2 balances the comparator inputs. The ADC124S051 is in this state for the first three SCLK cycles after CS is brought low. Figure 2 shows the ADC124S051 in hold mode: switch SW1 connects the sampling capacitor to ground, maintaining the sampled voltage, and switch SW2 unbalances the comparator. The control logic then instructs the charge-redistribution DAC to add fixed amounts of charge to the sampling capacitor until the comparator is balanced. When the comparator is balanced, the digital word supplied to the DAC is the digital representation of the analog input voltage. The ADC124S051 is in this state for the fourth through sixteenth SCLK cycles after CS is brought low. The time when CS is low is considered a serial frame. Each of these frames should contain an integer multiple of 16 SCLK cycles, during which time a conversion is performed and clocked out at the DOUT pin and data is clocked into the DIN pin to indicate the multiplexer address for the next conversion. 20111309 FIGURE 1. ADC124S051 in Track Mode 20111310 FIGURE 2. ADC124S051 in Hold Mode 2.0 USING THE ADC124S051 An ADC124S051 timing diagram and a serial interface timing diagram for the ADC124S051 are shown in the Timing Diagrams section. CS is chip select, which initiates conversions and frames the serial data transfers. SCLK (serial clock) controls both the conversion process and the timing of serial data. DOUT is the serial data output pin, where a conversion result is sent as a serial data stream, MSB first. Data to be written to the ADC124S051’s Control Register is placed on DIN, the serial data input pin. New data is written to DIN with each conversion. A serial frame is initiated on the falling edge of CS and ends on the rising edge of CS. Each frame must contain an integer multiple of 16 rising SCLK edges. The ADC output data (DOUT) is in a high impedance state when CS is high and is active when CS is low. Thus, CS acts as an output enable. Additionally, the device goes into a power down state when CS is high, and also between continuous conversion cycles. 15 During the first 3 cycles of SCLK, the ADC is in the track mode, acquiring the input voltage. For the next 13 SCLK cycles the conversion is accomplished and the data is clocked out, MSB first, starting on the 5th clock. If there is more than one conversion in a frame, the ADC will re-enter the track mode on the falling edge of SCLK after the N*16th rising edge of SCLK, and re-enter the hold/convert mode on the N*16+4th falling edge of SCLK, where "N" is an integer. When CS is brought high, SCLK is internally gated off. If SCLK is stopped in the low state while CS is high, the subsequent fall of CS will generate a falling edge of the internal version of SCLK, putting the ADC into the track mode. This is seen by the ADC as the first falling edge of SCLK. If SCLK is stopped with SCLK high, the ADC enters the track mode on the first falling edge of SCLK after the falling edge of CS. During each conversion, data is clocked into the DIN pin on the first 8 rising edges of SCLK after the fall of CS. For each www.national.com ADC124S051 Applications Information (Continued) conversion, it is necessary to clock in the data indicating the input that is selected for the conversion after the current one. See Tables 1, 2 and Table 3. If CS and SCLK go low simultaneously, it is the following rising edge of SCLK that is considered the first rising edge for clocking data into DIN. There are no power-up delays or dummy conversions required with the ADC124S051. The ADC is able to sample and convert an input to full conversion immediately following power up. The first conversion result after power-up will be that of IN1. TABLE 1. Control Register Bits Bit 7 (MSB) DONTC Bit 6 DONTC Bit 5 ADD2 Bit 4 ADD1 Bit 3 ADD0 Bit 2 DONTC Bit 1 DONTC Bit 0 DONTC TABLE 2. Control Register Bit Descriptions Bit #: 7 - 6, 2 - 0 5 4 3 Symbol: DONTC ADD2 ADD1 ADD0 Description Don’t care. The value of these bits do not affect device operation. These three bits determine which input channel will be sampled and converted in the next track/hold cycle. The mapping between codes and channels is shown in Table 3. TABLE 3. Input Channel Selection ADD2 x x x x ADD1 0 0 1 1 ADD0 0 1 0 1 Input Channel IN1 (Default) IN2 IN3 IN4 www.national.com 16 ADC124S051 Applications Information 3.0 ADC124S051 TRANSFER FUNCTION (Continued) The output format of the ADC124S051 is straight binary. Code transitions occur midway between successive integer LSB values. The LSB width for the ADC124S051 is VA/4096. The ideal transfer characteristic is shown in Figure 3. The transition from an output code of 0000 0000 0000 to a code of 0000 0000 0001 is at 1/2 LSB, or a voltage of VA/8192. Other code transitions occur at steps of one LSB. 20111311 FIGURE 3. Ideal Transfer Characteristic 4.0 TYPICAL APPLICATION CIRCUIT A typical application of the ADC124S051 is shown in Figure 4. Power is provided in this example by the National Semiconductor LP2950 low-dropout voltage regulator, available in a variety of fixed and adjustable output voltages. The power supply pin is bypassed with a capacitor network located close to the ADC124S051. Because the reference for the ADC124S051 is the supply voltage, any noise on the supply will degrade device noise performance. To keep noise off the supply, use a dedicated linear regulator for this device, or provide sufficient decoupling from other circuitry to keep noise off the ADC124S051 supply pin. Because of the ADC124S051’s low power requirements, it is also possible to use a precision reference as a power supply to maximize performance. The four-wire interface is also shown connected to a microprocessor or DSP. 20111313 FIGURE 4. Typical Application Circuit 17 www.national.com ADC124S051 Applications Information 5.0 ANALOG INPUTS (Continued) An equivalent circuit for one of the ADC124S051’s input channels is shown in Figure 5. Diodes D1 and D2 provide ESD protection for the analog inputs. At no time should any input go beyond (VA + 300 mV) or (GND − 300 mV), as these ESD diodes will begin conducting, which could result in erratic operation. The capacitor C1 in Figure 5 has a typical value of 3 pF, and is mainly the package pin capacitance. Resistor R1 is the on resistance of the multiplexer and track / hold switch, and is typically 500 ohms. Capacitor C2 is the ADC124S051 sampling capacitor, and is typically 30 pF. The ADC124S051 will deliver best performance when driven by a low-impedance source to eliminate distortion caused by the charging of the sampling capacitance. This is especially important when using the ADC124S051 to sample AC signals. Also important when sampling dynamic signals is a band-pass or low-pass filter to reduce harmonics and noise, improving dynamic performance. The user may trade off throughput for power consumption by simply performing fewer conversions per unit time. The Power Consumption vs. Sample Rate curve in the Typical Performance Curves section shows the typical power consumption of the ADC124S051 versus throughput. To calculate the power consumption, simply multiply the fraction of time spent in the normal mode by the normal mode power consumption , and add the fraction of time spent in shutdown mode multiplied by the shutdown mode power dissipation. 7.1 Power Management When the ADC124S051 is operated continuously in normal mode, the maximum throughput is fSCLK/16. Throughput may be traded for power consumption by running fSCLK at its maximum 8 MHz and performing fewer conversions per unit time, putting the ADC124S051 into shutdown mode between conversions. A plot of typical power consumption versus throughput is shown in the Typical Performance Curves section. To calculate the power consumption for a given throughput, multiply the fraction of time spent in the normal mode by the normal mode power consumption and add the fraction of time spent in shutdown mode multiplied by the shutdown mode power consumption. Generally, the user will put the part into normal mode and then put the part back into shutdown mode. Note that the curve of power consumption vs. throughput is nearly linear. This is because the power consumption in the shutdown mode is so small that it can be ignored for all practical purposes. 7.2 Power Supply Noise Considerations The charging of any output load capacitance requires current from the power supply, VA. The current pulses required from the supply to charge the output capacitance will cause voltage variations on the supply. If these variations are large enough, they could degrade SNR and SINAD performance of the ADC. Furthermore, discharging the output capacitance when the digital output goes from a logic high to a logic low will dump current into the die substrate, which is resistive. Load discharge currents will cause "ground bounce" noise in the substrate that will degrade noise performance if that current is large enough. The larger is the output capacitance, the more current flows through the die substrate and the greater is the noise coupled into the analog channel, degrading noise performance. To keep noise out of the power supply, keep the output load capacitance as small as practical. If the load capacitance is greater than 35 pF, use a 100 Ω series resistor at the ADC output, located as close to the ADC output pin as practical. This will limit the charge and discharge current of the output capacitance and improve noise performance. 20111314 FIGURE 5. Equivalent Input Circuit 6.0 DIGITAL INPUTS AND OUTPUTS The ADC124S051’s digital output DOUT is limited by, and cannot exceed, the supply voltage, VA. The digital input pins are not prone to latch-up and, and although not recommended, SCLK, CS and DIN may be asserted before VA without any latchup risk. 7.0 POWER SUPPLY CONSIDERATIONS The ADC124S051 is fully powered-up whenever CS is low, and fully powered-down whenever CS is high, with one exception: the ADC124S051 automatically enters powerdown mode between the 16th falling edge of a conversion and the 1st falling edge of the subsequent conversion (see Timing Diagrams). The ADC124S051 can perform multiple conversions back to back; each conversion requires 16 SCLK cycles. The ADC124S051 will perform conversions continuously as long as CS is held low. www.national.com 18 ADC124S051 4 Channel, 500 kSPS, 12-Bit A/D Converter Physical Dimensions inches (millimeters) unless otherwise noted 10-Lead MSOP Order Number ADC124S051CIMM, ADC124S051CIMMX NS Package Number P0MUB10A National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications. For the most current product information visit us at www.national.com. LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. 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