LM26480SQ-AA

LM26480 Externally Programmable Dual High-Current Step-Down DC/DC and Dual Linear Regulators March 29, 2010 LM26480 Externally Programmable Dual High-Current Step-Down DC/DC and Dual Linear Regulators General Description The LM26480 is a multi-functional Power Management Unit, optimized for low-power digital applications. This device integrates two highly efficient 1.5A step-down DC/DC converters and two 300 mA linear regulators. The LM26480 is offered in a tiny 4 x 4 x 0.8mm LLP-24 pin package. Linear Regulators (LDO) ■ VOUT of 1.0V–3.5V ■ ±3% FB voltage accuracy ■ 300 mA output current ■ 25 mV (typ) dropout Key Specifications Step-Down DC/DC Converter (Buck) ■ 1.5A output current ■ VOUT from: — Buck1 : 0.8V–2.0V @ 1.5A — Buck2 : 1.0V–3.3V @ 1.5A ■ Up to 96% efficiency ■ ±3% FB voltage accuracy ■ 2 MHz PWM switching frequency ■ PWM - PFM automatic mode change under low loads ■ Automatic soft start Features ■ Compatible with advanced applications processors and ■ ■ ■ ■ ■ ■ ■ FPGAs 2 LDOs for powering Internal processor functions and I/Os Precision internal reference Thermal overload protection Current overload protection 24-lead 4 × 4 × 0.8mm LLP package External Power-On-Reset function for Buck1 and Buck2 Undervoltage lock-out detector to monitor input supply voltage Applications ■ Core digital power ■ Applications processors ■ Peripheral I/O power Typical Application Circuit 30040401 © 2010 National Semiconductor Corporation 300404 www.national.com LM26480 30040402 FIGURE 1. Application Circuit www.national.com 2 LM26480 Connection Diagrams and Package Mark Information 30040403 FIGURE 2. 24-Lead LLP Package (top view) Note: The physical placement of the package marking will vary from part to part. (*) UZXYTT format: ‘U’ – wafer fab code; ‘Z’ – assembly code; ’XY’ 2 digit date code; ‘TT” – die run code. See http://www.national.com/quality/ marking_conventions.html for more information on marking information. Part Number LM26480SQ-AA LM26480SQX-AA LM26480SQ-BF LM26480SQX-BF Spec NOPB NOPB NOPB NOPB Quantity 1000 tape and reel 4500 tape and reel 1000 tape and reel 4500 tape and reel 3 www.national.com LM26480 Pin Descriptions LLP Pin No. 1 2 Name VINLDO12 SYNC I/O I I Type PWR G/(D) Description Analog Power for Internal Functions (VREF, BIAS, I2C, Logic) Frequency Synchronization pin which allows the user to connect an external clock signal to synchronize the PMIC internal oscillator. Default OFF and must be grounded when not used. Part number LM26480SQ-BF has this feature enabled. nPOR Power on reset pin for both Buck1 and Buck 2. Open drain logic output 100K pullup resistor. nPOR is pulled to ground when the voltages on these supplies are not good. See nPOR section for more info. Buck1 NMOS Power Ground Buck1 switcher output pin Power in from either DC source or Battery to Buck1 Enable Pin for Buck1 switcher, a logic HIGH enables Buck1. Pin cannot be left floating. Buck1 input feedback terminal Non-switching core ground pin Analog Power for Buck converters Buck2 input feedback terminal Enable Pin for Buck2 switcher, a logic HIGH enables Buck2. Pin cannot be left floating. Power in from either DC source or Battery to Buck2 Buck2 switcher output pin Buck2 NMOS LDO2 enable pin, a logic HIGH enables LDO2. Pin cannot be left floating. LDO1 enable pin, a logic HIGH enables LDO1. Pin cannot be left floating. LDO ground Power in from either DC source or battery to LDO1 LDO1 Output LDO1 Feedback Terminal LDO2 Feedback Terminal LDO Output Power in from either DC source or battery to LDO2. Connection isn't necessary for electrical performance, but it is recommended for better thermal dissipation. I: Input Pin I/O: Input/Output Pin O: Output Pin 3 NPOR O D 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 DAP A: Analog Pin GND_SW1 SW1 VIN1 ENSW1 FB1 GND_C AVDD FB2 ENSW2 VIN2 SW2 GND_SW2 ENLDO2 ENLDO1 GND_L VINLDO1 LDO1 FBL1 FBL2 LDO2 VINLDO2 DAP D: Digital Pin G O I I I G I I I I O G I I G I O I I O I GND G: Ground Pin G PWR PWR D A G PWR A D PWR PWR G D D G PWR PWR A A PWR PWR GND PWR: Power Pin Power Block Operation Power Block Input VINLDO12 AVDD VIN1 VIN2 VINLDO1 VINLDO2 Enabled VIN+ VIN+ VIN+ VIN+ Disabled VIN+ VIN+ VIN+ or 0V VIN+ or 0V Note Always Powered Always Powered ≤ VIN+ ≤ VIN+ ≤ VIN+ ≤ VIN+ If Enabled, Min VIN is 1.74V If Enabled, Min VIN is 1.74V VIN+ is the largest potential voltage on the device. www.national.com 4 LM26480 Absolute Maximum Ratings (Note 1, Note 2) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. VINLDO12, VIN1, AVDD, VIN2, VINLDO1, VINLDO2, ENSW1, FB1, FB2, ENSW2, ENLDO1, ENLDO2, SYNC, FBL1, FBL2 −0.3V to +6V GND to GND SLUG ±0.3V Power Dissipation (PD_MAX) (TA=85°C, TMAX=125°C ) (Note 5) 1.17W Junction Temperature (TJ-MAX) 150°C Storage Temperature Range −65°C to +150°C Maximum Lead Temperature (Soldering) 260°C ESD Ratings Human Body Model (Note 4) Operating Ratings: Bucks 2, Note 7) VIN VEN Junction Temperature (TJ) Range Ambient Temperature (TA) Range (Note 6) (Note 1, Note 2.8V to 5.5V 0 to (VIN + 0.3V) –40°C to +125°C −40°C to +85°C Thermal Properties Junction-to-Ambient Thermal Resistance (θJA) SQA024AG (Note 3, Note 5, Note 6) 34.1°C/W 2 kV General Electrical Characteristics Symbol IQ VPOR TSD TSDH UVLO Parameter VINLDO12 Shutdown Current Power-On Reset Threshold Thermal Shutdown Threshold Themal Shutdown Hysteresis Under Voltage Lock Out (Note 1, Note 2, Note 7, Note 13, Note 16) Unless otherwise noted, VIN = 3.6V. Typical values and limits appearing in normal type apply for TJ = 25°C. Limits appearing in boldface type apply over the entire junction temperature range for operation, −40°C to +125°C. Conditions VIN = 3.6V VDD Falling Edge(Note 16) (Note 13) (Note 13) Rising Failing Min Typ 0.5 1.9 160 20 2.9 2.7 Max Units µA V °C °C V V Low Drop Out Regulators, LDO1 and LDO2 Unless otherwise noted, VIN = 3.6V, CIN = 1.0 µF, COUT = 0.47 µF. Typical values and limits appearing in normal type apply for TJ = 25°C. Limits appearing in boldface type apply over the entire junction temperature range for operation, −40°C to +125°C. (Note 2, Note 7, Note 8, Note 9) Symbol VIN VFB ΔVOUT Parameter Operational Voltage Range FB Voltage Accuracy Line Regulation Load Regulation Short Circuit Current Limit Dropout Voltage Power Supply Ripple Rejection Supply Output Noise Quiescent Current “On” IQ TON Quiescent Current “On” Quiescent Current “Off” Turn On Time VIN = (VOUT + 0.3V) to 5.0V (Note 12) Load Current = 1 mA VIN = 3.6V, Load Current = 1 mA to IMAX LDO1-2, VOUT = 0V Load Current = 50 mA (Note 10) F = 10 kHz, Load Current = IMAX 10 Hz < F < 100 kHz IOUT = 0 mA IOUT = 300 mA EN is de-asserted Start up from shut-down 500 25 45 150 40 60 0.03 300 150 200 1 200 Conditions VINLDO1 and VINLDO2 PMOS pins (Note 15) Min 1.74 −3 Typ Max 5.5 3 0.15 0.011 Units V % %/V %/mA mA mV dB µVrms µA µA µA µsec ISC VIN – VOUT PSRR θn 5 www.national.com LM26480 Symbol Parameter Conditions Capacitance for stability 0°C ≤ TJ ≤ 125°C Min 0.33 0.68 5 Typ 0.47 1.0 Max Units µF µF COUT Output Capacitor −40°C ≤ TJ ≤ 125°C ESR (Equivalent Series Resistance) 500 mΩ Buck Converters SW1, SW2 Unless otherwise noted, VIN = 3.6V, CIN = 10 µF, COUT = 10 µF, LOUT = 2.2 µH. Typical values and limits appearing in normal type apply for TJ = 25°C. Limits appearing in boldface type apply over the entire junction temperature range for operation, −40°C to +125°C. ((Note 2, Note 7, Note 8, Note 9, Note 11, Note 14) Symbol VFB (Note 14) VOUT Load Regulation Eff ISHDN fOSC IPEAK IQ RDSON (P) RDSON (N) TON CIN CO Efficiency Shutdown Supply Current Internal Oscillator Frequency Buck1 Peak Switching Current Limit Buck2 Peak Switching Current Limit Quiescent Current “On” Pin-Pin Resistance PFET Pin-Pin Resistance NFET Turn On Time Input Capacitor Output Capacitor Start up from shut-down Capacitance for stability Capacitance for stability 10 10 No load PFM Mode Parameter Feedback Voltage Line Regulation 2.8 < VIN < 5.5 IO =10 mA 100 mA < IO < IMAX Load Current = 250 mA EN is de-asserted Conditions Min −3 0.089 0.0013 96 0.01 2.0 2.0 2.0 33 200 180 500 400 400 1 2.4 2.4 2.4 Typ Max +3 Units % %/V %/mA % µA MHz A µA mΩ mΩ µsec µF µF I/O Electrical Characteristics Unless otherwise noted: Typical values and limits appearing in normal type apply for TJ = 25°C. Limits appearing in boldface type apply over the entire junction temperature range for operation, TJ = 0°C to +125°C. Symbol VIL VIH Parameter Input Low Level Input High Level 0.7*VDD Conditions Limit Min Max 0.4 Units V V Power On Reset Threshold/Function (POR) Symbol nPOR nPOR Threshold VOL Parameter nPOR = Power on reset for Buck1 and Buck2 Percentage of Target voltage Buck1 or Buck2 Output Level Low Default VBUCK1 AND VBUCK2 rising VBUCK1 OR VBUCK2 falling Load = IOL = 500 µA Conditions Min Typ 60 92 82 0.23 0.5 Max Units msec % V www.national.com 6 LM26480 Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the component may occur. Operating Ratings are conditions under which operation of the device is guaranteed. Operating Ratings do not imply guaranteed performance limits. For guaranteed performance limits and associated test conditions, see the Electrical Characteristics. Note 2: All voltages are with respect to the potential at the GND pin. Note 3: Internal thermal shutdown circuitry protects the device from permanent damage. Thermal shutdown engages at TJ = 160°C (typ.) and disengages at TJ = 140°C (typ.) Note 4: The Human body model is a 100 pF capacitor discharged through a 1.5 kΩ resistor into each pin. (MILSTD - 883 3015.7) Note 5: In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature may have to be derated. Maximum ambient temperature (TA-MAX) is dependent on the maximum operating junction temperature (TJ-MAX-OP = 125°C), the maximum power dissipation of the device in the application (PD-MAX), and the junction-to-ambient thermal resistance of the part/package in the application (θJA), as given by the following equation: TA-MAX = TJ-MAX-OP − (θJA × PD-MAX). See Applications section. Note 6: Junction-to-ambient thermal resistance is highly application and board-layout dependent. In applications where high maximum power dissipation exists, special care must be paid to thermal dissipation issues in board design. Note 7: Min and Max limits are guaranteed by design, test, or statistical analysis. Typical numbers are not guaranteed, but do represent the most likely norm. Note 8: CIN, COUT: Low-ESR Surface-Mount Ceramic Capacitors (MLCCs) used in setting electrical characteristics. Note 9: The device maintains a stable, regulated output voltage without a load. Note 10: Dropout voltage is the voltage difference between the input and the output at which the output voltage drops to 100 mV below its nominal value. Note 11: Quiescent current is defined here as the difference in current between the input voltage source and the load at VOUT. Note 12: VIN minimum for line regulation values is 1.8V. Note 13: This specification is guaranteed by design. Note 14: VIN ≥ VOUT + RDSON(P) (IOUT + 1/2 IRIPPLE). If these conditions are not met, voltage regulation will degrade as load increases. Note 15: Pins 24, 19 can operate from VIN min of 1.74V to a VIN max of 5.5V. This rating is only for the series pass PMOS power FET. It allows the system design to use a lower voltage rating if the input voltage comes from a buck output. Note 16: VPOR is voltage at which the EPROM resets. This is different from the UVLO on VINLDO12, which is the voltage at which the regulators shut off; and is also different from the nPOR function, which signals if the regulators are in a specified range. 7 www.national.com LM26480 Typical Performance Characteristics — LDO Output Voltage Change vs Temperature (LDO1) VIN = 3.6V, VOUT = 2.5V, 100 mA load Output Voltage Change vs Temperature (LDO2) VIN = 3.6V, VOUT = 1.8V, 100 mA load 30040466 30040455 Load Transient 3.6 VIN, 2.5VOUT, 0 – 150 mA load Load Transient 3.6 VIN, 2.5VOUT, 150–300 mA load 30040437 30040438 Line Transient (LDO1) 3.6 - 4.2 VIN, 2.5 VOUT, 100 mA load Line Transient (LDO2) 3.6 – 4.2 VIN, 1.8VOUT, 150 mA load 30040439 30040440 www.national.com 8 LM26480 Enable Start-up time (LDO1) 0-3.6 VIN, 2.5 VOUT, 1 mA load Enable Start-up time (LDO2) 0 – 3.6 VIN, 1.8VOUT, 1 mA load 30040441 30040442 9 www.national.com LM26480 Typical Performance Characteristics — Buck Shutdown Current vs. Temp VIN = 2.8V to 5.5V, TA = 25°C Output Voltage vs. Supply Voltage (VOUT = 1.2V) 30040443 30040444 Output Voltage vs. Supply Voltage (VOUT = 2.0V) Output Voltage vs. Supply Voltage (VOUT = 3.0V) 30040445 30040446 www.national.com 10 LM26480 Typical Performance Characteristics — Buck mode for Buck 1 Efficiency vs. Output Current (VOUT = 1.2V, L = 2.2 µH) Output Current transitions from PFM mode to PWM Efficiency vs. Output Current (VOUT = 2.0V, L = 2.2 µH) 30040447 30040448 Output Current transitions from PWM mode to PFM mode for Buck 2 Efficiency vs. Output Current (VOUT = 3.0V, L = 2.2 µH) Efficiency vs. Output Current (VOUT = 3.5V, L = 2.2 µH) 30040449 30040450 11 www.national.com LM26480 Typical Performance Characteristics — Buck VIN= 3.6V, TA = 25°C, VOUT = 1.2V unless otherwise noted Load Transient Response VOUT = 1.2V (PWM Mode) Mode Change by Load Transients VOUT = 1.2V (PWM to PFM) 30040456 30040457 Line Transient Response VIN = 3.6 – 4.2V, VOUT = 1.2V, 250 mA load Line Transient Response VIN = 3.0 – 3.6V, VOUT = 3.0V, 250 mA load 30040458 30040459 Start up into PWM Mode VOUT = 1.2V, 1.5A load Start up into PWM Mode VOUT = 3.0 V, 1.5A load 30040460 30040461 www.national.com 12 LM26480 Start up into PFM Mode VOUT = 1.2V, 30 mA load Start up into PFM Mode VOUT = 3.0V, 30 mA load 30040462 30040470 13 www.national.com LM26480 DC/DC Converters OVERVIEW The LM26480 provides the DC/DC converters that supply the various power needs of the application by means of two linear low dropout regulators, LDO1 and LDO2, and two buck converters, SW1 and SW2. The table here under lists the output characteristics of the various regulators. Supply Specification Output Supply Load IMAX VOUT Range (V) Maximum Output Current (mA) 1.0 to 3.5 1.0 to 3.5 0.8 to 2.0 1.0 to 3.3 300 300 1500 1500 turns off the device, offering the lowest current consumption. PWM or PFM mode is selected automatically or PWM mode can be forced through the setting of the buck control register. Both SW1 and SW2 can operate up to a 100% duty cycle (PMOS switch always on) for low drop out control of the output voltage. In this way the output voltage will be controlled down to the lowest possible input voltage. Additional features include soft-start, under-voltage lock-out, current overload protection, and thermal overload protection. CIRCUIT OPERATION DESCRIPTION A buck converter contains a control block, a switching PFET connected between input and output, a synchronous rectifying NFET connected between the output and ground (BCKGND pin) and a feedback path. During the first portion of each switching cycle, the control block turns on the internal PFET switch. This allows current to flow from the input through the inductor to the output filter capacitor and load. The inductor limits the current to a ramp with a slope of LDO1 LDO2 SW1 SW2 analog analog digital digital LINEAR LOW DROPOUT REGULATORS (LDOs) LDO1 and LDO2 are identical linear regulators targeting analog loads characterized by low noise requirements. LDO1 and LDO2 are enabled through the ENLDO pin. by storing energy in a magnetic field. During the second portion of each cycle, the control block turns the PFET switch off, blocking current flow from the input, and then turns the NFET synchronous rectifier on. The inductor draws current from ground through the NFET to the output filter capacitor and load, which ramps the inductor current down with a slope of The output filter stores charge when the inductor current is high, and releases it when low, smoothing the voltage across the load. 30040404 NO-LOAD STABILITY The LDOs will remain stable and in regulation with no external load. This is an important consideration in some circuits, for example, CMOS RAM keep-alive applications. SW1, SW2: Synchronous StepDown Magnetic DC/DC Converters FUNCTIONAL DESCRIPTION The LM26480 incorporates two high-efficiency synchronous switching buck regulators, SW1 and SW2, that deliver a constant voltage from a single Li-Ion battery to the portable system processors. Using a voltage mode architecture with synchronous rectification, both bucks have the ability to deliver up to 1500 mA depending on the input voltage and output voltage (voltage head room), and the inductor chosen (maximum current capability). There are three modes of operation depending on the current required - PWM, PFM, and shutdown. PWM mode handles current loads of approximately 70 mA or higher, delivering voltage precision of +/-3% with 90% efficiency or better. Lighter output current loads cause the device to automatically switch into PFM for reduced current consumption (IQ = 33 µA typ.) and a longer battery life. The Standby operating mode SYNC FUNCTION The LM26480SQ-BF is the only version of the part that has the ability to use an external oscillator. The source must be 13 MHz nominal and operate within a range of 15.6 MHz and 10.4 MHz, proportionally the same limits as the 2.0 MHz internal oscillator. The LM26480SQ-BF has an internal divider which will divide the speed down by 6.5 to the nominal 2MHz and use it for the regulators. This SYNC function replaces the internal oscillator and works in forced PWM only. The buck regulators no longer have the PFM function enabled. When the LM26480SQ-BF is sold with this feature enabled, the part will not function without the external oscillator present. PWM OPERATION During PWM operation the converter operates as a voltagemode controller with input voltage feed forward. This allows the converter to achieve excellent load and line regulation. The DC gain of the power stage is proportional to the input voltage. To eliminate this dependence, feed forward voltage inversely proportional to the input voltage is introduced. INTERNAL SYNCHRONOUS RECTIFICATION While in PWM mode, the buck uses an internal NFET as a synchronous rectifier to reduce rectifier forward voltage drop and associated power loss. Synchronous rectification provides a significant improvement in efficiency whenever the output voltage is relatively low compared to the voltage drop across an ordinary rectifier diode. 14 www.national.com LM26480 CURRENT LIMITING A current limit feature allows the converter to protect itself and external components during overload conditions. PWM mode implements current limiting using an internal comparator that trips at 2.0A for both bucks (typ). If the output is shorted to ground the device enters a timed current limit mode where the NFET is turned on for a longer duration until the inductor current falls below a low threshold, ensuring inductor current has more time to decay, thereby preventing runaway. PFM OPERATION At very light loads, the converter enters PFM mode and operates with reduced switching frequency and supply current to maintain high efficiency. The part will automatically transition into PFM mode when either of two conditions occurs for a duration of 32 or more clock cycles: A. The inductor current becomes discontinuous or B. The peak PMOS switch current drops below the IMODE level the I PFM level set for PFM mode. The typical peak current in PFM mode is: During PFM operation, the converter positions the output voltage slightly higher than the nominal output voltage during PWM operation, allowing additional headroom for voltage drop during a load transient from light to heavy load. The PFM comparators sense the output voltage via the feedback pin and control the switching of the output FETs such that the output voltage ramps between 0.8% and 1.6% (typical) above the nominal PWM output voltage. If the output voltage is below the ‘high’ PFM comparator threshold, the PMOS power switch is turned on. It remains on until the output voltage exceeds the ‘high’ PFM threshold or the peak current exceeds Once the PMOS power switch is turned off, the NMOS power switch is turned on until the inductor current ramps to zero. When the NMOS zero-current condition is detected, the NMOS power switch is turned off. If the output voltage is below the ‘high’ PFM comparator threshold (see following figure), the PMOS switch is again turned on and the cycle is repeated until the output reaches the desired level. Once the output reaches the ‘high’ PFM threshold, the NMOS switch is turned on briefly to ramp the inductor current to zero and then both output switches are turned off and the part enters an extremely low power mode. Quiescent supply current during this ‘sleep’ mode is less than 30 µA, which allows the part to achieve high efficiencies under extremely light load conditions. When the output drops below the ‘low’ PFM threshold, the cycle repeats to restore the output voltage to ~1.6% above the nominal PWM output voltage. If the load current should increase during PFM mode (see figure below) causing the output voltage to fall below the ‘low2’ PFM threshold, the part will automatically transition into fixed-frequency PWM mode. SW1, SW2 CONTROL SW1 and SW2 are enabled/disabled through the external enable pins. The Modulation mode PWM/PFM is by default automatic and depends on the load as described above in the functional description. The modulation mode can be factory trimmed, forcing the buck to operate in PWM mode regardless of the load condition. 15 www.national.com LM26480 30040405 SHUTDOWN MODE During shutdown the PFET switch, reference, control and bias circuitry of the converters are turned off. The NFET switch will be on in shutdown to discharge the output. When the converter is enabled, soft start is activated. It is recommended to disable the converter during the system power up and under voltage conditions when the supply is less than 2.8V. SOFT START The soft-start feature allows the power converter to gradually reach the initial steady state operating point, thus reducing startup stresses and surges. The two LM26480 buck converters have a soft-start circuit that limits in-rush current during startup. During startup the switch current limit is increased in steps. Soft start is activated only if EN goes from logic low to logic high after VIN reaches 2.8V. Soft start is implemented by increasing switch current limit in steps of 250 mA, 500 mA, 950 mA and 2A for both bucks (typ. switch current limit). The startup time thereby depends on the output capacitor and load current demanded at start-up. LOW DROPOUT OPERATION The LM26480 can operate at 100% duty cycle (no switching; PMOS switch completely on) for low dropout support of the output voltage. In this way the output voltage will be controlled down to the lowest possible input voltage. When the device operates near 100% duty cycle, output voltage ripple is approximately 25 mV. The minimum input voltage needed to support the output voltage is VIN, MIN = ILOAD * (RDSON, PFET + RINDUCTOR) + VOUT — ILOAD — RDSON, PFET — RINDUCTOR Load current Drain to source resistance of PFET switch in the triode region Inductor resistance FLEXIBLE POWER-ON RESET (i.e., POWER GOOD WITH DELAY) The LM26480 is equipped with an internal Power-On-Reset (“POR”) circuit which monitors the output voltage levels on bucks 1 and 2. The nPOR is an open drain logic output which is logic LOW when either of the buck outputs are below 91% of the rising value , or when one or both outputs fall below 82% of the desired value. The time delay between output voltage level and nPOR is enabled is (50 µs, 50 ms, 100 ms, 200 ms), 50 ms by default. For any other delay option, other than the default, please consult a National Sales Representative. The system designer can choose the external pull-up resistor (i.e. 100 kΩ ) for the nPOR pin. www.national.com 16 LM26480 NPOR with Counter Delay 30040406 The above diagram shows the simplest application of the Power-On Reset, where both switcher enables are tied together. In Case 1, EN1 causes nPOR to transition LOW and triggers the nPOR delay counter. If the power supply for Buck2 does not come on within that period, nPOR will stay LOW, indicating a power fail mode. Case 2 indicates the vice versa scenario if Buck1 supply did not come on. In both cases the nPOR remains LOW. Case 3 shows a typical application of the Power-On Reset, where both switcher enables are tied together. Even if RDY1 ramps up slightly faster than RDY2 (or vice versa), the nPOR signal will trigger a programmable delay before going HIGH, as explained below. 17 www.national.com LM26480 Faults Occurring in Counter Delay After Startup 30040407 The above timing diagram details the Power Good with delay with respect to the enable signals EN1, and EN2. The RDY1, RDY2 are internal signals derived from the output of two comparators. Each comparator has been trimmed as follows: Comparator Level HIGH LOW Buck Supply Level Greater than 91% Less than 82% The circuits for EN1 and RDY1 are symmetrical to EN2 and RDY2, so each reference to EN1 and RDY1 will also work for EN2 and RDY2 and vice versa. If EN1 and RDY1 signals are High at time t1, then the RDY1 signal rising edge triggers the programmable delay counter (50 μs, 50 ms, 100 ms, 200 ms). This delay forces nPOR LOW between time interval t1 and t2. NPOR is then pulled high after the programmable delay is completed. Now if EN2 and RDY2 are initiated during this interval the nPOR signal ignores this event. If either RDY1or RDY2 were to go LOW at t3 then the programmable delay is triggered again. www.national.com 18 LM26480 NPOR Mask Window 30040408 In Case 1, we see that case where EN2 and RDY2 are initiated after triggered programmable delay. To prevent the nPOR being asserted again, a masked window (5 ms) counter delay is triggered off the EN2 rising edge. NPOR is still held HIGH for the duration of the mask, whereupon the nPOR status afterwards will depend on the status of both RDY1 and RDY2 lines. In Case 2, we see the case where EN2 is initiated after the RDY1 triggered programmable delay, but RDY2 never goes HIGH (Buck2 never turns on). Normal operation operation of nPOR occurs wilth respect to EN1 and RDY1, and the nPOR signal is held HIGH for the duration of the mask window. We see that nPOR goes LOW after the masking window has timed out because it is now dependent on RDY1 and RDY2, where RDY2 is LOW. 19 www.national.com LM26480 Design Implementation of the Flexible Power-On Reset 30040409 Design implementation of the flexible power-on reset. An internal power-on reset of the IC is used with EN1 and EN2 to produce a reset signal (LOW) to the delay timer nPOR. EN1 and RDY1 or EN2 and RDY2 are used to generate the set signal (HIGH) to the delay timer. S=R=1 never occurs. The mask timers are triggered off EN1 and EN2 which are gated with RDY1, and RDY2 to generate outputs to the final AND gate to generate the nPOR. UNDER VOLTAGE LOCK OUT The LM26480 features an “under voltage lock out circuit”. The function of this circuit is to continuously monitor the raw input supply voltage (VINLDO12) and automatically disables the four voltage regulators whenever this supply voltage is less than 2.8 VDC. The circuit incorporates a bandgap based circuit that establishes the reference used to determine the 2.8 VDC trip point for a VIN OK – Not OK detector. This VIN OK signal is then used to gate the enable signals to the four regulators of the LM26480. When VINLDO12 is greater than 2.8 VDC the four enables control the four regulators, when VINLDO12 is less than 2.8 VDC the four regulators are disabled by the VIN detector being in the “Not OK” state. The circuit has built in hysteresis to prevent chattering occurring. www.national.com 20 LM26480 Application Notes EXTERNAL COMPONENT SELECTION 30040410 Ideal Resistor Values Common R Values Target R2 (KΩ) R1 (KΩ) R2 (KΩ) Vout (V) R1 (KΩ) 0.8 0.9 1 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 3 3.1 3.2 3.3 120 160 200 240 280 320 360 400 440 427 463 498 450 480 422 446 471 400 420 440 460 480 500 520 540 560 200 200 200 200 200 200 200 200 200 178 178 178 150 150 124 124 124 100 100 100 100 100 100 100 100 100 121 162 200 240 280 324 357 402 442 432 464 499 453 475 422 442 475 402 422 442 464 475 499 523 536 562 200 200 200 200 200 200 200 200 200 178 178 178 150 150 124 124 124 100 100 100 100 100 100 100 100 100 Actual VOUT W/ Com/R (V) 0.803 0.905 1 1.1 1.2 1.31 1.393 1.505 1.605 1.713 1.803 1.902 2.01 2.083 2.202 2.282 2.415 2.51 2.61 2.71 2.82 2.875 2.995 3.115 3.18 3.31 Actual VOUT Delta from Target (V) 0.002 0.005 0 0 0 0.01 -0.008 0.005 0.005 0.013 0.003 0.002 0.01 -0.017 0.002 -0.018 0.015 0.01 0.01 0.01 0.02 -0.025 -0.005 0.015 -0.02 0.01 Feedback Capacitors C1(pF) 15 15 15 15 12 12 10 10 8.2 8.2 8.2 8.2 8.2 8.2 8.2 8.2 8.2 8.2 8.2 8.2 8.2 8.2 6.8 6.8 6.8 6.8 C2(pF) none none none none none none none none none none none none none none none none none none none 33 33 33 33 33 33 33 Buck1 Only ^ | | Buck1 And Buck2 | | | | > ^ | | | | | Buck2 Only | | | | | The output voltages of the bucks of the LM26480 are established by the feedback resistor dividers R1 and R2 shown on the application circuit above. The equation for determining V is: VOUT = VFB (R1+R2)/R2 where VFB is the voltage on the Buck FBx pin. The Buck control loop will force the voltage on VFB to be 0.50 V ±3%. The above table shows ideal resistor values to establish buck voltages from 0.8V to 3.3 V along with common resistor valInductor LSW1,2 Value 2.2 Unit µH ues to establish these voltages. Common resistors do not always produce the target value, error is given in the delta column. In addition to the resistor feedback, capacitor feedback C1 is always required, and depending on the output voltage capacitor C2 is also required. See the application diagram below and the above table for these requirements. Description SW1,2 inductor Notes D.C.R. 70 mΩ 21 www.national.com LM26480 OUTPUT INDUCTORS & CAPACITORS FOR SW1 AND SW2 There are several design considerations related to the selection of output inductors and capacitors: • Load transient response; • Stability; • Efficiency; • Output ripple voltage; and • Over-current ruggedness. The LM26480 has been optimized for use with nominal values 2.2 µH and 10 µF. If other values are needed for the design, please contact National Semiconductor sales with any concerns. INDUCTOR SELECTION FOR SW1 AND SW2 A nominal inductor value of 2.2 µH is recommended. It is important to guarantee the inductor core does not saturate during any foreseeable operational situation. Care should be taken when reviewing the different saturation current ratings that are specified by different manufacturers. Saturation current ratings are typically specified at 25ºC, so ratings at maximum ambient temperature of the application should be requested from the manufacturer. There are two methods to choose the inductor saturation current rating: Recommended method: The best way to guarantee the inductor does not saturate is to choose an inductor that has saturation current rating greater than the maximum LM26480 current limit of 2.4A. In this case the device will prevent inductor saturation. Alternate method: Model DO3314-222MX LPO3310-222MX ELL6PG2R2N ELC6GN2R2N CDRH2D14NP-2R2NC Coilcraft Coilcraft Panasonic Panasonic Sumida Vendor If the recommended approach cannot be used, care must be taken to guarantee that the saturation current is greater than the peak inductor current: 30040471 ISAT: Inductor saturation current at operating temperature ILPEAK: Peak inductor current during worst case conditions IOUTMAX: Maximum average inductor current IRIPPLE: Peak-to-Peak inductor current VOUT: Output voltage VIN: Input voltage L: Inductor value in Henries at IOUTMAX F: Switching frequency, Hertz D: Estimated duty factor EFF: Estimated power supply efficiency ISAT may not be exceeded during any operation, including transients, startup, high temperature, worst case conditions, etc. SUGGESTED INDUCTORS AND THEIR SUPPLIERS Dimensions (mm) 3.3 x 3.3 x 1.4 3.3 x 3.3 x 1 6.0 x 6.0 x 2.0 6.0 x 6.0 x 1.5 3.2 x 3.2 x 1.5 DCR (max) 200 mΩ 150 mΩ 37 mΩ 53 mΩ 94 mΩ ISATURATION ≈1.8A ≈1.3A ≈2.2A ≈1.9A ≈1.5A Note: Inductor Current Saturation values are estimates; inductor manufacturer should be contacted for guaranteed values. OUTPUT CAPACITOR SELECTION FOR SW1 AND SW2 A ceramic output capacitor of 10 µF, 6.3V is recommended with an ESR of about 2mΩ or less. Output ripple can be estimated from the vector sum of the reactive (Capacitor) voltage component and the real (ESR) voltage component of the output capacitor. VCOUT: VROUT: VPPOUT: Estimated reactive output ripple Estimated real output ripple Estimated peak-to-peak output ripple performance, X7R or X5R types are recommended. DC bias characteristics of ceramic capacitors must be considered when selecting case sizes like 0805 and 0603. DC bias characteristics vary from manufacturer to manufacturer and by case size. DC bias curves should be requested from them as part of the capacitor selection process. ESR is typically higher for smaller packages. The output filter capacitor smooths out current flow from the inductor to the load, helps maintain a steady output voltage during transient load changes and reduces output voltage ripple. These capacitors must be selected with sufficient capacitance and sufficiently low ESR to perform these functions. Note that the output voltage ripple is dependent on the inductor current ripple and the equivalent series resistance of the output capacitor (ESRCOUT). ESRCOUT is frequency dependent as well as temperature dependent. The RESR should be calculated with the applicable switching frequency and ambient temperature. The output capacitor needs to be mounted as close as possible to the output pin of the device. For better temperature www.national.com 22 LM26480 INPUT CAPACITOR SELECTION FOR SW1 AND SW2 It is required to use a ceramic input capacitor of at least 4.7 μF and 6.3V with an ESR of under 10 mΩ. The input power source supplies average current continuously. During the PFET switch on-time, however, the demanded di/dt is higher than can be typically supplied by the input power source. This delta is supplied by the input capacitor. A simplified “worst case” assumption is that all of the PFET current is supplied by the input capacitor. This will result in conservative estimates of input ripple voltage and capacitor RMS current. Input ripple voltage is estimated as follows: VPPIN: IOUT: CIN: ESRIN: Estimated peak-to-peak input ripple voltage Output current, Amps Input capacitor value, Farads Input capacitor ESR, Ohms This capacitor is exposed to significant RMS current, so it is important to select a capacitor with an adequate RMS current rating. Capacitor RMS current estimated as follows: IRSCIN Estimated input capacitor RMS current Model 4.7 µF for CIN C2012X5R0J475K JMK212BJ475K GRM21BR60J475K C1608X5R0J475K 10 µF for COUT GRM21BR60J106K JMK212BJ106K C2012X5R0J106K C1608X5R0J106K Type Ceramic, X5R Ceramic, X5R Ceramic, X5R Ceramic, X5R Ceramic, X5R Ceramic, X5R Ceramic, X5R Ceramic, X5R Vendor TDK Taiyo-Yuden Murata TDK Murata Taiyo-Yuden TDK TDK Voltage Rating 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V Case Size 0805, (2012) 0805, (2012) 0805, (2012) 0603, (1608) 0805, (2012) 0805, (2012) 0805, (2012) 0603, (1608) 23 www.national.com LM26480 FEEDBACK RESISTORS FOR LDOs 30040410 Target VOUT (V) 1 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 3 3.1 3.2 3.3 3.4 3.5 Ideal Resistor Values R1 (KΩ) 200 240 280 320 360 400 440 480 520 560 600 640 680 720 760 800 840 880 920 960 1000 1040 1080 1120 1160 1200 R2 (KΩ) 200 200 200 200 200 200 200 200 200 200 200 200 200 200 200 200 200 200 200 200 200 200 200 200 200 200 R1 (KΩ) Common R Values R2 (KΩ) 200 200 200 200 200 200 200 232 232 200 200 221 200 226 221 187 215 249 249 255 200 191 187 215 210 200 200 240 280 324 357 402 442 562 604 562 604 715 681 806 845 750 909 1100 1150 1210 1000 1000 1000 1210 1210 1210 Actual VOUT W/ Com/R (V) 1 1.1 1.2 1.31 1.393 1.505 1.605 1.711 1.802 1.905 2.01 2.118 2.203 2.283 2.412 2.505 2.614 2.709 2.809 2.873 3 3.118 3.174 3.314 3.381 3.525 The output voltages of the LDOs of the LM26480 are established by the feedback resistor dividers R1 and R2 shown on the application circuit above. The equation for determining VOUT is: VOUT = VFB(R1+R2)/R2, where VFB is the voltage on the LDOX_FB pin. The LDO control loop will force the voltage on VFB to be 0.50 V ±3%. The above table shows ideal resistor values to es- tablish LDO voltages from 1.0V to 3.5V along with common resistor values to establish these voltages. Common resistors do not always produce the target value, error is given in the final column. To keep the power consumed by the feedback network low it is recommended that R2 be established as about 200 KΩ. Lesser values of R2 are OK at the users discretion.. www.national.com 24 LM26480 LDO CAPACITOR SELECTION Input Capacitor An input capacitor is required for stability. It is recommended that a 1.0 μF capacitor be connected between the LDO input pin and ground (this capacitance value may be increased without limit). This capacitor must be located a distance of not more than 1 cm from the input pin and returned to a clean analog ground. Any good quality ceramic, tantalum, or film capacitor may be used at the input. Warning: Important: Tantalum capacitors can suffer catastrophic failures due to surge currents when connected to a low impedance source of power (like a battery or a very large capacitor). If a tantalum capacitor is used at the input, it must be guaranteed by the manufacturer to have a surge current rating sufficient for the application. There are no requirements for the ESR on the input capacitor, but tolerance and temperature coefficient must be considered when selecting the capacitor to ensure the capacitance will remain approximately 1.0 μF over the entire operating temperature range. different capacitor case sizes in a capacitance vs. DC bias plot. Output Capacitor The LDOs on the LM26480 are designed specifically to work with very small ceramic output capacitors. A 1.0 μF ceramic capacitor (temperature types Z5U, Y5V or X7R) with ESR between 5 mΩ to 500 mΩ, are suitable in the application circuit. It is also possible to use tantalum or film capacitors at the device output COUT (or VOUT), but these are not as attractive for reasons of size and cost. The output capacitor must meet the requirement for the minimum value of capacitance and also have an ESR value that is within the range 5 mΩ to 500 mΩ for stability. Capacitor Characteristics The LDOs are designed to work with ceramic capacitors on the output to take advantage of the benefits they offer. For capacitance values in the range of 0.47 μF to 4.7 μF, ceramic capacitors are the smallest, least expensive and have the lowest ESR values, thus making them best for eliminating high frequency noise. The ESR of a typical 1.0 μF ceramic capacitor is in the range of 20 mΩ to 40 mΩ, which easily meets the ESR requirement for stability for the LDOs. For both input and output capacitors, careful interpretation of the capacitor specification is required to ensure correct device operation. The capacitor value can change greatly, depending on the operating conditions and capacitor type. In particular, the output capacitor selection should take account of all the capacitor parameters, to ensure that the specification is met within the application. The capacitance can vary with DC bias conditions as well as temperature and frequency of operation. Capacitor values will also show some decrease over time due to aging. The capacitor parameters are also dependent on the particular case size, with smaller sizes giving poorer performance figures in general. As an example, the graph below shows a typical graph comparing Capacitor CLDO1 CLDO2 CSW1 CSW2 Min Value 0.47 0.47 10 10 Unit µF µF µF µF 30040416 As shown in the graph, increasing the DC bias condition can result in the capacitance value that falls below the minimum value given in the recommended capacitor specifications table. Note that the graph shows the capacitance out of spec for the 0402 case size capacitor at higher bias voltages. It is therefore recommended that the capacitor manufacturers’ specifications for the nominal value capacitor are consulted for all conditions, as some capacitor sizes (e.g. 0402) may not be suitable in the actual application. The ceramic capacitor’s capacitance can vary with temperature. The capacitor type X7R, which operates over a temperature range of −55°C to +125°C, will only vary the capacitance to within ±15%. The capacitor type X5R has a similar tolerance over a reduced temperature range of −55°C to +85°C. Many large value ceramic capacitors, larger than 1 μF are manufactured with Z5U or Y5V temperature characteristics. Their capacitance can drop by more than 50% as the temperature varies from 25°C to 85°C. Therefore X7R is recommended over Z5U and Y5V in applications where the ambient temperature will change significantly above or below 25°C. Tantalum capacitors are less desirable than ceramic for use as output capacitors because they are more expensive when comparing equivalent capacitance and voltage ratings in the 0.47 μF to 4.7 μF range. Another important consideration is that tantalum capacitors have higher ESR values than equivalent size ceramics. This means that while it may be possible to find a tantalum capacitor with an ESR value within the stable range, it would have to be larger in capacitance (which means bigger and more costly) than a ceramic capacitor with the same ESR value. It should also be noted that the ESR of a typical tantalum will increase about 2:1 as the temperature goes from 25°C down to −40°C, so some guard band must be allowed. Recommended Type Description LDO1 output capacitor Ceramic, 6.3V, X5R LDO2 output capacitor Ceramic, 6.3V, X5R SW1 output capacitor SW2 output capacitor Ceramic, 6.3V, X5R Ceramic, 6.3V, X5R 25 www.national.com LM26480 Analog Power Signal Routing All power inputs should be tied to the main VDD source (i.e. battery), unless the user wishes to power it from another source. (i.e. powering LDO from Buck output). The analog VDD inputs power the internal bias and error amplifiers, so they should be tied to the main VDD. The analog VDD inputs must have an input voltage between 2.8 and 5.5 V, as specified in the Electrical Characteristics section of this datasheet. The other Vins (VINLDO1, VINLDO2, VIN1, VIN2) can actually have inputs lower than 2.8V, as long as it's higher than the programmed output (+0.3V, to be safe). The analog and digital grounds should be tied together outside of the chip to reduce noise coupling. For more information on board layout techniques, refer to Application Note AN–1187 “Leadless Lead frame Package (LLP)” on http://www.national.com This application note also discusses package handling, solder stencil and the assembly process. www.national.com 26 LM26480 Board Layout Considerations PC board layout is an important part of DC-DC converter design. Poor board layout can disrupt the performance of a DCDC converter and surrounding circuitry by contributing to EMI, ground bounce, and resistive voltage loss ii the traces. These can send erroneous signals to the DC-DC converter IC, re- sulting in poor regulation or instability. Poor layout can also result in re-flow problems leading to poor solder joints, which can result in erratic or degraded performance. Good layout for the LM26480 bucks can be implemented by following a few simple design rules, as illustrated in Figure 3. 30040468 FIGURE 3. Board Layout Design Rules for the LM26480 1. Place the buck inductor and filter capacitors close together and make the trace short. The traces between these components carry relatively high switching currents and act as antennas. Following this rule reduces radiated noise. Place the capacitors and inductor close to the buck. Arrange the components so that the switching current loops curl in the same direction. During the first halt of each cycle, current flows from the input filter capacitor, through the buck and inductor to the output filter capacitor and back through ground, forming a current loop. In the second half of each cycle, current is pulled up from ground, through the buck by the inductor, to the output filter capacitor and then back through ground, forming a second current loop. Routing these loops so the current curls in the same direction prevents magnetic field reversal between the two half-cycles and reduces radiated noise. Connect the ground pins of the buck, and filter capacitors together using generous component-side copper fill as a pseudo-ground plane. Then connect this to the groundplane (if one is used) with several vias. This reduces ground—plane noise by preventing the switching currents from circulating through the ground plane. it also reduces ground bounce at the buck by giving it a lowimpedance ground connection. 4. Use wide traces between the power components and for power connections to the DC-DC converter circuit. This reduces voltage errors caused by resistive losses across the traces 5. Rout noise sensitive traces, such as the voltage feedback path, away from noisy traces between the power components. The voltage feedback trace must remain close to the buck circuit and should be routed directly from FB to VOUT at the output capacitor and should be routed opposite to noise components. This reduces EMI radiated onto the DC-DC converter’s own voltage feedback trace. In mobile phones, for example, a common practice is to place the DC-DC converter on one corner of the board, arrange the CMOS digital circuitry around it (since this also generates noise), and then place sensitive preamplifiers and IF stages on the diagonally opposing corner. Often, the sensitive circuitry is shielded with a metal pan and power to it is postregulated to reduce conducted noise, using low-dropout linear regulators. 2. 3. 27 www.national.com LM26480 High VIN-High Load Operation Additional inforamtion is provided when the IC is operated at extremes of VIN and regulator loads. These are described in terms of the junction temperature and buck output ripple management. Power dissipation of LDO1 (PLDO1) = (VINLDO1 − VOUTLDO1) * IOUTLDO1 [V*A] Power dissipation of LDO2 (PLDO2) = (VINLDO2 − VOUTLDO2) * IOUTLDO2 [V*A] Power dissipation of Buck1 (PBuck1) = POUT − PIN = VOUTBUCK1 − IOUTBUCK1 * (1 − η2)/ η2 [V*A] η1 = efficiency of Buck1 Power dissipation of Buck2 (PBuck2) = POUT − PIN = VOUTBUCK2 − IOUTBUCK2 * (1 − η2)/ η2 [V*A] η2 = efficiency of Buck2 Where η is the efficiency for the specific condition is taken from efficiency graphs. If VIN and ILOADincrease, the output ripple associated with the Buck Regulators also increases. This mainly occurs with VIN > 5.2V and a load current greater than 1.20A. To ensure operation in this area of operation, it is recommended that the system designer circumvents the output ripple issues by installing Schottky diodes on the bucks(s) that are expected to perform under these extreme conditions. Junction Temperature The maximum junction temperature TJ-MAX-OP of 125°C of the IC package. The following equations demonstrate junction temperature determination, ambient temperature TA-MAX and total chip power ust be controlled to keep TJ below this maximum: TJ-MAX-OP = TA-MAX + (θJA) [°C/Watt] * (PD-MAX) [Watts] Total IC power dissipation PD-MAX is the sum of the individual power dissipation of the four regulators plus a minor amount for chip overhead. Chip overhead is bias, TSD and LDO analog. PD-MAX = PLOD1 + PLDO2 +PBUCK1 + PBUCK2 + (0.0001A * VIN) [Watts]. www.national.com 28 LM26480 Physical Dimensions inches (millimeters) unless otherwise noted 4 X 4 X 0.8 mm 24-Pin LLP Package NS Package SQA24A For ordering, refer to Ordering Information table 29 www.national.com LM26480 Externally Programmable Dual High-Current Step-Down DC/DC and Dual Linear Regulators Notes For more National Semiconductor product information and proven design tools, visit the following Web sites at: www.national.com Products Amplifiers Audio Clock and Timing Data Converters Interface LVDS Power Management Switching Regulators LDOs LED Lighting Voltage References PowerWise® Solutions Temperature Sensors PLL/VCO www.national.com/amplifiers www.national.com/audio www.national.com/timing www.national.com/adc www.national.com/interface www.national.com/lvds www.national.com/power www.national.com/switchers www.national.com/ldo www.national.com/led www.national.com/vref www.national.com/powerwise WEBENCH® Tools App Notes Reference Designs Samples Eval Boards Packaging Green Compliance Distributors Quality and Reliability Feedback/Support Design Made Easy Design Support www.national.com/webench www.national.com/appnotes www.national.com/refdesigns www.national.com/samples www.national.com/evalboards www.national.com/packaging www.national.com/quality/green www.national.com/contacts www.national.com/quality www.national.com/feedback www.national.com/easy www.national.com/solutions www.national.com/milaero www.national.com/solarmagic www.national.com/training Applications & Markets Mil/Aero PowerWise® Design University Serial Digital Interface (SDI) www.national.com/sdi www.national.com/wireless www.national.com/tempsensors SolarMagic™ THE CONTENTS OF THIS DOCUMENT ARE PROVIDED IN CONNECTION WITH NATIONAL SEMICONDUCTOR CORPORATION (“NATIONAL”) PRODUCTS. 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