LM2653_05

LM2653 1.5A High Efficiency Synchronous Switching Regulator April 2005 LM2653 1.5A High Efficiency Synchronous Switching Regulator General Description The LM2653 switching regulator provides high efficient power conversion over a 100:1 load range (1.5A to 15 mA). This feature makes the LM2653 an ideal fit in batterypowered applications. Synchronous rectification is used to achieve up to 97% efficiency. At light loads, the LM2653 enters a low power hysteretic or “sleep” mode to keep the efficiency high. In many applications, the efficiency still exceeds 80% at 15 mA load. A shutdown pin is available to disable the LM2653 and reduce the supply current to 7µA. All the power, control, and drive functions are integrated within the ICs. The ICs contain patented current sensing circuity for current mode control. This feature eliminates the external current sensing resistor required by other currentmode DC-DC converters. The ICs have a 300 kHz fixed frequency internal oscillator. The high oscillator frequency allows the use of extremely small, low profile components. Protection features include thermal shutdown, input undervoltage lockout, adjustable soft-start, cycle by cycle current limit, output overvoltage and undervoltage protections. Features n n n n n n n n n n n n n Efficiency up to 97% 4V to 14V input voltage range 1.5V to 5.0V adjustable output voltage 0.1Ω Switch On Resistance 300 kHz fixed frequency internal oscillator 7 µA shutdown current Patented current sensing for current mode control Input undervoltage lockout Output overvoltage shutdown protection Output undervoltage shutdown protection Adjustable soft-start Adjustable PGOOD delay Current limit and thermal shutdown Applications n n n n n n n n Webpad Personal digital assistants (PDAs) Computer peripherals Battery-powered devices Notebook computer video supply Handheld scanners GXM I/O and core voltage High efficiency 5V conversion Typical Application Efficiency vs Load Current (VIN = 5V, VOUT = 3.3V) 10104930 10104902 © 2005 National Semiconductor Corporation DS101049 www.national.com LM2653 Absolute Maximum Ratings (Note 1) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Input Voltage PGOOD Pin Voltage Feedback Pin Voltage Power Dissipation (TA =25˚C), (Note 2) Junction Temperature Range Storage Temperature Range −40˚C ≤ TJ ≤ +125˚C −65˚C to +150˚C 893 mW 15V 15V −0.4V ≤ VFB ≤ 5V Lead Temperature M Package Vapor Phase (60 sec.) Infrared (15 sec.) Maximum Junction Temperature ESD Susceptibility Human Body Model (Note 3) 1 kV 215˚C 220˚C 150˚C Operating Ratings (Note 1) Supply Voltage 4V ≤ VIN ≤ 14V Electrical Characteristics Specifications with standard typeface are for TJ = 25˚C, and those in boldface type apply over full Operating Temperature Range. VIN = 10V unless otherwise specified. Symbol VFB Parameter Feedback Voltage Conditions ILOAD = 900 mA Typical (Note 5) 1.238 1.200 1.263 VOUT Output Voltage Line Regulation Output Voltage Load Regulation Output Voltage Load Regulation VINUV VUV_HYST ICL VIN Undervoltage Lockout Threshold Voltage Hysteresis for the Input Undervoltage Lockout Switch Current Limit VIN = 5V VOUT = 2.5V VIN = 5V, VOUT = 2.5V VIN = 4V to 12V ILOAD = 900 mA ILOAD = 10 mA to 1.5A VIN = 5V ILOAD = 200 mA to 1.5A VIN = 5V Rising Edge 0.2 1.3 0.3 3.8 3.95 210 2.0 1.55 2.60 100 24 1.7 2.0 IQSD RDS(ON) RSW(ON) Quiescent Current in Shutdown Mode High-Side or Low-Side MOSFET ON Resistance High-Side or Low-Side Switch On Resistance (MOSFET ON Resistance + Bonding Wire Resitstance) Switch Leakage Current — High Side Switch Leakge Current — Low Side Shutdown Pin Pulled Low ISWITCH = 1A ISWITCH = 1A 7 12/20 75 130 110 Limit (Note 4) Units V V(min) V(max) % % % V V(max) mV A A(min) A(max) mA mV mA mA(max) µA µA(max) mΩ mΩ (max) mΩ ISM VHYST IQ Sleep Mode Threshold Current Sleep Mode Feedback Voltage Hysteresis Quiescent Current IL 130 130 nA nA www.national.com 2 LM2653 Electrical Characteristics (Continued) Specifications with standard typeface are for TJ = 25˚C, and those in boldface type apply over full Operating Temperature Range. VIN = 10V unless otherwise specified. Symbol VBOOT Parameter Conditions Typical (Note 5) 6.75 6.45/6.40 6.95/7.00 GM AV IEA_SOURCE IEA_SINK VEAH VEAL VD FOSC Error Amplifier Transconductance Error Amplifier Voltage Gain Error Amplifier Source Current Error Amplifier Sink Current VIN = 3.6V, VFB = 1.17V, VCOMP = 2V VIN = 3.6V, VFB = 1.31V, VCOMP = 2V 1250 100 40 25/15 65 30 Error Amplifier Output Swing VIN = 4V, VFB = 1.17V Upper Limit Error Amplifier Output Swing VIN = 4V, VFB = 1.31V Lower Limit Body Diode Voltage Oscillator Frequency IDIODE = 1.5A Measured at Switch Pin VIN = 4V VIN = 4V Voltage at the SS Pin = 1.4V 2.70 2.50/2.40 1.25 1.35/1.50 1 300 280/255 330/345 95 92 ISS Soft-Start Current 11 7 14 VOUTUV VOUT Undervoltage Lockout Threshold Voltage Hysteresis for VOUTUV VOUTOV VOUT Overvoltage Lockout Threshold Voltage Hysteresis for VOUTOV ILDELAY__ SOURCE Limit (Note 4) Units V V(min) V(max) µmho Bootstrap Regulator Voltage IBOOT = 1 mA µA µA(min) µA µA(min) V V(min) V V(max) V kHz kHz(min) kHz(max) % %(min) µA µA(min) µA(max) %VOUT %VOUT(min) %VOUT(max) %VOUT %VOUT %VOUT(min) %VOUT(max) %VOUT µA DMAX Maximum Duty Cycle 81 76 84 5 108 106 114 3 5 VPGOOD = 0.4V VPGOOD = 5V Shutdown Pin Pulled Low 50 2.2 0.8/0.5 3.7/4.0 15 LDELAY Pin Source Current PGOOD Pin Sink Current IPGOOD__SINK mA(max) nA µA µA(min) µA(max) V V(min) V(max) ˚C ˚C IPGOOD__LEAKAGE PGOOD Pin Leakage Current ISHUTDOWN Shutdown Pin Current VSHUTDOWN Shutdown Pin Threshold Voltage Thermal Shutdown Temperature Thermal Shutdown Hysteresis Temperature Rising Edge 0.6 0.3 0.9 165 25 TSD TSD_HYST Note 1: Absolute Maxmum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is intended to be functional, but device parameter specifications may not be guaranteed under these conditions. For guaranteed specifications and test conditions, see the Electrical Characteristics. 3 www.national.com LM2653 Electrical Characteristics (Continued) Note 2: The maximum allowable power dissipation is calculated by using PDMAX = (TJMAX − TA)/θJA, where TJMAX is the maximum junction temperature, TA is the ambient temperature, and θJA is the junction-to-ambient thermal resistance of the specified package. The 893 mW rating results from using 150˚C, 25˚C, and 140˚C/W for TJMAX, TA, and θJA respectively. A θJA of 140˚C/W represents the worst-case condition of no heat sinking of the 16-pin TSSOP package. Heat sinking allows the safe dissipation of more power. The Absolute Maximum power dissipation must be derated by 7.14 mW per ˚C above 25˚C ambient. The LM2653 actively limits its junction temperatures to about 165˚C. Note 3: The human body model is a 100 pF capacitor discharged through a 1.5 kΩ resistor into each pin. Note 4: Typical numbers are at 25˚C and represent the most likely norm. Note 5: All limits guaranteed at room temperature (standard typeface) and at temperature extremes (bold typeface). All room temperature limits are 100% production tested. All limits at temperature extremes are guaranteed via correlation using standard Statistical Quality Control (SQC) methods. All limits are used to calculate Average Outgoing Quality Level (AOQL). Typical Performance Characteristics Efficiency vs Load Current (VIN = 5V, VOUT = 2.5V) lQ vs VIN 10104922 10104904 IQSD vs Input Voltage IQSD vs Junction Temperature 10104925 10104926 Frequency vs Junction Temperature RSW(ON) vs Input Voltage 10104907 10104923 www.national.com 4 LM2653 Typical Performance Characteristics RSW(ON) vs Junction Temperature (Continued) Current Limit vs Input Voltage (VOUT = 2.5V) 10104924 10104927 Current Limit vs Junction Temperature (VOUT = 2.5V) Reference Voltage vs Junction Temperature 10104928 10104929 Sleep Mode Threshold vs Output Voltage (VIN = 5V) 10104931 5 www.national.com LM2653 Connection Diagram 16-Lead TSSOP (MTC) 10104914 Top View Order Number LM2653MTC-ADJ See NS Package Number MTC16 Pin Description Pin 1-2 3-5 6 7 8 Name SW VIN VCB AVIN SD(SS) Function Switched-node connection, which is connected with the source of the internal high-side MOSFET. Main power supply input pin. Connected to the drain of the high-side MOSFET. Bootstrap capacitor connection for high-side gate drive. Input voltage for control and driver circuits. Shutdown and Soft-start control pin. Pulling this pin below 0.3V shuts off the regulator. A capacitor connected from this pin to ground provides a control ramp of the input current. Do not drive this pin with an external source or erroneous operation may result. Output voltage feedback input. Connected to the output voltage. Compensation network connection. Connected to the output of the voltage error amplifier. A constant monitor on the output voltage. PGOOD will go low if the output voltage exceeds 110% or goes below 80% of its nominal. A capacitor between this pin to ground sets the delay from the output voltage reaches 80% of its nominal to when the undervoltage latch protection is enabled and PGOOD pin goes low. Low-noise analog ground. Power ground. 9 10 11 12 FB COMP PGOOD LDELAY 13 14-16 AGND PGND www.national.com 6 LM2653 Block Diagram 10104915 Operation The LM2653 operates in a constant frequency (300 kHz), current-mode PWM for moderate to heavy loads; and it automatically switches to hysteretic mode for light loads. In hysteretic mode, the switching frequency is reduced to keep the efficiency high. MAIN OPERATION When the load current is higher than the sleep mode threshold, the part is always operating in PWM mode. At the beginning of each switching cycle, the high-side switch is turned on, the current from the high-side switch is sensed and compared with the output of the error amplifier (COMP pin). When the sensed current reaches the COMP pin voltage level, the high-side switch is turned off; after 40 ns (deadtime), the low-side switch is turned on. At the end of the switching cycle, the low-side switch is turned off; and the same cycle repeats. The current of the top switch is sensed by a patented internal circuitry. This unique technique gets rid of the external sense resistor, saves cost and size, and improves noise immunity of the sensed current. A feedforward from the input voltage is added to reduce the variation of the current limit over the input voltage range. When the load current decreases below the sleep mode theshold, the output voltage will rise slightly, this rise is sensed by the hysteretic mode comparator which makes the 7 part go into the hysteretic mode with both the high and low side switches off. The output voltage starts to drop until it hits the low threshold of the hysteretic comparator, and the part immediately goes back to the PWM operation. The output voltage keeps increasing until it reaches the top hysteretic threshold, then both the high and low side switches turn off again, and th same cycle repeats. PROTECTIONS The cycle-by-cycle current limit circuitry turns off the highside MOSFET whenever the current in MOSFET reaches 2A. A second level current limit is accomplished by the undervoltage protection: if the load pulls the output voltage down below 80% of its nominal value, the undervoltage latch protection will wait for a period of time (set by the capacitor at the LDELAY pin, see LDELAY CAPACITOR section for more information). If the output voltage is still below 80% of its nominal after the waiting period, the latch protection will be enabled. In the latch protection mode, the low-side MOSFET is on and the high-side MOSFET is off. The latch protection will also be enabled immediately whenever the output voltage exceeds the overvoltage threshold (110% of its nominal). Both protections are disabled during startup.(See SOFT-START CAPACITOR section and LDELAY www.national.com LM2653 Operation (Continued) CAPACITOR section for more information.) Toggling the input supply voltage or the shutdown pin can reset the device from the latched protection mode. PGOOD FLAG The PGOOD flag goes low whenever the overvoltage or undervoltage latch protection is enabled. Design Procedure This section presents guidelines for selecting external components. INPUT CAPACITOR A low ESR aluminum, tantalum, or ceramic capacitor is needed betwen the input pin and power ground. This capacitor prevents large voltage transients from appearing at the input. The capacitor is selected based on the RMS current and voltage requirements. The RMS current is given by: num) is recommended. An electrolytic capacitor is not recommended for temperatures below −25˚C since its ESR rises dramatically at cold temperature. A tantalum capacitor has a much better ESR specification at cold temperature and is preferred for low temperature applications. The output voltage ripple in constant frequency mode has to be less than the sleep mode voltage hysteresis to avoid entering the sleep mode at full load: VRIPPLE < 20mV * VOUT /VFB BOOST CAPACITOR A 0.1 µF ceramic capacitor is recommended for the boost capacitor. The typical voltage across the boost capacitor is 6.7V. SOFT-START CAPACITOR A soft-start capacitor is used to provide the soft-start feature. When the input voltage is first applied, or when the SD(SS) pin is allowed to go high, the soft-start capacitor is charged by a current source (approximately 2 µA). When the SD(SS) pin voltage reaches 0.6V (shutdown threshold), the internal regulator circuitry starts to operate. The current charging the soft-start capacitor increases from 2 µA to approximately 10 µA. With the SD(SS) pin voltage between 0.6V and 1.3V, the level of the current limit is zero, which means the output voltage is still zero. When the SD(SS) pin voltage increases beyond 1.3V, the current limit starts to increase. The switch duty cycle, which is controlled by the level of the current limit, starts with narrow pulses and gradually gets wider. At the same time, the output voltage of the converter increases towards the nominal value, which brings down the output voltage of the error amplifier. When the output of the error amplifier is less than the current limit voltage, it takes over the control of the duty cycle. The converter enters the normal current-mode PWM operation. The SD(SS) pin voltage is eventually charged up to about 2V. The soft-start time can be estimated as: TSS = CSS * 0.6V/2 µA + CSS * (2V−0.6V)/10 µA During start-up, the internal circuit is monitoring the soft-start voltage. When the softstart voltage reaches 2V, the undervoltage and overvoltage protections are enabled. If the output voltage doesn’t rise above 80% of the normal value before the soft-start reaches 2V. The undervoltage protection will kick in and shut the device down. You can avoid this by either increasing the value of the soft-start capacitor, or using a LDELAY capacitor. LDELAY CAPACITOR As mentioned in the operation section, the LDELAY capacitor sets the time delay between the output voltage goes below 80% of its nominal value and the undervoltage latch protection is enabled. Charging the CDELAY by a 5 µA current source up to 2V sets the delay time. Therefore, TDELAY = CDELAY * 2V/5µA. The undervoltage protection is disabled by tying the LDELAY pin to the ground. The RMS current reaches its maximum (IOUT/2) when VIN equals 2VOUT. For an aluminum or ceramic capacitor, the voltage rating should be at least 25% higher than the maximum input voltage. If a tantalum capacitor is used, the voltage rating required is about twice the maximum input voltage. The tantalum capacitor should be surge current tested by the manufacturer to prevent shorted by the inrush current. It is also recommended to put a small ceramic capacitor (0.1 µF) between the input pin and ground pin to reduce high frequency spikes. INDUCTOR The most critical parameters for the inductor are the inductance, peak current and the DC resistance. The inductance is related to the peak-to-peak inductor ripple current, the input and the output voltages: A higher value of ripple current reduces inductance, but increases the conductance loss, core loss, current stress for the inductor and switch devices. It also requires a bigger output capacitor for the same output voltage ripple requirement. A reasonable value is setting the ripple current to be 30% of the DC output current. Since the ripple current increases with the input voltage, the maximum input voltage is always used to determine the inductance. The DC resistance of the inductor is a key parameter for the efficiency. Lower DC resistance is available with a bigger winding area. A good tradeoff between the efficiency and the core size is letting the inductor copper loss equal 2% of the output power. OUTPUT CAPACITOR The selection of COUT is driven by the maximum allowable output voltage ripple. The output ripple in the constant frequency, PWM mode is approximated by: The ESR term usually plays the dominant role in determining the voltage ripple. A low ESR aluminum electrolytic or tantalum capacitor (such as Nichicon PL series, Sanyo OS-CON, Sprague 593D, 594D, AVX TPS, and CDE polymer alumiwww.national.com 8 LM2653 Design Procedure (Continued) R1 and R2 (PROGRAMMING OUTPUT VOLTAGE) Use the following formula to select the appropriate resistor values: VOUT = VREF(1 + R1/R2) where VREF = 1.238V Select resistors between 10kΩ and 100kΩ. (1% or higher accuracy metal film resistors for R1 and R2.) COMPENSATION COMPONENTS In the control to output transfer function, the first pole Fp1 can be estimated as 1/(2πROUTCOUT); The ESR zero Fz1 of the output capacitor is 1/(2πESRCOUT); Also, there is a high frequency pole Fp2 in the range of 45kHz to 150kHz: Fp2 = Fs/(πn(1−D)) where D = VOUT/VIN, n = 1+0.348L/(VIN−VOUT) (L is in µHs and VIN and VOUT in volts). The total loop gain G is approximately 500/IOUT where IOUT is in amperes. A Gm amplifier is used inside the LM2653. The output resistor Ro of the Gm amplifier is about 80kΩ. Cc1 and RC together with Ro give a lag compensation to roll off the gain: Fpc1 = 1/(2πCc1(Ro+Rc)), Fzc1 = 1/2πCc1Rc. In some applications, the ESR zero Fz1 can not be cancelled by Fp2. Then, Cc2 is needed to introduce Fpc2 to cancel the ESR zero, Fp2 = 1/(2πCc2Ro\Rc). The rule of thumb is to have more than 45˚ phase margin at the crossover frequency (G=1). If COUT is higher than 68µF, Cc1 = 2.2nF, and Rc = 15KΩ are good choices for most applications. If the ESR zero is too low to be cancelled by Fp2, add Cc2. If the transient response to a step load is important, choose RC to be higher than 10kΩ. EXTERNAL SCHOTTKY DIODE A Schottky diode D1 is recommended to prevent the intrinsic body diode of the low-side MOSFET from conducting during the deadtime in PWM operation and hysteretic mode when both MOSFETs are off. If the body diode turns on, there is extra power dissipation in the body diode because of the reverse-recovery current and higher forward voltage; the high-side MOSFET also has more switching loss since the negative diode reverse-recovery current appears as the high-side MOSFET turn-on current in addition to the load current. These losses degrade the efficiency by 1-2%. The improved efficiency and noise immunity with the Schottky diode become more obvious with increasing input voltage and load current. The breakdown voltage rating of D1 is preferred to be 25% higher than the maximum input voltage. Since D1 is only on for a short period of time, the average current rating for D1 only requires being higher than 30% of the maximum output current. It is important to place D1 very close to the drain and source of the low-side MOSFET, extra parasitic inductance in the parallel loop will slow the turn-on of D1 and direct the current through the body diode of the low-side MOSFET. PCB Layout Considerations Layout is critical to reduce noises and ensure specified performance. The important guidelines are listed as follows: Minimize the parasitic inductance in the loop of input capacitors and the internal MOSFETs by connecting the input capacitors to VIN and PGND pins with short and wide traces. This is important because the rapidly switching current, together with wiring inductance can generate large voltage spikes that may result in noise problems. 2. Minimize the trace from the center of the output resistor divider to the FB pin and keep it away from noise sources to avoid noise pick up. For applications require tight regulation at the output, a dedicated sense trace (separated from the power trace) is recommended to connect the top of the resistor divider to the output. 3. If the Schottky diode D1 is used, minimize the traces connecting D1 to SW and PGND pins. 1. 10104901 Schematic for the Typical Board Layout 9 www.national.com LM2653 Typical PC Board Layout: (2X Size) 10104919 Component Placement Guide 10104920 Component Side PC Board Layout www.national.com 10 LM2653 Typical PC Board Layout: (2X Size) (Continued) 10104921 Solder Side PC Board Layout 11 www.national.com LM2653 1.5A High Efficiency Synchronous Switching Regulator Physical Dimensions unless otherwise noted inches (millimeters) 16-Lead TSSOP (MTC) Order Number LM2653MTC-ADJ NS Package Number MTC16 National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications. For the most current product information visit us at www.national.com. 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