LM27402MH

LM27402 High Performance Synchronous Buck Controller with DCR Current Sensing September 2, 2010 LM27402 High Performance Synchronous Buck Controller with DCR Current Sensing General Description The LM27402 is a synchronous voltage mode DC/DC buck controller with inductor DCR current sense capability. Sensing the inductor current eliminates the need to add resistive powertrain elements which increases overall efficiency and facilitates accurate continuous current limit sensing. A 0.6V ±1% voltage reference enables high accuracy and low voltage capability at the output. An input operating voltage range of 3V to 20V makes the LM27402 suitable for a large variety of input rails. The LM27402 voltage mode control loop incorporates input voltage feed-forward to maintain stability throughout the entire input voltage range. The switching frequency is adjustable from 200 kHz to 1.2 MHz. Dual high current integrated Nchannel MOSFET drivers support large QG, low RDS(ON) MOSFETs. A power good indicator provides power rail sequencing capability and output fault detection. Adjustable external soft-start capability limits inrush current and provides monotonic output control during startup. Other features include external tracking of other power supplies, integrated LDO bias supply, and synchronization capability. The LM27402 is offered in a 16 pin eTSSOP package and a 4 mm x 4 mm 16 pin exposed LLP. Features ■ Input operating voltage range of 3V to 20V ■ Continuous inductor DCR or shunt resistor current sensing ■ 0.6V ±1% reference (-40°C to 125°C junction ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ temperature) Output voltage as high as 95% of input voltage Integrated MOSFET drivers Internal LDO bias supply External clock synchronization Adjustable soft-start with external capacitor Pre-biased startup capability Power supply tracking Input voltage feed-forward Power good indicator Precision enable with hysteresis Applications ■ High current, low voltage FPGA/ASIC DC/DC converters ■ General purpose high current buck converters ■ Telecom, datacom, networking, distributed power architectures Typical Application Circuit 30092601 PowerWise® is a registered trademark of National Semiconductor Corporation. © 2010 National Semiconductor Corporation 300926 www.national.com LM27402 Connection Diagrams 30092602 Top View eTSSOP-16 Package 4.4 mm x 5 mm x 0.9 mm 0.65 mm PITCH 30092605 Top View LLP-16 Package 4 mm x 4 mm x 0.8 mm 0.65 mm PITCH Ordering Information Order Number LM27402MH LM27402MHX Order Number LM27402SQ LM27402SQX Package Type LLP-16 NSC Package Drawing SQB16A Package Type eTSSOP-16 NSC Package Drawing MXA16A Supplied As Coming Soon Coming Soon Supplied As 1000 Units per Tape and Reel 4500 Units per Tape and Reel www.national.com 2 LM27402 Pin Descriptions eTSSOP Pin # 1 2 3 LLP Pin # 16 15 1 CS+ CSSS/TRACK Name Description Non-inverting input to the current sense comparator. Inverting input to the current sense comparator with +10 µA offset current for adjustable current limit setpoint. Soft-start or tracking input. A startup rate can be defined with the use of an external soft-start capacitor from SS/TRACK to GND. A +3 µA current source charges the soft-start capacitor to set the output voltage rise time during startup. SS/TRACK can also be controlled with an external voltage source for tracking. SS/TRACK should not exceed the voltage on VDD. Inverting input to the error amplifier to set the output voltage and compensate the voltage mode control loop. Output of the internal error amplifier. The COMP voltage is compared to an internally generated ramp of the PWM comparator to establish the duty cycle command. Frequency adjust pin. The switching frequency can be set to a predetermined rate by connecting a resistor between FADJ and GND. Frequency synchronization pin. An external clock signal can be applied to SYNC to set the switching frequency. The SYNC frequency must be greater than the frequency set by the FADJ pin. If the signal is not present, the switching frequency will decrease to the frequency set by the FADJ resistor. SYNC should not exceed the voltage on VDD and should be grounded if not used. LM27402 enable pin. Apply a voltage typically higher than 1.17V to EN and the LM27402 will begin to switch if VIN and VDD have exceeded the UVLO voltage. A hysteresis of 100 mV on EN provides noise immunity. EN is internally tied to VDD through a 2 µA pullup current source. EN should not exceed the voltage on VDD. Power good output flag. PGOOD is connected to the drain of a pulldown FET. The PGOOD pin is typically connected to VDD through a pull-up resistor. Input supply rail. The VIN operating range is 3V to 20V and is connected to the input rail through an RC filter. Common ground. Internal sub-regulated 4.5V bias supply. VDD is used to supply the voltage on CBOOT to facilitate high-side FET switching. Connect a 1 µF ceramic capacitor from VDD to GND as close as possible to the LM27402. VDD cannot be connected to a separate voltage rail. However, VDD can be connected to VIN to provide increased gate drive only if VIN ≤ 5.5V. A 1Ω, 1 µF input filter can be used for increased noise rejection. 13 14 15 16 EP 11 12 14 13 EP LG SW HG CBOOT EP Low-side N-FET gate drive. Switch-node connection and return path for the high-side gate driver. High-side N-FET gate drive. High-side gate driver supply rail. Connect a ceramic capacitor from CBOOT to SW and a Schottky diode from VDD to CBOOT. Exposed Pad. The EP must be connected to GND but cannot be used as the primary ground connection. Use multiple vias under this pad for optimal thermal performance. 4 5 2 3 FB COMP 6 7 4 6 FADJ SYNC 8 5 EN 9 10 11 12 8 7 9 10 PGOOD VIN GND VDD 3 www.national.com LM27402 Absolute Maximum Ratings (Note 1) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Unless otherwise specified, voltages are from the indicated pins to GND. VIN, CS+, CS-, SW VDD, PGOOD EN, SYNC, SS/TRACK, FADJ, COMP, FB, LG CBOOT CBOOT to SW CS+ to CSStorage Temperature Junction Temperature Lead Temperature (Soldering, 10 sec) Minimum ESD Rating (Note 2) Operating Ratings Input Voltage Range (Note 3) VIN VIN (VDD = VIN) VDD to GND SS/TRACK, SYNC, EN PGOOD Junction Temperature θJA (LLP-16) (Note 4) θJA (eTSSOP-16) (Note 4) (Note 1) +3.0V to +20V +3.0V to +5.5V +2.2V to +5.5V 0V to VVDD 0V to +5.5V -40°C to + 125°C 40°C/W 40°C/W -0.3V to +22V -0.3V to +6V -0.3V to VDD -0.3V to +24V +6V -2V to +2V -65°C to 150°C 150°C 260°C ±2kV Unless otherwise stated, the following conditions apply: VIN = 12V. Limits in standard type are for TJ = 25°C only, limits in bold face type apply over the junction temperature (TJ) range of -40°C to +125°C. Minimum and maximum limits are guaranteed through test, design, or statistical correlation. Typical values represent the most likely parametric norm at TJ = 25°C and are provided for reference purposes only. Electrical Characteristics System Parameters Symbol IQ IQSD UVLO UVLO UVLOHYS REFERENCE VFB IFB SWITCHING FSW FSW FSW DMAX TOFF_MIN VDD BW-3db AVOL VSLEW_RISE VSLEW_FALL ISOURCE ISINK VCOMP_MAX VCOMP_MIN www.national.com Parameter Quiescent Current Quiescent Current In Shutdown Input Under Voltage Lockout UVLO Hysteresis Feedback Voltage Feedback Pin Bias Current Switching Frequency Switching Frequency Switching Frequency Maximum Duty Cycle Minimum Off Time Sub-Regulator Output Voltage Open Loop Bandwidth Error Amp DC Gain Error Amplifier Rising Slew Rate Error Amplifier Falling Slew Rate COMP Source Current COMP Sink Current Max COMP Voltage Min COMP Voltage Conditions VFB = 0.6V (not switching) VEN = 0V VVIN Rising, VVDD Rising VVIN Falling, VVDD Falling Min Typ 4.5 25 Max 6.0 45 2.99 Units mA µA V mV OPERATIONAL SPECIFICATIONS 2.7 2.9 300 0.594 VFB = 0.65V RFADJ = 4.12 kΩ RFADJ = 20 kΩ RFADJ = 95.3 kΩ FSW = 300 kHz VFB = 0.5V IDD = 25 mA -50 950 400 175 93 125 4.0 0.600 0 1150 500 214 95 165 4.5 2 50 0.606 50 1350 600 265 205 5.0 V nA kHz kHz kHz % ns V MHz dB V/µs V/µs mA mA V V VDD SUB-REGULATOR ERROR AMPLIFIER VFB = 0.5V VFB = 0.7V VFB = 0.5V VFB = 0.7V VFB = 0.5V VFB = 0.7V 4 5 3 8 4 12 12 3.1 0.5 LM27402 Symbol OVER CURRENT VOFFSET ICSGATE DRIVE RDSON1 RDSON2 RDSON3 RDSON4 TDT SOFT-START ISS RSS_PD TSS_INT IPGS IPGL OVT OVT_HYS UVT UVT_HYS TDEGLITCH ENABLE VEN VEN_HYS IEN VLH_SYNC VLL_SYNC SYNCFSW_L SYNCFSW_H TSHD TSHD_HYS Parameter Comparator Voltage Offset Current Limit Offset Current High-Side FET Driver Pull-Up On Resistance High-Side FET Driver Pull-Down On Resistance Low-Side FET Driver Pull-Up On Resistance Low-Side FET Driver Pull-Down On Resistance Deadtime Timeout Soft-Start Source Current Soft-Start Pull-Down Resistance Internal Soft-Start Time PGOOD Low Sink Current PGOOD Leakage Current Over-Voltage Threshold OVT Hysteresis Under-Voltage Threshold UVT Hysteresis Deglitch Time Enable Logic High Threshold Enable Hysteresis Enable Pin Pull-Up Current SYNC Pin Logic High SYNC Pin Logic Low Minimum Clock Sync Frequency Maximum Clock Sync Frequency Thermal Shutdown Thermal Shutdown Hysteresis Conditions Min -5 Typ 0 10.0 Max 5 10.5 Units mV µA VCS- = 5V VCBOOT - VSW = 4.7V, IHG = +100 mA VCBOOT - VSW = 4.7V, IHG = -100 mA VVDD = 4.7V, ILG = +100 mA VVDD = 4.7V, ILG = -100 mA FSW = 500 kHz VSS/TRACK = 0V VSS/TRACK = 0.6V 9.5 1.7 1.2 1.7 1.0 40 2 3 288 1.28 4 Ω Ω Ω Ω ns µA Ω ms µA 10 120 97 µA % % % % µs 1.24 V mV µA V 0.8 V kHz 1200 kHz °C °C POWERGOOD VPGOOD = 0.2V, VFB = 0.75V VPGOOD = 5V VFB Rising VFB Falling VFB Rising VFB Falling VPGOOD Rising and Falling VEN Rising VEN Falling VEN = 0V VVDD = 4.7V VVDD = 4.7V 200 2.0 1.10 91 114 60 100 1 117 2 94 3 20 1.17 100 2 FREQUENCY SYNCHRONIZATION THERMAL SHUTDOWN Temperature Rising Temperature Falling 165 15 Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is intended to be functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. Note 2: The human body model is a 100 pF capacitor discharged through a 1.5 kΩ resistor to each pin. Note 3: VDD is the output of an internal linear regulator. Under normal operating conditions where VIN is greater than 5.5V, VDD must not be connected to any external voltage source. In an application where VIN is between 3.0V and 5.5V, it is recommended to connect VDD to VIN. In order to have better noise rejection under these conditions, a 1Ω and 1µF RC input filter may be used. Note 4: Tested on a four layer JEDEC board. Four vias are provided under the LLP exposed pad and nine vias are provided under the eTSSOP exposed pad. 5 www.national.com LM27402 Typical Performance Characteristics using example circuit 1 at the end of this datasheet. VIN = 12V. Efficiency (Vout = 1.5V) Unless otherwise stated, all data sheet curves were recorded Efficiency ( Vout = 5V, Example Circuit 2) 30092679 30092680 Efficiency (Vout = 3.3V, Example Circuit 2) Load Regulation (Vout = 1.5V) 30092603 30092653 Line Regulation (Vout = 1.5V) VDD Voltage vs Temperature (IVDD = 25mA) 30092667 30092607 www.national.com 6 LM27402 Frequency vs Temperature (RFADJ = 20kΩ) Frequency vs RFADJ 30092609 30092639 CS- Current Source vs Temperature Deadtime vs Temperature 30092663 30092638 CS- Current Source Compliance Voltage Load Transient 30092637 100 µs/DIV 30092635 7 www.national.com LM27402 Startup Waveforms Pre-Bias Startup Waveforms 30092636 2 ms/DIV 2 ms/DIV 30092691 OCP Hiccup Sync 30092692 30092693 2 ms/DIV 400 ns/DIV Tracking Shutdown Quiescent Current vs Temperature 30092694 2 ms/DIV 30092634 www.national.com 8 LM27402 Quiescent Current vs Temperature Feedback Voltage vs Temperature 30092689 30092688 9 www.national.com LM27402 Block Diagram 30092610 www.national.com 10 LM27402 Theory of Operation GENERAL INFORMATION The LM27402 is a single-phase synchronous voltage mode DC/DC buck controller. The inductor DCR sense capability and integrated low impedance gate drivers allow the LM27402 to be used in high current, high power density applications. Multiple fault conditions are supported including over-voltage, under-voltage, over-temperature, and over-current. The switching frequency can be adjusted over a wide range either by connecting a clock signal to SYNC pin or a resistor from FADJ to GND. The LM27402 supports pre-biased outputs while maintaining synchronous mode operation. Input voltage feed-forward is incorporated into the control loop to mitigate the effects of input voltage variation. UVLO An under-voltage lockout is built into the LM27402 which allows the device to only switch if the input voltage (VIN) and the internal sub-regulated voltage (VDD) both exceed 2.9V. A 300mV UVLO hysteresis exists on both VDD and VIN to prevent power on and off anomalies related to input voltage deviations. PRECISION ENABLE (EN) The enable pin of the LM27402 allows the output to be toggled on and off and is a precision analog input. When the EN voltage exceeds 1.17V, the controller will initiate the soft-start sequence as long as the input voltage and sub-regulated voltage have exceeded their UVLO thresholds of 2.9V. The EN pin has an absolute maximum voltage rating of 6.0V and should not exceed the voltage on VDD. There is an internal 2 µA pull-up current source connected to the EN pin. If EN is open, the LM27402 will turn on automatically if VIN and VDD exceed 2.9V. If the EN voltage is held below 0.8V, the LM27402 enters a deep shutdown state where the internal bias circuitry is off. The quiescent current is approximately 35 µA in deep shutdown. The EN pin has 100mV of hysteresis to reject noise and allow the pin to be resistively coupled to the input voltage or sequenced with other rails. SOFT-START AND VOLTAGE TRACKING (SS/TRACK) When the enable pin has exceeded 1.17V and both VIN and VDD have exceeded their UVLO thresholds, the LM27402 will begin charging the output linearly to the voltage level dictated by the feedback resistor network. The soft-start time is set by connecting a capacitor from SS/TRACK to GND. After EN exceeds 1.17V, an internal 3 µA current source begins to linearly charge the soft-start capacitor. Soft-start allows the user to limit inrush currents related to high output capacitance and output slew rate. If a soft-start capacitor is not used, the LM27402 defaults to a 1.28 ms digitally controlled startup time. The SS/TRACK pin can also be used to ratiometrically or coincidentally track an external voltage source. See the SETTING THE SOFT-START TIME and TRACKING sections of the design guide for more information. PRE-BIAS STARTUP In certain applications, the output may acquire a pre-bias voltage before the LM27402 is powered on or enabled. Pre- biased conditions are managed by preventing switching until the soft-start (SS/TRACK) voltage exceeds the feedback (FB) voltage. Once VSS/TRACK has exceeded VFB, the LM27402 will begin to switch synchronously and regulate the output voltage. 30092645 FIGURE 1. Pre-Bias Startup Prohibiting switching during a pre-biased startup condition prevents the output from forcing parasitic paths to conduct excessive current. The LM27402 will not switch if the output is pre-biased to a voltage higher than the nominally set output voltage. CURRENT LIMIT The LM27402 may enter two states when a current limit event is detected. If a current limit condition has occurred, the highside FET is immediately turned off until the next switching cycle. This is considered the first current limit state and provides an immediate response to any current limit event. During the first state, an internal counter will begin to record the number of over-current events. The counter is reset if 32 consecutive switching cycles occur with no current limit events detected. If five over-current events are detected within 32 switching cycles, the LM27402 then enters into a hiccup mode state. During hiccup mode, the LM27402 will shutdown for 1.28 ms and then attempt to restart again. When transitioning into hiccup mode, the high-side FET is turned off and the lowside FET is turned on. As the inductor current reaches zero subsequent to the over-current event, the low-side FET is turned off and the switch-node becomes high impedance to prepare for the next startup sequence. The soft-start capacitor is discharged through an internal pull-down FET to reinitialize the startup sequence. To illustrate how the LM27402 behaves during current limit faults, an over-current scenario is illustrated in Figure 2. 11 www.national.com LM27402 30092622 FIGURE 2. Current Limit Timing Diagram In the example shown in Figure 2, the LM27402 immediately turns off the high-side FET when an over-current pulse is detected. After the third over-current event is detected, 24 switching cycles occur before the fourth over-current pulse is detected. Since the current limit logic does not count 32 switching cycles between two over-current events, the internal current limit counter is not reset and continues counting until the LM27402 enters hiccup mode. The soft-start capacitor is then discharged to initialize startup and a wait period of 1.28 ms occurs. NEGATIVE CURRENT LIMIT To prevent excess negative current, the LM27402 implements a negative current limit through the low-side FET. Negative current limit is only enabled when an over-voltage event is detected. Should an over-voltage fault occur, the lowside FET will turn off if the SW pin voltage exceeds a positive 100mV during the low-side on time, thereby protecting the powertrain from excessive negative current. POWER GOOD The PGOOD pin of the LM27402 is used to signal when the output is out of regulation or during non-regulated pre-biased conditions. This means that current limit, UVLO, over-voltage threshold, under-voltage threshold, or a non regulated output will cause the PGOOD pin to pull low. To prevent glitches to PGOOD, a 20 μs de-glitch filter is built into the LM27402. Figure 3 illustrates when the PGOOD flag is asserted low. www.national.com 12 LM27402 30092664 FIGURE 3. Power Good Behavior THERMAL PROTECTION Internal thermal shutdown is provided to protect the controller in the event that the maximum junction temperature of approximately 165°C has been exceeded. Both the high-side and low-side FETs are turned off during this condition. During a thermal fault condition, PGOOD is held at logic zero. 13 www.national.com LM27402 Design Guide The Design Guide assists the designer with the steps necessary to select the external components to build a fully functional power supply. As with any DC-DC converter numerous tradeoffs are possible to optimize the design for efficiency, size, or performance. These tradeoffs will be taken into account and highlighted throughout the discussion. To facilitate component selection, the circuit shown in Figure 4 below may be used as a reference. Unless otherwise indicated, all formulae assume units of Amps (A) for current, Farads (F) for capacitance, Henries (H) for inductance and Volts (V) for voltage. 30092670 FIGURE 5. Switch Voltage and Inductor Current Waveforms The peak inductor current at maximum load, IOUT + ΔIL/2, should be kept adequately below the peak current limit setpoint of the device. 30092601 FIGURE 4. Typical Application Circuit The above schematic shows RF and CF acting as an RC filter to the input of the LM27402. The filter is used to attenuate voltage ripple that may exist on the input rail particularly during high output currents. The recommended values of RF and CF are 2.2Ω and 1 µF, respectively. There is a practical limit to the size of RF as it can cause a large voltage drop if large operating bias currents are present. The VIN pin of the LM27402 should not exceed 150 mV difference from the input voltage rail (VIN). The first equation to calculate for any buck converter is duty ratio: OUTPUT CAPACITOR SELECTION (COUT) The output capacitor, COUT, filters the inductor ripple current and provides a source of charge for transient load events. A wide range of output capacitors may be used with the LM27402 that provide excellent performance. The best performance is typically obtained using ceramic, tantalum, or electrolytic type chemistries. Typically, ceramic capacitors provide extremely low ESR to reduce the output ripple voltage and noise spikes, while tantalum and electrolytic capacitors provide a large bulk capacitance in a small size for transient loading events. When selecting the output capacitance value, the two performance characteristics to consider are the output voltage ripple and transient response. The output voltage ripple can be approximated by: Due to the resistive powertrain losses, the duty ratio will increase based on the overall efficiency, η. Calculation of η can be found in the POWER/EFFICIENCY CALCULATIONS section of this datasheet. INDUCTOR SELECTION (L) The inductor value is determined based on the operating frequency, load current, ripple current, and duty ratio. The selected inductor should have a saturation current rating greater than the peak current limit of the LM27402. To optimize the performance, the inductance is typically selected such that the ripple current, ΔIL, is between 20% and 40% of the rated output current. Figure 5 illustrates the switch voltage and inductor ripple current waveforms. Once the nominal input voltage, output voltage, operating frequency, and desired ripple current are known, the minimum inductance value can be calculated by: where ΔVOUT (V) is the amount of peak to peak voltage ripple at the power supply output, RESR (Ω) is the series resistance of the output capacitor, fSW (Hz) is the switching frequency, and COUT (F) is the output capacitance used in the design. The amount of output ripple that can be tolerated is application specific; however a general recommendation is to keep the output ripple less than 1% of the rated output voltage. Note that ceramic capacitors are sometimes preferred because they have very low ESR; however, depending on package and voltage rating of the capacitor, the value of capacitance can drop significantly with applied voltage and operating temperature. The output capacitor will affect the output voltage droop during a load transient. The peak output voltage deviation is dependent on many factors such as output capacitance, output capacitor ESR, inductor size, control loop bandwidth, powertrain parasitics, etc. Given sufficient control loop band- www.national.com 14 LM27402 width, a good approximation of the output voltage deviation is: UVLO voltage. This can be done with an external resistor divider from VIN to EN and EN to GND as shown in Figure 6. ΔVTR (V) is the transient output voltage deviation, ΔIOUT (A) is the load current step change and L (H) is the filter inductance. VL is the minimum inductor voltage which is duty ratio dependent. VL = VOUT , if D ≤ 0.5, VL = VIN - VOUT , if D > 0.5 For a desired ΔVTR (V), a minimum output capacitance can be found by: 30092612 FIGURE 6. Enable Sequencing The resistor values of RA and RB can be relatively sized to allow the EN pin to reach the enable threshold voltage (1.17V) at the appropriate input supply voltage. With the enable current source considered, the equation to solve for RA is: INPUT CAPACITOR SELECTION (CIN) Input capacitors are necessary to limit the input ripple voltage while supplying much of the switch current during the highside FET on-time. It is generally recommended to use ceramic capacitors at the input as they provide both a low impedance and a high RMS current rating. It is important to choose a stable dielectric for the ceramic capacitor such as X5R or X7R. A quality dielectric provides better temperature performance and also avoids the DC voltage derating inherent with Y5V capacitors. The input capacitor should be placed as close as possible to the drain of the high-side FET and the source of the low-side FET. Non-ceramic input capacitors should be selected for RMS current rating, minimum ripple voltage, and to provide damping. A good approximation for the required ripple current rating is given by the relationship: where RA is the resistor from VIN to EN, RB is the resistor from EN to GND, IEN is the internal enable pull-up current (2µA) and 1.17V is the fixed precision enable threshold voltage. Typical values for RB range from 10kΩ to 100kΩ. SETTING THE SOFT-START TIME Adding a soft-start capacitor can reduce inrush currents and provide a monotonic startup. The size of the soft-start capacitor can be calculated by: The highest requirement for RMS current rating occurs for D = 0.5. When D = 0.5, the RMS ripple current rating of the input capacitor should be greater than half the output current. Low ESR ceramic capacitors can be placed in parallel with higher valued bulk capacitors to provide optimized input filtering for the regulator. The input voltage ripple can be calculated using: The minimum amount of input capacitance as a function of desired input voltage ripple can be calculated using: The size of the CSS capacitor is influenced by the desired softstart time tss (s) , the soft-start current Iss (A) (3 µA) and the nominal feedback (FB) voltage level of 0.6V. If VVIN and VVDD are above the UVLO voltage level (2.90V) and EN is above the enable threshold (1.17V), the soft-start sequence will begin. The LM27402 defaults to a minimum startup time of 1.28 ms when no soft-start capacitor is connected. In other words, the LM27402 will not startup faster than 1.28 ms. The soft-start capacitor is discharged when enable is cycled, during UVLO, OTP, or when the LM27402 enters hiccup mode from an over-current event. There is a delay between EN transitioning above 1.17V and the beginning of the soft-start sequence. The delay allows the LM27402 to initialize its internal circuitry. Once the output has charged to 94% of the nominal output voltage and SS/TRACK has exceeded 564 mV, the PGOOD indicator will transition high as illustrated in Figure 7. USING PRECISION ENABLE If enable (EN) is not controlled directly, the LM27402 can be pre-programmed to turn on at an input voltage higher than the 15 www.national.com LM27402 30092643 FIGURE 7. Soft-Start Timing TRACKING The SS/TRACK pin also functions as a tracking pin when external power supply tracking is needed. Tracking is achieved by simply dividing down the external supply voltage with a simple resistor network shown in Figure 8. With the correct resistor divider configuration, the LM27402 can track an external voltage source to obtain a coincident or ratiometric startup behavior. FIGURE 9. Tracking Startup Sequences Similar to the soft-start function, the fastest possible startup time is 1.28 ms regardless of the rise time of the tracking voltage. When using the track feature, the final voltage seen by the SS/TRACK pin should exceed 0.8V to provide sufficient overdrive and transient immunity. SETTING THE SWITCHING FREQUENCY There are two options for setting the switching frequency of the LM27402. The frequency can be adjusted by an external resistor from FADJ to GND, or the user can synchronize the LM27402 to an external clock signal through SYNC. The LM27402 will only synchronize to frequencies above the frequency set by the RFADJ resistor. The clock signal must range from less than 0.8V to greater than 2.0V to ensure proper operation. If the clock signal ceases, the switching frequency will reduce to the frequency set by the FADJ resistor. The frequency range is 200 kHz to 1.2 MHz. The sync-in clock can synchronize a maximum of 400 kHz above the frequency set by the resistor. To find the value of resistance needed for a given frequency use the following equation: (fSW (kHz), RFADJ (kΩ)) 30092616 30092615 FIGURE 8. Tracking an External Power Supply Since the soft-start charging current ISS is sourced from the SS/TRACK pin, the size of R2 should be less than 10 kΩ to minimize errors in the tracking output. Once a value for R2 is selected, the value for R1 can be calculated using the appropriate equation in Figure 9 to give the desired startup sequence. Figure 9 shows two common startup sequences; the top waveform shows a coincidental startup while the bottom waveform illustrates a ratiometric startup. A coincidental configuration provides a robust startup sequence for certain applications since it avoids turning on any parasitic conduction paths that may exist between loads. A ratiometric configuration is preferred in applications where both supplies need to be at the final value at the same time. SETTING THE CURRENT LIMIT THRESHOLD The LM27402 exploits the filter inductor DCR (DC resistance) to detect over current events. If desired, the user can employ inductors with low tolerance DCR to increase the accuracy of the current limit threshold. The most common topology for sensing the DCR is shown in Figure 10. www.national.com 16 LM27402 30092619 FIGURE 10. DCR Sensing Circuit The most accurate sensing of voltage across the DCR is achieved by matching the time constant of the RSCS filter with the inductor L/RDCR time constant. If the time constants are matched, the voltage across the capacitor follows the voltage across the DCR. A typical range of capacitance used in the RSCS network is 100 nF to 1µF. The equation matching the time constants is: 30092681 FIGURE 12. Common Mode Voltage Resistor Divider Network Please refer to Application Note AN-2060 for design guidelines to adjust the common mode voltage of the current sense comparator. CONTROL LOOP COMPENSATION The LM27402 voltage mode control system incorporates input voltage feed-forward to eliminate the input voltage dependence of the PWM gain. Input voltage feed-forward allows the LM27402 to be stable throughout the entire input voltage range and makes it easier for the designer to select the compensation and power components. The following text will describe how to set the output voltage and obtain the open loop transfer function. During steady state operation, the DC output voltage is set by a feedback resistor network between VOUT, FB and GND. The FB voltage is nominally 0.6V ±1%. The equation describing the output voltage is: The current limit threshold can be adjusted to any level with a single resistor from the current limit comparator to the output voltage pin. Use the circuit in Figure 11 to set the current limit. 30092620 FIGURE 11. Setting the Current Limit Level Since the voltage across the inductor DCR follows the current through the inductor, the device will trip at the peak of the inductor current. Capacitor CSBY shown in Figure 11 filters the input to the current sense comparator. A working range for this capacitance is 47 pF to 100 pF. The equation to set the resistor value of RSET is: A good starting value for RFB1 is 20 kΩ. If an output voltage of 0.6V is required, RFB2 should not be used. There are three main blocks of a voltage mode buck switcher that the power supply designer must consider when designing the control system: the powertrain, PWM modulator, and the compensator. A diagram representing the control loop is shown in Figure 13. ILIMIT (A) is the desired current limit level, RDCR (Ω) is the rated DC resistance of the inductor and Ics- (A) is the 10 µA current source flowing out of the CS- pin. The internal current source ICS- is powered from the input voltage rail (VIN). The minimum voltage required to power the current source is 1V from VIN to VOUT. If a condition occurs where VIN - VOUT < 1V, the LM27402 may prematurely initiate hiccup mode. There are multiple options to avoid this situation. The first option is to enable the LM27402 after the input voltage has risen 1V above the nominal output voltage as seen in Figure 6. The second option is to lower the comparator common mode voltage shown in Figure 12 such that the ICScurrent source has enough headroom voltage. 17 www.national.com LM27402 The bode plot of the above transfer function can be seen in Figure 14. 30092623 FIGURE 13. Control Loop Schematic Diagram The powertrain consists of the filter inductor (L) with DCR (RDCR), output capacitor (COUT) with ESR (effective series resistance RESR), and effective load resistance (RO). The error amplifier (EA) regulates the feedback pin (FB) to 0.6V. The passive compensation components around the error amplifier help maintain system stability. Type III compensation is shown in Figure 13. The PWM modulator establishes the duty cycle command by comparing the error amplifier output (COMP) with an internally generated ramp set at the switching frequency. The modulator gain, powertrain and compensator transfer functions must be taken into consideration when obtaining the total open loop transfer function. The PWM modulator adds a DC gain to the open loop transfer function. In a basic voltage mode system, the PWM gain will vary with input voltage. However the LM27402 internal voltage feed-forward circuitry maintains a constant PWM gain of 7: 30092698 FIGURE 14. Powertrain Bode Plot The complex poles (fLC) created by the filter inductor and output capacitor cause a 180° phase shift as seen in Figure 14. The phase is boosted back up to -90° by virtue of the output capacitor ESR zero. The phase shift caused by the complex poles must be compensated to stabilize the loop response. The compensation network shown around the error amplifier in Figure 13 creates two poles, two zeros and a pole at the origin. Placing these poles and zeros at the correct frequencies will optimize the loop response. The compensator transfer function is: The powertrain transfer function includes the output inductor with DCR, output capacitor with ESR, and load resistance. The inductor and capacitor create two complex poles at a frequency described by: A left half plane zero is created by the output capacitor ESR located at a frequency described by: The pole located at the origin provides high DC gain to optimize DC load regulation performance. The other two poles and two zeros can be located accordingly to stabilize the voltage mode loop depending on the power stage complex poles and damping characteristic Q. Figure 15 is an illustration of what the error amplifier compensation transfer function will look like. The complete powertrain transfer function is: www.national.com 18 LM27402 After finding the compensation components it is wise to create a bode plot of the loop response using all three transfer functions. An illustration of the loop response is provided in Figure 16 . 30092640 FIGURE 15. Type lll Compensation Network Bode Plot Km is the mid-band gain of the compensator and can be estimated by: fC (Hz) is the desired crossover frequency and is usually selected between one tenth and one fifth of the switching frequency (f SW). The next set of equations show pole and zero locations expressed in terms of the components in the compensator feedback loop. 30092644 FIGURE 16. Loop Response It is important to always verify the stability by either observing the load transient response or by using a network analyzer. A phase margin between 45° and 70° is usually desired for voltage mode controlled systems. Excessive phase margin can cause slow system response to load transients and low phase margin may cause an oscillatory load transient response. If the load transient response peak deviation is larger than desired, increasing fC and recalculating the compensation components may help but usually at the expense of phase margin. MOSFET GATE DRIVE To drive large MOSFETs with high gate charge, the LM27402 includes low impedance high-side and low-side gate drivers. Low impedance gate drivers allow high current designs by enabling fast transition times and increased efficiency. The high-side gate drive is powered from a charge pump common to the switch-node and the low-side gate is powered by the VDD rail shown in Figure 17. Depending on Q, the complex double pole can cause an increase in gain at the LC resonant frequency and a precipitous drop in phase. To compensate for the phase drop, it is common practice to place both compensator zeros created by the type III compensation network at or slightly below the LC double pole frequency. The other two poles should be located beyond this point. One pole is located at the zero caused by the output capacitor ESR and the other pole is placed at half the switching frequency to roll off the higher frequency response. Conservative values for the compensation components can be found by using the following equations. 19 www.national.com LM27402 nent of a buck regulator, the following sections present equations detailing components with the highest relative power loss. MOSFETS Selecting the correct MOSFET for a design is important to the overall operation of the circuit. If inappropriate FETs are selected for the application, it can result in poor efficiency, high temperature issues, shoot-through and other impairments. It is important to calculate the power dissipation for each MOSFET at the maximum output current and make sure the maximum allowable power dissipation is not exceeded. MOSFET datasheets should also specify a junction-to-ambient thermal resistance (θJA) so the temperature rise can be estimated from this specification . Both high-side and low-side FETs contribute significant loss to the system relative to the other components. The high-side FET contributes transition switching losses, conduction losses and gate charge losses. The low-side FET also contributes conduction and gate charge losses, but the FET body diode voltage drop during deadtime and reverse recovery loss must also be considered. The transition losses for the low-side FET are small and usually ignored. High-Side MOSFET The next set of equations can be used to calculate the losses associated with the high-side FET. 30092624 FIGURE 17. VDD Charge Pump Circuit The circuit in Figure 17 will effectively supply close to the VDD voltage (4.5V) between the gate and the source of the highside MOSFET during the on time. It is recommended to use a Schottky diode for DBOOT with sufficient reverse standoff voltage and continuous current rating. The average current through this diode is dependent on the gate charge of the high-side FET and the frequency. It can be calculated using the following equation IDBOOT is the average current through the DBOOT diode, fSW (Hz) is the switching frequency and QGHS (C) is the gate charge of the high-side MOSFET. If the input voltage is below 5.5V, it is recommended to connect VDD to the input supply of the LM27402 through a 1Ω resistor shown in Figure 18. This will increase the gate voltage of both the low-side and high-side FETs. PCND_HS is the conduction loss of the high-side FET during the D cycle when current is flowing through the FET on-resistance. A self heating coefficient of 1.3 is included in this equation to approximate the effects of the RDS(ON) temperature coefficient. RDS(ON)_HS (Ω) is the drain to source resistance, IOUT (A) is the output current and D is the duty ratio. PSW_HS is the switching power loss during the high-side FET transition time. VIN (V) is the input voltage, fSW (Hz) is the switching frequency, and tr and tf (s) are the rise and fall times of the switch-node voltage respectively. PTOT_HS is the total power dissipation of the high-side FET. The gate charge of the high-side MOSFET can greatly affect the turn-on transition time and therefore efficiency. Furthermore, it is wise to consider the ratio of switching loss to conduction loss associated with the high-side FET. If the duty ratio is small and the input voltage is high, it may be beneficial to tradeoff QG for higher RDS(ON) to avoid high switching losses relative to conduction losses. If the duty ratio is large and the input voltage is low, then a lower RDS(ON) FET in tandem with a higher QG may result in less power dissipation. Low-Side MOSFET The next set of equations can be used to calculate the losses due to the low-side FET. 30092632 FIGURE 18. Tie VDD to VIN when VIN ≤ 5.5V POWER / EFFICIENCY CALCULATIONS The overall efficiency of a buck regulator is simply the ratio of output power to input power. Accurately predicting the overall efficiency can be tedious and depends on many variables. Although power losses can be found in almost every compowww.national.com 20 LM27402 PCND_LS is the conduction loss of the low-side FET during the 1-D cycle when current is flowing through the on-resistance of the FET. RDS(ON)_LS (Ω) is the drain to source resistance. PD is the deadtime power loss due to the body diode drop of the low-side FET. Tdeadtime (s) is the total deadtime. PRR is the reverse recovery charge power loss. QRR (C) is the total reverse recovery charge usually specified in the FET datasheet. PTOT_LS is the total power dissipation of the lowside FET. Gate Charge Loss A finite amount of gate charge is required in order to switch the high-side and low-side FETs. This gate charge is continuously charging the FETs during every switching cycle and appears as a constant current flowing into the controller from the input supply. The next equation describes the power loss due to the gate charge. The controller IQ power loss equation includes the IQ current (4 mA) and input voltage VIN (V). It is also important to calculate the power dissipated in the controller itself due to the gate charge current flowing from VIN to the output of the LDO (VDD). The gate charge current essentially passes through a resistance dropping the input voltage VIN to the LDO voltage (4.5V). This can cause the controller to operate at an elevated temperature since it must dissipate the power of the LDO pass device. The next equation calculates the power dissipated by the internal LDO of the controller. PLDO is the power dissipated in the LDO, QGHS (C) and QGLS are the high-side and low-side FET gate charges, respectively, and can be found in the FET datasheets. PQG is the total gate charge power loss, QGHS (C) and QGLS (C) are the high-side and low-side FET gate charges respectively, and can be found in the FET datasheets,VIN (V) is the input voltage, and fSW (Hz) is the switching frequency. Input and Output Capacitor ESR Losses Both the input and output capacitors are subject to steady state AC current and must be taken into consideration when calculating power losses. The next equation shown is the input capacitor ESR power loss. PCB LAYOUT CONSIDERATIONS After selecting the correct components, PCB layout is another crucial step in optimizing a buck regulator. The layout must be able to handle large DC and AC currents, minimize switchnode noise, and spread heat. The following layout guidelines and tips will help increase the chances of a successful design and should be taken seriously during the layout process. Input and Output Capacitor Layout A buck regulator is a switching converter with switched currents and voltages. The high di/dt and dv/dt nature of buck switching calls for careful layout of decoupling capacitors. The next figures shows the switching currents for the D and 1-D intervals of a buck regulator. Overall Efficiency After calculating the losses, the efficiency can then be calculated using: The input capacitor power loss equation includes the effective series resistance or RESR_IN (Ω) of the input capacitor. The power loss due to the ESR of the output capacitor is: The output capacitor power loss equation includes the peak to peak inductor current, ΔIL(A), and the effective series resistance or RESR (Ω) of the output capacitor. Inductor Losses The losses due to the inductor are caused primarily by the DCR. The next equation calculates the inductor DCR power loss. PDCR is the total power loss of the Inductor. A self heating coefficient of 1.2 is included in this equation to approximate the effects of the copper temperature coefficient approximately equal to 3900ppm/°C. RDCR (Ω) is the inductor DC resistance. Controller Losses The controller loss remains constant and contributes to a very small loss of power. The quiescent current is the main factor in terms of power loss attributed to the controller and it remains constant at 4 mA. The quiescent current power loss equation is: FIGURE 19. Power Flow 30092665 During the high-side FET on time, the AC component of the input current is supplied by the input capacitor. Due to the high di/dt nature of this current, it is essential that the input capacitor is closely coupled to the drain of the high-side FET to minimize any parasitic inductance. The output capacitor re- 21 www.national.com LM27402 turn and input capacitor return should also be closely coupled to minimize parasitic ground inductance. During the low-side FET on time, current flows from ground through the low-side FET and to the output capacitor through the inductor. It is essential the input capacitor is also closely coupled with the lowside FET source. MOSFET Layout With FETs acting as switches in a switching regulator, good layout is essential. Current is constantly transitioning from the high-side FET to the low-side FET so it is essential to place the source of the high-side FET next to the drain of the lowside FET and the switch-node side of the inductor. This will minimize any parasitic inductance between the switch-node and the FETs which can cause switch-node ringing. The FETs can become very hot due to internal power dissipation. Using vias to connect the drain of the FETs to other layers may help spread the heat. The switch-node copper area should not be so small that the low-side FET will not be able to spread its heat. As seen in the POWER / EFFICIENCY CALCULATIONS section, the rise times of the FETs can significantly affect the efficiency. Therefore, it is good layout practice to maintain the shortest path from the LG/HG gate pins to the pins of the lowside/high-side FETs to minimize the parasitic inductance. The high-side gate trace should be coupled with the switch-node trace since the internal high-side gate drive is connect between CBOOT and SW. The low-side FET gate trace should be coupled with ground return since the internal low-side gate driver is powered between VDD and ground. A good trace width is around 0.015 inches to support the high transient currents. During switching transition, it is common to see peak transient currents of 1 - 2A flowing through gate traces so minimizing the parasitic inductance is crucial to fast and efficient switching. Noise Because of the high energy switching characteristic of the switching regulator, it is good practice to separate noise generating circuitry from noise sensitive circuitry. For a buck regulator, this means separating the switch-node from the feedback circuitry. This can be achieved by distance or can be shielded on the back side of the board through an internal copper ground plane. Reducing the noise in the DCR sense circuitry is imperative to realize accurate effective over-current response. Separation of this circuitry from the switch-node and gate drivers will reduce the amount of switching noise pickup at the input of the current limit comparator. Running the DCR sense traces in parallel as a differential pair can significantly reduce the effect of any system noise (including switch-node pickup) at the input of the current limit comparator. The SW pin of the LM27402 receives signals directly from the switch-node of the regulator to collect switching information. This is an unimpeded noise path that may cause erratic switching behavior if excessive noise is injected from the switch-node. If needed, a snubber can be used to limit the dv/ dt of the signal effectively reducing the noise into the switchnode sense pin. Controller Layout Proper layout practices of the controller can help guarantee proper operation.Locating the input decoupling capacitor (CF), as close as possible to the VDD capacitor (CVDD) with the LM27402 GND will help increase noise immunity. www.national.com 22 LM27402 EXAMPLE CIRCUIT 1 30092676 FIGURE 20. 5V - 12V VIN to 1.5V VOUT, 20A IOUT, fsw = 300 kHz Bill of Materials Designator U1 CBOOT CC1 CC2 CC3 CVDD CF CIN COUT CS CSS CSBY DBOOT Type Synchronous Buck Controller Capacitor Capacitor Capacitor Capacitor Capacitor Capacitor Capacitor Capacitor Capacitor Capacitor Capacitor Diode 0.22 µF, Ceramic, X7R, 25V, 10% Parameters Part Number LM27402 GRM188R71E224KA88D Qty 1 1 1 1 1 1 1 5 4 1 1 1 1 Manufacturer National Semiconductor Murata Murata Murata Murata Murata Murata Murata Kemet Murata Murata Murata Central Semi 3900 pF, Ceramic, X7R, GRM188R71H392KA01D 50V, 10% 150 pF, Ceramic, C0G, 50V, 5% 820 pF, Ceramic, C0G, 50V, 5% 1 µF, Ceramic, X5R, 25V, 10% 1 µF, Ceramic, X5R, 25V, 10% 22 µF, Ceramic, X5R, 25V, 10% 100 µF, Ceramic, X5R, 6.3V, 20% 0.22 µF, Ceramic, X7R, 25V, 10% 47000 pF, Ceramic, X7R, 16V, 10% 100 pF, Ceramic, C0G, 50V, 5% Schottky Diode, Average I = 100 mA, Max Surge I = 750 mA Schottky Diode, Average I = 3A, Max Surge I = 80A .68 µH, 2.34 mΩ GRM1885C1H151JA01D GRM1885C1H821JA01D GRM188R61E105KA12D GRM188R61E105KA12D GRM32ER61E226KE15L C1210C107M9PACTU GRM188R71E224KA88D GRM188R71C473KA01D GRM1885C1H101JA01D CMOSH-3 DSW Diode CMSH3-40M 1 Central Semi LOUT Inductor IHLP5050CEERR68M06 1 Vishay 23 www.national.com LM27402 Designator QL QH RC1 RC2 RFADJ RFB1 RFB2 RF RPGD RS RSET Type N-CH MOSFET N-CH MOSFET Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Parameters 30V, 60A, 43.5 nC, RDS (ON) @ 4.5V = 1.85 mΩ Part Number Si7192DP SiR436DP CRCW06038k06FKEA CRCW0603261RFKEA CRCW060345K3FKEA CRCW060320K0FKEA CRCW060320K0FKEA CRCW06032R20JNEA CRCW060351K1JNEA CRCW06031K30FKEA CRCW06036K34FKEA Qty 1 1 1 1 1 1 1 1 1 1 1 Manufacturer Vishay Vishay Vishay Vishay Vishay Vishay Vishay Vishay Vishay Vishay Vishay 25V, 40A, 13 nC, RDS (ON) @ 4.5V = 6.2 mΩ 8.06 kΩ, 1%, 0.1W 261Ω, 1%, 0.1W 45.3 kΩ, 1%, 0.1W 20.0 kΩ, 1%, 0.1W 20.0 kΩ, 1%, 0.1W 2.2Ω, 5%, 0.1W 51.1 kΩ, 5%, 0.1W 1.3 kΩ, 1%, 0.1W 6.34 kΩ, 1%, 0.1W www.national.com 24 LM27402 EXAMPLE CIRCUIT 2 30092695 FIGURE 21. 5V - 12V VIN to 3.3V VOUT, 25A IOUT , fsw = 300 kHz Bill Of Materials Designator U1 CBOOT CC1 CC2 CC3 CVDD CF CIN COUT 1 COUT2 CS CSS CSBY DBOOT Type Synchronous Buck Controller Capacitor Capacitor Capacitor Capacitor Capacitor Capacitor Capacitor Capacitor Capacitor Capacitor Capacitor Capacitor Diode 0.22 µF, Ceramic, X7R, 25V, 10% 1200 pF, Ceramic, COG, 50V, 5% 56 pF, Ceramic, COG, 50V, 5% 820 pF, Ceramic, COG, 50V, 5% 1 µF, Ceramic, X5R, 25V, 10% 1 µF, Ceramic, X5R, 25V, 10% 22 µF, Ceramic, X5R, 25V, 10% 100 µF, Ceramic, X5R, 6.3V, 20% 330 µF, POSCAP, 6.3V, 20% 0.22 µF, Ceramic, X7R, 25V, 10% 47000 pF, Ceramic, X7R, 16V, 10% 100 pF, Ceramic, C0G, 50V, 5% Schottky Diode, Average I = 100 mA, Max Surge I = 750 mA Parameters Part Number LM27402 GRM188R71E224KA88D GRM1885C1H122JA01D GRM1885C1H560JA01D GRM1885C1H821JA01D GRM188R61E105KA12D GRM188R61E105KA12D GRM32ER61E226KE15L C1210C107M9PACTU 6TPE1330MIL GRM188R71E224KA88D GRM188R71E473KA01D GRM1885C1H101JA01D CMOSH-3 Qty 1 1 1 1 1 1 1 5 1 1 1 1 1 1 Manufacturer National Semiconductor Murata Murata Murata Murata Murata Murata Murata Kemet Sanyo Murata Murata Murata Central Semi 25 www.national.com LM27402 Designator DSW Type Diode Parameters Schottky Diode, Average I = 3A, Max Surge I = 80A 1 µH, 0.9 mΩ 30V, 60A, 43.5 nC, RDS (ON) Part Number CMSH3-40M Qty 1 Manufacturer Central Semi LOUT QL QH(1,2) RC1 RC2 RFADJ RFB1 RFB2 RF RPGD RS RSET Inductor N-CH MOSFET N-CH MOSFET Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor SER2010-102ML Si7192DP SiR892DP CRCW060318K7FKEA CRCW06034K75FKEA CRCW060345K3FKEA CRCW060320K0FKEA CRCW06034K42FKEA CRCW06032R20JNEA CRCW060351K1JNEA CRCW06034K12FKEA CRCW06034K53FKEA 1 1 1 1 1 1 1 1 1 1 1 1 Coilcraft Vishay Vishay Vishay Vishay Vishay Vishay Vishay Vishay Vishay Vishay Vishay @ 4.5V = 1.85 mΩ 25V, 50A, 20 nC, RDS (ON) @ 4.5V = 3.4 mΩ 18.7 kΩ, 1%, 0.1W 4.75 kΩ, 1%, 0.1W 45.3 kΩ, 1%, 0.1W 20.0 kΩ, 1%, 0.1W 4.42 kΩ, 1%, 0.1W 2.2Ω, 5%, 0.1W 51.1 kΩ, 5%, 0.1W 4.12 kΩ, 1%, 0.1W 4.53 kΩ, 1%, 0.1W www.national.com 26 LM27402 EXAMPLE CIRCUIT 3 30092696 FIGURE 22. 3.3V VIN to 0.9V VOUT, 20A IOUT , fsw = 500 kHz Bill Of Materials Designator U1 CBOOT CC1 CC2 CC3 CVDD CF CIN COUT CS CSS CSBY DBOOT Type Synchronous Buck Controller Capacitor Capacitor Capacitor Capacitor Capacitor Capacitor Capacitor Capacitor Capacitor Capacitor Capacitor Diode 0.22 µF, Ceramic, X7R, 25V, 10% 820 pF, Ceramic, COG, 50V, 5% 68 pF, Ceramic, COG, 50V, 5% 390 pF, Ceramic, COG, 50V, 5% 1 µF, Ceramic, X5R, 25V, 10% 1 µF, Ceramic, X5R, 25V, 10% 22 µF, Ceramic, X5R, 25V, 10% 100 µF, Ceramic, X5R, 6.3V, 20% 0.22 µF, Ceramic, X7R, 25V, 10% 22000 pF, Ceramic, X7R, 16V, 10% 68 pF, Ceramic, C0G, 50V, 5% Schottky Diode, Average I = 100 mA, Max Surge I = 750 mA Schottky Diode, Average I = 3A, Max Surge I = 80A 0.33 µH, 1.4 mΩ 27 Parameters Part Number LM27402 GRM188R71E224KA88D GRM1885C1H821JA01D GRM1885C1H680JA01D GRM1885C1H391JA01D GRM188R61E105KA12D GRM188R61E105KA12D C2012X5R0J226M JMK316BJ107ML GRM188R71E224KA88D GRM188R71E223KA01D GRM1885C1H680JA01D CMOSH-3 Qty 1 1 1 1 1 1 1 5 3 1 1 1 1 Manufacturer National Semiconductor Murata Murata Murata Murata Murata Murata TDK Taiyo Yuden Murata Murata Murata Central Semi DSW Diode CMSH3-40M 1 Central Semi LOUT Inductor RL-8250-1.4-R33M 1 Renco www.national.com LM27402 Designator QL QH RC1 RC2 RDD RFADJ RFB1 RFB2 RF RPGD RS RSET Type N-CH MOSFET N-CH MOSFET Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Parameters 20V, 100A, 64 nC, RDS (ON) @ 4.5V = 1.6 mΩ Part Number BSC019N02KS BSC026N02KS CRCW060310K0FKEA CRCW0603150RFKEA CRCW06031R00JNEA CRCW060320K0FKEA CRCW060320K0FKEA CRCW060340K2FKEA CRCW06032R20JNEA CRCW060351K1JNEA CRCW06031K07FKEA CRCW06035K11FKEA Qty 1 1 1 1 1 1 1 1 1 1 1 1 Manufacturer Infineon Infineon Vishay Vishay Vishay Vishay Vishay Vishay Vishay Vishay Vishay Vishay 20V, 100A, 40 nC, RDS (ON) @ 4.5V = 2.1 mΩ 10.0 kΩ, 1%, 0.1W 150Ω, 1%, 0.1W 1Ω, 5%, 0.1W 20.0 kΩ, 1%, 0.1W 20.0 kΩ, 1%, 0.1W 40.2 kΩ, 1%, 0.1W 2.2Ω, 5%, 0.1W 51.1 kΩ, 5%, 0.1W 1.07 kΩ, 1%, 0.1W 5.11 kΩ, 1%, 0.1W www.national.com 28 LM27402 Physical Dimensions inches (millimeters) unless otherwise noted 16-Lead eTSSOP Package NS Package Number MXA16A 29 www.national.com LM27402 16-Lead exposed LLP NS Package Number SQB16A www.national.com 30 LM27402 Notes 31 www.national.com LM27402 High Performance Synchronous Buck Controller with DCR Current Sensing Notes For more National Semiconductor product information and proven design tools, visit the following Web sites at: www.national.com Products Amplifiers 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