LM3676

LM3676 2MHz, 600mA Step-Down DC-DC Converter with Mode Control December 2006 LM3676 2MHz, 600mA Step-Down DC-DC Converter with Mode Control General Description The LM3676 step-down DC-DC converter is optimized for powering low voltage circuits from a single Li-Ion cell battery and input voltage rails from 2.9V to 5.5V. It provides up to 600mA load current, over the entire input voltage range. There are several different fixed voltage output options available as well as an adjustable output voltage version. The LM3676 has a mode-control pin that allows the user to select continuous Forced PWM mode over the complete load range or an intelligent PFM-PWM mode that changes modes depending on the load. PWM mode offers superior efficiency under high load conditions (>100mA) and the lowest output noise performance. In Auto mode, PFM-PWM, hysteretic PFM extends the battery life through reduction of the quiescent current to 16µA (typ.) during light loads and system standby. The LM3676 is available in a 8-lead non-pullback LLP package in leaded (PB) and lead-free (NO PB) versions. A high switching frequency of 2 MHz (typ) allows use of tiny surfacemount components, an inductor and two ceramic capacitors. Features ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ 16 µA typical quiescent current 600 mA maximum load capability 2 MHz PWM fixed switching frequency (typ) Automatic PFM/PWM mode switching or Forced PWM mode Available in fixed output voltages and adjustable version 8-Lead non-pullback LLP package Internal synchronous rectification for high efficiency Internal soft start 0.01 µA typical shutdown current Operates from a single Li-Ion cell battery Only three tiny surface-mount external components required (one inductor, two ceramic capacitors) Current overload and Thermal shutdown protection Applications ■ ■ ■ ■ ■ ■ ■ Mobile phones PDAs MP3 players W-LAN Portable instruments Digital still cameras Portable Hard disk drives Typical Application Circuits 20176401 FIGURE 1. Typical Application Circuit © 2007 National Semiconductor Corporation 201764 www.national.com LM3676 20176431 FIGURE 2. Typical Application Circuit for ADJ version Connection Diagram and Package Mark Information 20176402 FIGURE 3. LLP8 Package NS Package Number SDA08A Pin Descriptions (8-Lead LLP) Pin # 1 2 3 4 Name PGND SW MODE FB Description Power Ground Pin. Switching node connection to the internal PFET switch and NFET synchronous rectifier. Mode Control Pin: > 1.0V selects continous PWM mode ; 80 mA or when the Mode pin is set high. When the mode pin is set low, Auto mode, lighter load current causes the device to automatically switch into PFM for reduced current consumption (IQ = 16 µA typ) and prolong battery life . Shutdown mode turns off the device, offering the lowest current consumption (ISHUTDOWN = 0.01 µA typ). Additional features include soft-start, under voltage protection, current overload protection, and thermal shutdown protection. As shown in Figure 1, only three external power components are required for implementation. The part uses an internal reference voltage of 0.5V. It is recommended to keep the part in shutdown until the input voltage is 2.9V or higher. CIRCUIT OPERATION During the first portion of each switching cycle, the control block in the LM3676 turns on the internal PFET switch. This allows current to flow from the input through the inductor to the output filter capacitor and load. The inductor limits the current to a ramp with a slope of (VIN–VOUT)/L, by storing energy in a magnetic field. During the second portion of each cycle, the controller turns the PFET switch off, blocking current flow from the input, and then turns the NFET synchronous rectifier on. The inductor draws current from ground through the NFET to the output filter capacitor and load, which ramps the inductor current down with a slope of - VOUT/L. The output filter stores charge when the inductor current is high, and releases it when inductor current is low, smoothing the voltage across the load. The output voltage is regulated by modulating the PFET switch on time to control the average current sent to the load. The effect is identical to sending a duty-cycle modulated rectangular wave formed by the switch and synchronous rectifier at the SW pin to a low-pass filter formed by the inductor and output filter capacitor. The output voltage is equal to the average voltage at the SW pin. MODE PIN Setting the Mode pin low (1.0V) places the part in Forced PWM. The part is in forced PWM regardless of the load. Do not leave the Mode pin floating. PWM OPERATION During PWM operation the converter operates as a voltagemode controller with input voltage feed forward. This allows the converter to achieve good load and line regulation. The DC gain of the power stage is proportional to the input voltage. 11 To eliminate this dependence, feed forward inversely proportional to the input voltage is introduced. While in PWM mode, the output voltage is regulated by switching at a constant frequency and then modulating the energy per cycle to control power to the load. At the beginning of each clock cycle the PFET switch is turned on and the inductor current ramps up until the comparator trips and the control logic turns off the switch. The current limit comparator can also turn off the switch in case the current limit of the PFET is exceeded. Then the NFET switch is turned on and the inductor current ramps down. The next cycle is initiated by the clock turning off the NFET and turning on the PFET. 20176423 FIGURE 5. Typical PWM Operation Internal Synchronous Rectification While in PWM mode, the LM3676 uses an internal NFET as a synchronous rectifier to reduce rectifier forward voltage drop and associated power loss. Synchronous rectification provides a significant improvement in efficiency whenever the output voltage is relatively low compared to the voltage drop across an ordinary rectifier diode. Current Limiting A current limit feature allows the LM3676 to protect itself and external components during overload conditions. PWM mode implements current limiting using an internal comparator that trips at 1020 mA (typ). If the output is shorted to ground the device enters a timed current limit mode where the NFET is turned on for a longer duration until the inductor current falls below a low threshold. This allows the inductor current more time to decay, thereby preventing runaway. PFM OPERATION At very light load, the converter enters PFM mode and operates with reduced switching frequency and supply current to maintain high efficiency. The part automatically transitions into PFM mode when either of two conditions occurs for a duration of 32 or more clock cycles: A. The NFET current reaches zero. B. The peak PMOS switch current drops below the IMODE level, (Typically IMODE < 30mA + VIN/42 Ω ). www.national.com LM3676 20176422 FIGURE 6. Typical PFM Operation During PFM operation, the converter positions the output voltage slightly higher than the nominal output voltage during PWM operation, allowing additional headroom for voltage drop during a load transient from light to heavy load. The PFM comparators sense the output voltage via the feedback pin and control the switching of the output FETs such that the output voltage ramps between ~0.6% and ~1.7% above the nominal PWM output voltage. If the output voltage is below the ‘high’ PFM comparator threshold, the PMOS power switch is turned on. It remains on until the output voltage reaches the ‘high’ PFM threshold or the peak current exceeds the IPFM level set for PFM mode. The typical peak current in PFM mode is: IPFM = 112mA + VIN/27Ω . Once the PMOS power switch is turned off, the NMOS power switch is turned on until the inductor current ramps to zero. When the NMOS zero-current condition is detected, the NMOS power switch is turned off. If the output voltage is below the ‘high’ PFM comparator threshold (see Figure 8), the PMOS switch is again turned on and the cycle is repeated until the output reaches the desired level. Once the output reaches the ‘high’ PFM threshold, the NMOS switch is turned on briefly to ramp the inductor current to zero and then both output switches are turned off and the part enters an extremely low power mode. Quiescent supply current during this ‘sleep’ mode is 16µA (typ), which allows the part to achieve high efficiency under extremely light load conditions. If the load current should increase during PFM mode (see Figure 8) causing the output voltage to fall below the ‘low2’ PFM threshold, the part will automatically transition into fixedfrequency PWM mode. When VIN =2.9V the part transitions from PWM to PFM mode at ~35mA output current and from PFM to PWM mode at ~85mA , when VIN=3.6V, PWM to PFM transition happens at ~50mA and PFM to PWM transition happens at ~100mA, when VIN =4.5V, PWM to PFM transition happens at ~65mA and PFM to PWM transition happens at ~115mA. 20176403 FIGURE 7. Operation in PFM Mode and Transfer to PWM Mode www.national.com 12 LM3676 SHUTDOWN MODE Setting the EN input pin low (1.0V) enables normal operation. It is recommended to set EN pin low to turn off the LM3676 during system power up and undervoltage conditions when the supply is less than 2.9V. Do not leave the EN pin floating. SOFT START The LM3676 has a soft-start circuit that limits in-rush current during start-up. During start-up the switch current limit is increased in steps. Soft start is activated only if EN goes from logic low to logic high after Vin reaches 2.9V. Soft start is implemented by increasing switch current limit in steps of 70mA, 140mA, 280mA and 1020mA (typical switch current limit). The start-up time thereby depends on the output capacitor and load current demanded at start-up. Typical start-up times with a 10µF output capacitor and 300mA load is 400µs and with 1mA load is 275µs. LDO - LOW DROP OUT OPERATION The LM3676-ADJ can operate at 100% duty cycle (no switching; PMOS switch completely on) for low drop out support of the output voltage. In this way the output voltage will be controlled down to the lowest possible input voltage. When the device operates near 100% duty cycle, output voltage ripple is approximately 25 mV. The minimum input voltage needed to support the output voltage is VIN, MIN = ILOAD * (RDSON, PFET + RINDUCTOR) + VOUT • ILOAD • RDSON, PFET • RINDUCTOR Load current Drain to source resistance of PFET switch in the triode region Inductor resistance below the 16 µA quiescent current level (PFM mode) but large enough that it is not susceptible to noise. If R2 is 200 kΩ, and VFB is 0.5V, the current through the resistor feedback network will be 2.5 µA. The output voltage of the adjustable parts ranges from 1.1V to 3.3V. The formula for output voltage selection is: • VOUT: output voltage (volts) • VFB : feedback voltage = 0.5V • R1: feedback resistor from VOUT to FB • R2: feedback resistor from FB to GND For any output voltage greater than or equal to 1.1V, a zero must be added around 45 kHz for stability. The formula for calculation of C1 is: For output voltages higher than 2.5V, a pole must be placed at 45 kHz as well. If the pole and zero are at the same frequency the formula for calculation of C2 is: The formula for location of zero and pole frequency created by adding C1 and C2 is given below. By adding C1, a zero as well as a higher frequency pole is introduced. Application Information OUTPUT VOLTAGE SELECTION FOR LM3676-ADJ The output voltage of the adjustable parts can be programmed through the resistor network connected from VOUT to FB, then to GND. VOUT is adjusted to make the voltage at FB equal to 0.5V. The resistor from FB to GND (R2) should be 200 kΩ to keep the current drawn through this network well See the "LM3676-ADJ configurations for various VOUT" table. LM3676-ADJ Configurations For Various VOUT (Circuit of Figure 2) VOUT(V) 1.1 1.2 1.3 1.5 1.6 1.7 1.8 1.875 2.5 2.8 3.3 R1(kΩ) 240 280 320 357 442 432 464 523 402 464 562 R2 (kΩ) 200 200 200 178 200 178 178 191 100 100 100 C1 (pF) 15 12 12 10 8.2 8.2 8.2 6.8 8.2 8.2 6.8 C2 (pF) none none none none none none none none none 33 33 L (µH) 2.2 2.2 2.2 2.2 2.2 2.2 2.2 2.2 2.2 2.2 2.2 CIN (µF) 4.7 4.7 4.7 4.7 4.7 4.7 4.7 4.7 4.7 4.7 4.7 COUT(µF) 10 10 10 10 10 10 10 10 10 10 10 13 www.national.com LM3676 INDUCTOR SELECTION There are two main considerations when choosing an inductor; the inductor should not saturate, and the inductor current ripple should be small enough to achieve the desired output voltage ripple. Different saturation current rating specifications are followed by different manufacturers so attention must be given to details. Saturation current ratings are typically specified at 25°C. However, ratings at the maximum ambient temperature of application should be requested from the manufacturer. The minimum value of inductance to guarantee good performance is 1.76µH at ILIM (typ) dc current over the ambient temperature range. Shielded inductors radiate less noise and should be preferred. There are two methods to choose the inductor saturation current rating. Method 1: The saturation current should be greater than the sum of the maximum load current and the worst case average to peak inductor current. This can be written as A 2.2 µH inductor with a saturation current rating of at least 1200 mA is recommended for most applications.The inductor’s resistance should be less than 0.3Ω for good efficiency. Table one lists suggested inductors and suppliers. For low-cost applications, an unshielded bobbin inductor could be considered. For noise critical applications, a toroidal or shielded-bobbin inductor should be used. A good practice is to lay out the board with overlapping footprints of both types for design flexibility. This allows substitution of a low-noise shielded inductor, in the event that noise from low-cost bobbin models is unacceptable. INPUT CAPACITOR SELECTION A ceramic input capacitor of 4.7 µF, 6.3V is sufficient for most applications. Place the input capacitor as close as possible to the VIN pin of the device. A larger value may be used for improved input voltage filtering. Use X7R or X5R types; do not use Y5V. DC bias characteristics of ceramic capacitors must be considered when selecting case sizes like 0805 and 0603. The minimum input capacitance to guarantee good performance is 2.2µF at 3V dc bias; 1.5µF at 5V dc bias including tolerances and over ambient temperature range. The input filter capacitor supplies current to the PFET switch of the LM3676 in the first half of each cycle and reduces voltage ripple imposed on the input power source. A ceramic capacitor’s low ESR provides the best noise filtering of the input voltage spikes due to this rapidly changing current. Select a capacitor with sufficient ripple current rating. The input current ripple can be calculated as: • • • • IRIPPLE: average to peak inductor current IOUTMAX: maximum load current (600mA) VIN: maximum input voltage in application L : min inductor value including worst case tolerances (30% drop can be considered for method 1) • f : minimum switching frequency (1.6Mhz) • VOUT: output voltage Method 2: A more conservative and recommended approach is to choose an inductor that has a saturation current rating greater than the maximum current limit of 1200mA. www.national.com 14 LM3676 TABLE 1. Suggested Inductors and Their Suppliers Model DO3314-222MX LPO3310-222MX ELL5GM2R2N CDRH2D14-2R2 Vendor Coilcraft Coilcraft Panasonic Sumida Dimensions LxWxH(mm) 3.3 x 3.3 x 1.4 3.3 x 3.3 x 1.0 5.2 x 5.2 x 1.5 3.2 x 3.2 x 1.55 D.C.R (max) 200 mΩ 150 mΩ 53 mΩ 94 mΩ OUTPUT CAPACITOR SELECTION A ceramic output capacitor of 10 µF, 6.3V is sufficient for most applications. Use X7R or X5R types; do not use Y5V. DC bias characteristics of ceramic capacitors must be considered when selecting case sizes like 0805 and 0603. DC bias characteristics vary from manufacturer to manufacturer and dc bias curves should be requested from them as part of the capacitor selection process. The minimum output capacitance to guarantee good performance is 5.75µF at 1.8V dc bias including tolerances and over ambient temperature range. The output filter capacitor smoothes out current flow from the inductor to the load, helps maintain a steady output voltage during transient load changes and reduces output voltage ripple. These capacitors must be selected with sufficient capacitance and sufficiently low ESR to perform these functions. The output voltage ripple is caused by the charging and discharging of the output capacitor and by the RESR and can be calculated as: Voltage peak-to-peak ripple due to capacitance can be expressed as follow: Voltage peak-to-peak ripple due to ESR can be expressed as follow: VPP-ESR = (2 * IRIPPLE) * RESR Because these two components are out of phase the rms (root mean squared) value can be used to get an approximate value of peak-to-peak ripple. The peak-to-peak ripple voltage, rms value can be expressed as follow: Note that the output voltage ripple is dependent on the inductor current ripple and the equivalent series resistance of the output capacitor (RESR). The RESR is frequency dependent (as well as temperature dependent); make sure the value used for calculations is at the switching frequency of the part. TABLE 2. Suggested Capacitors and Their Suppliers Model 4.7 µF for CIN C2012X5R0J475K JMK212BJ475K GRM21BR60J475K C1608X5R0J475K 10 µF for COUT GRM21BR60J106K JMK212BJ106K C2012X5R0J106K C1608X5R0J106K Ceramic, X5R Ceramic, X5R Ceramic, X5R Ceramic, X5R Murata Taiyo-Yuden TDK TDK 6.3V 6.3V 6.3V 6.3V 0805 (2012) 0805 (2012) 0805 (2012) 0603 (1608) Ceramic, X5R Ceramic, X5R Ceramic, X5R Ceramic, X5R TDK Taiyo-Yuden Murata TDK 6.3V 6.3V 6.3V 6.3V 0805 (2012) 0805 (2012) 0805 (2012) 0603 (1608) Type Vendor Voltage Rating Case Size Inch (mm) 15 www.national.com LM3676 BOARD LAYOUT CONSIDERATIONS PC board layout is an important part of DC-DC converter design. Poor board layout can disrupt the performance of a DCDC converter and surrounding circuitry by contributing to EMI, ground bounce, and resistive voltage loss in the traces. These can send erroneous signals to the DC-DC converter IC, resulting in poor regulation or instability. Good layout for the LM3676 can be implemented by following a few simple design rules below. Refer to Figure 8 for top layer board layout. 1. Place the LM3676, inductor and filter capacitors close together and make the traces short. The traces between these components carry relatively high switching currents and act as antennas. Following this rule reduces radiated noise. Special care must be given to place the input filter capacitor very close to the VIN and GND pin. 2. Arrange the components so that the switching current loops curl in the same direction. During the first half of each cycle, current flows from the input filter capacitor through the LM3676 and inductor to the output filter capacitor and back through ground, forming a current loop. In the second half of each cycle, current is pulled up from ground through the LM3676 by the inductor to the output filter capacitor and then back through ground forming a second current loop. Routing these loops so the current curls in the same direction prevents magnetic field reversal between the two half-cycles and reduces radiated noise. 3. Connect the ground pins of the LM3676 and filter capacitors together using generous component-side copper fill as a pseudo-ground plane. Then, connect this to the ground-plane (if one is used) with several vias. This reduces ground-plane noise by preventing the switching currents from circulating through the ground plane. It also reduces ground bounce at the LM3676 by giving it a lowimpedance ground connection. Connect SGND to PGND at one single point within the board layout. 4. Use wide traces between the power components and for power connections to the DC-DC converter circuit. This reduces voltage errors caused by resistive losses across the traces. 5. Route noise sensitive traces, such as the voltage feedback path, away from noisy traces between the power components. The voltage feedback trace must remain close to the LM3676 circuit and should be direct but should be routed opposite to noisy components. This reduces EMI radiated onto the DC-DC converter’s own voltage feedback trace. A good approach is to route the feedback trace on another layer and to have a ground plane between the top layer and layer on which the feedback trace is routed. In the same manner for the adjustable part it is desired to have the feedback dividers on the bottom layer. 6. Place noise sensitive circuitry, such as radio IF blocks, away from the DC-DC converter, CMOS digital blocks and other noisy circuitry. Interference with noisesensitive circuitry in the system can be reduced through distance. In mobile phones, for example, a common practice is to place the DC-DC converter on one corner of the board, arrange the CMOS digital circuitry around it (since this also generates noise), and then place sensitive preamplifiers and IF stages on the diagonally opposing corner. Often, the sensitive circuitry is shielded with a metal pan and power to it is postregulated to reduce conducted noise, using low-dropout linear regulators. www.national.com 16 LM3676 20176464 FIGURE 8. Top layer of board layout for LLP 17 www.national.com LM3676 Physical Dimensions inches (millimeters) unless otherwise noted 8-Lead LLP Package NS Package Number SDA08A www.national.com 18 LM3676 Notes 19 www.national.com LM3676 2MHz, 600mA Step-Down DC-DC Converter with Mode Control Notes THE CONTENTS OF THIS DOCUMENT ARE PROVIDED IN CONNECTION WITH NATIONAL SEMICONDUCTOR CORPORATION (“NATIONAL”) PRODUCTS. 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