LM4548

LM4548 AC ’97 Rev 2 Codec with Sample Rate Conversion and National 3D Sound February 1999 LM4548 AC ’97 Rev 2 Codec with Sample Rate Conversion and National 3D Sound General Description The LM4548 is an audio codec for PC systems which is fully PC98 compliant and performs the analog intensive functions of the AC97 Rev2 architecture. Using 18-bit Sigma-Delta A/D’s and D/A’s, the LM4548 provides 90dB of Dynamic Range. The LM4548 was designed specifically to provide a high quality audio path and provide all analog functionality in a PC audio system. It features full duplex stereo A/D’s and D/A’s and an analog mixer with 4 stereo and 3 mono inputs, each of which has separate gain, attenuation and mute control. The LM4548 also provides the additional True Line-Level output and National’s 3D Sound stereo enhancement. The LM4548 supports variable sample rate conversion as defined in the AC97 Rev2 specification. The sample rate for the A/D and D/A can be programmed separately to convert any rate between 4kHz - 48kHz with a resolution of 1Hz. The AC97 architecture separates the analog and digital functions of the PC audio system allowing both for system design flexibility and increased performance. Key Specifications n Analog Mixer Dynamic Range n D/A Dynamic Range n A/D Dynamic Range 97dB (typ) 89dB (typ) 90dB (typ) Features n AC’97 Rev2 compliant n National’s 3D Sound circuitry n High quality Sample Rate Conversion (SRC) from 4kHz to 48kHz in 1Hz increments. n Multiple Codec Support n True Line Level Output with volume control in addition to standard Line Out n Advanced power management support n Digital 3V and 5V compliant Applications n Desktop PC Audio Systems n Portable PC Systems n Mobile PC Systems Block Diagram DS100987-1 FIGURE 1. LM4548 Block Diagram © 1999 National Semiconductor Corporation DS100987 www.national.com Absolute Maximum Ratings (Note 3) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage Storage Temperature Input Voltage ESD Susceptibility (Note 5) pins 27, 28 pin 3 ESD Susceptibility (Note 6) pin 3 Junction Temperature 6.0V −40˚C to +150˚C −0.3V to VDD +0.3V 2500V 1500V 750V 200V 100V 150˚C Soldering Information TQFP Package Vapor Phase (60 sec.) Infrared (15 sec.) See AN-450 ″Surface Mounting and their Effects on Product Reliability″ for other methods of soldering surface mount devices. θJA (typ) — VBH48A 74˚C/W 215˚C 220˚C Operating Ratings Temperature Range TMIN ≤ TA ≤ TMAX Analog Supply Range Digital Supply Range −40˚C ≤ TA ≤ 85˚C 4.2V ≤ AVDD ≤ 5.5V 3.0V ≤ DVDD ≤ 5.5V Electrical Characteristics (Notes 1, 3) The following specifications apply for AVDD = 5V, DVDD = 5V, Fs = 48kHz, single codec configuration, unless otherwise noted. Limits apply for TA= 25˚C. The reference for 0dB is 1Vrms unless otherwise specified. Symbol Parameter Conditions LM4548 Typical (Note 7) AVDD DVDD DIDD Analog Supply Range Digital Supply Range Digital Quiescent Power Supply Current Analog Quiescent Power Supply Current Digital Shutdown Current Analog Shutdown Current Reference Voltage Power Supply Rejection Ratio CD Input to Line Output, -60dB Input THD+N, A-Weighted VO = -3dB, f = 1kHz, RL = 10kΩ DVDD = 5V DVDD = 3.3V AIDD IDSD IASD VREF PSRR 43 20 53 500 30 2.23 40 Limit (Note 8) 4.2 5.5 3.0 5.5 V (min) V (max) V (min) V (max) mA mA mA µA µA V dB Units (Limits) Analog Loopthru Mode Dynamic Range (Note 2) THD VIN Total Harmonic Distortion Line Input Voltage Mic Input with 20dB Gain Mic Input with 0dB Gain Xtalk ZIN CIN Crosstalk Input Impedance(Note 2) Input Capacitance Interchannel Gain Mismatch Record Gain Amplifier - A/D AS Mixer Section AS AM Step Size Mute Attenuation Resolution www.national.com 2 97 0.01 1 0.1 1 90 0.02 dB (min) % (max) Vrms Vrms Vrms dB Analog Input Section CD Left to Right -95 40 15 10 kΩ (min) pF dB dB dB dB Bits CD Left to Right 0dB to 22.5dB +12dB to -34.5dB 0.01 1.5 1.5 86 18 Step Size Analog to Digital Converters Electrical Characteristics (Notes 1, 3) Symbol Parameter (Continued) The following specifications apply for AVDD = 5V, DVDD = 5V, Fs = 48kHz, single codec configuration, unless otherwise noted. Limits apply for TA= 25˚C. The reference for 0dB is 1Vrms unless otherwise specified. Conditions LM4548 Typical (Note 7) Analog to Digital Converters Dynamic Range (Note 2) Frequency Response Digital to Analog Converters Resolution Dynamic Range (Note 2) THD Total Harmonic Distortion Frequency Response Group Delay (Note 2) Out of Band Energy Stop Band Rejection DT AS AM Discrete Tones Step Size Mute Attenuation 0dB to -46.5dB True Line Level Output Volume Section 1.5 86 0.30 x DVDD 0.40 x DVDD 0.50 x DVDD 0.20 x DVDD AC Link inputs High impedance AC Link outputs AC Link outputs 5 12.288 81.4 Variation of BIT_CLK period from 50% duty cycle 48 20.8 1.3 19.5 SDATA_IN, SDATA_OUT to falling edge of BIT_CLK Hold time of SDATA_IN, SDATA_OUT from falling edge of BIT_CLK BIT_CLK, SYNC, SDATA_IN or SDATA_OUT BIT_CLK, SYNC, SDATA_IN or SDATA_OUT For cold reset For cold reset 15 5 6 6 1.0 162.8 dB dB -40 70 -96 -60dB Input THD+N, A-Weighted VIN = -3dB, f=1kHz, RL = 10kΩ 18 89 0.01 20 - 21k 2 85 Bits dB (min) % Hz mS (max) dB dB dB -60dB Input THD+N, A-Weighted -1dB Bandwidth 90 20 86 dB (min) kHz Limit (Note 8) Units (Limits) Digital I/O (Note 2) VIL VHI VOH VOL IL IL IDR FBC TBCP TCH FSYNC TSP TSH TSL TSETUP THOLD TRISE TFALL TRST_LOW TRST2CLK Low level input voltage High level input voltage High level output voltage Low level output voltage Input Leakage Current Tri state Leakage Current Output drive current BIT_CLK frequency BIT_CLK period BIT_CLK high SYNC frequency SYNC period SYNC high pulse width SYNC low pulse width Setup Time Hold Time Rise Time Fall Time RESET# active low pulse width RESET# inactive to BIT_CLK start up V (max) V (min) V (min) V (max) µA µA mA MHz nS ± 10 ± 10 Digital Timing Specifications (Note 2) ± 20 % (max) kHz µS µS µS nS (min) nS (min) nS (max) nS (max) µS (min) nS (min) 3 www.national.com Electrical Characteristics (Notes 1, 3) Symbol Parameter (Continued) The following specifications apply for AVDD = 5V, DVDD = 5V, Fs = 48kHz, single codec configuration, unless otherwise noted. Limits apply for TA= 25˚C. The reference for 0dB is 1Vrms unless otherwise specified. Conditions LM4548 Typical (Note 7) Digital Timing Specifications (Note 2) TSH TSYNC2CLK TSU2RST TRST2HZ SYNC active high pulse width SYNC inactive to BIT_CLK start up Setup to trailing edge of RESET# Rising edge of RESET# to Hi-Z For warm reset For warm reset For ATE Test Mode For ATE Test Mode 1.3 162.8 15 25 µS nS (min) nS (min) nS (max) Limit (Note 8) Units (Limits) Note 1: All voltages are measured with respect to the ground pin, unless otherwise specified. Note 2: These specifications are guaranteed by design and characterization; they are not production tested. Note 3: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is functional, but do not guarantee specific performance limits. Electrical Characteristics state DC and AC electrical specifications under particular test conditions which guarantee specific performance limits. This assumes that the device is within the Operating Ratings. Specifications are not guaranteed for parameters where no limit is given, however, the typical value is a good indication of device performance. Note 4: The maximum power dissipation must be derated at elevated temperatures and is dictated by TJMAX, θJA, and the ambient temperature TA. The maximum allowable power dissipation is PDMAX = (TJMAX–TA)/θJA or the number given in Absolute Maximum Ratings, whichever is lower. For the LM4548, TJMAX = 150˚C. The typical junction-to-ambient thermal resistance is 74˚C/W for package number VBH48A. Note 5: Human body model, 100 pF discharged through a 1.5 kΩ resistor. Note 6: Machine Model, 220 pF–240 pF discharged through all pins. Note 7: Typicals are measured at 25˚C and represent the parametric norm. Note 8: Limits are guaranteed to National’s AOQL (Average Outgoing Quality Level). www.national.com 4 Timing Diagrams Clocks DS100987-10 Data Setup and Hold DS100987-11 Digital Rise and Fall DS100987-12 Cold Reset DS100987-13 Warm Reset DS100987-14 5 www.national.com Typical Application DS100987-3 FIGURE 2. LM4548 Typical Application Circuit www.national.com 6 Connection Diagram DS100987-2 Top View Order Number LM4548VH See NS Package Number VBH48A Pin Description Analog I/O Name Pin I/O Functional Description This is a mono input which gets summed into both the stereo line out and the true line level out after the National 3D Sound block. The PC_BEEP level can be adjusted from 0dB to −45dB in 3dB steps, or muted, via register 0Ah. This is a mono input which gets summed into both the stereo line out and the true line level out after the National 3D Sound block. The PHONE level can be adjusted from +12dB to −34.5dB in 1.5dB steps as well as muted via register 0Ch. This line level input can be routed through the Input Mux and recorded by the left ADC. In addition, this analog input gets summed into the left output stream. The amount of AUX_L signal mixed in the left output stream can be adjusted from +12dB to −34.5dB in 1.5dB steps as well as muted via register 16h. PC_BEEP 12 I PHONE 13 I AUX_L 14 I 7 www.national.com Pin Description Analog I/O Name (Continued) (Continued) Pin I/O Functional Description This line level input can be routed through the Input Mux and recorded by the right ADC. In addition, this analog input gets summed into the right output stream. The amount of AUX_R signal mixed in the right output stream can be adjusted from +12dB to −34.5dB in 1.5dB steps as well as muted via register 16h. This line level input can be routed through the Input Mux and recorded by the left ADC. In addition, this analog input gets summed into the left output stream. The amount of VIDEO_L signal mixed in the left output stream can be adjusted from +12dB to −34.5dB in 1.5dB steps as well as muted via register 14h. This line level input can be routed through the Input Mux and recorded by the right ADC. In addition, this analog input gets summed into the right output stream. The amount of VIDEO_R signal mixed in the right output stream can be adjusted from +12dB to −34.5dB in 1.5dB steps as well as muted via register 14h. This line level input can be routed through the Input Mux and recorded by the left ADC. In addition, this analog input gets summed into the left output stream. The amount of CD_L signal mixed in the left output stream can be adjusted from +12dB to −34.5dB in 1.5dB steps as well as muted via register 12h. This input can be used to reject common mode signals on the CD_L and CD_R inputs. CD_GND is an AC ground point and not a DC ground point. This input must be AC-coupled to the source signal’s ground. This line level input can be routed through the Input Mux and recorded by the right ADC. In addition, this analog input gets summed into the right output stream. The amount of CD_R signal mixed in the right output stream can be adjusted from +12dB to −34.5dB in 1.5dB steps as well as muted via register 12h. Either MIC1 or MIC2 can be selected via software and routed through the Input Mux for recording. The 20dB boost circuit is enabled/disabled via register 0Eh. Also, the amount of mic signal mixed in the output stream can be adjusted from +12dB to −34.5dB in 1.5dB steps as well as muted via register 0Eh. Either MIC1 or MIC2 can be selected via software and routed through the Input Mux for recording. The 20dB boost circuit is enabled/disabled via register 0Eh. Also, the amount of mic signal mixed in the output stream can be adjusted from +12dB to −34.5dB in 1.5dB steps as well as muted via register 0Eh. This line level input can be routed through the Input Mux and recorded by the left ADC. In addition, this analog input gets summed into the left output stream. The amount of LINE_IN_L signal mixed in the left output stream can be adjusted from +12dB to −34.5dB in 1.5dB steps as well as muted via register 10h. This line level input can be routed through the Input Mux and recorded by the right ADC. In addition, this analog input gets summed into the right output stream. The amount of LINE_IN_R signal mixed in the right output stream can be adjusted from +12dB to −34.5dB in 1.5dB steps as well as muted via register 10h. This is a post-mixed output for the left audio channel. The level of this output can be adjusted from 0dB to −45dB in 1.5dB steps as well as muted via register 02h. This is a post-mixed output for the right audio channel. The level of this output can be adjusted from 0dB to −45dB in 1.5dB steps as well as muted via register 02h. This line level output is either the post-mixed output or the mic input. The level of this output can be adjusted from 0dB to −45dB in 1.5dB steps as well as muted via register 06h. This is a post-mixed output for the left audio channel. The level of this output can be adjusted from 0dB to −45dB in 1.5dB steps as well as muted via register 04h. This is a post-mixed output for the right audio channel. The level of this output can be adjusted from 0dB to −45dB in 1.5dB steps as well as muted via register 04h. AUX_R 15 I VIDEO_L 16 I VIDEO_R 17 I CD_L 18 I CD_GND 19 I CD_R 20 I MIC1 21 I MIC2 22 I LINE_IN_L 23 I LINE_IN_R 24 I LINE_OUT_L LINE_OUT_R MONO_OUT LNLVL_OUT_L LNLVL_OUT_R 35 36 37 39 41 O O O O O www.national.com 8 Pin Description (Continued) Digital I/O and Clocking Name XTL_IN XTL_OUT SDATA_OUT Pin 2 3 5 I/O I O I Functional Description 24.576 MHz crystal input. Use a fundamental-mode type crystal. When operating from a crystal, a 1MΩ resistor must be connected across pins 2 and 3. 24.576 MHz crystal output. When operating from a crystal, a 1MΩ resistor must be connected across pins 2 and 3. This data stream contains both control data and DAC audio data. This input is sampled by the LM4548 on the falling edge of BIT_CLK. OUTPUT when in Primary Codec Mode: This pin outputs a 12.288 MHz clock which is derived (internally divided by two) from the 24.576MHz crystal input (XTL_IN). INPUT when in Secondary Codec Mode (Multiple Codec configurations only): 12.288MHz clock is to be supplied from an external source, such as from the BIT_CLK of a Primary Codec. This data stream contains both control data and ADC audio data. This output is clocked out by the LM4548 on the rising edge of BIT_CLK. 48kHz sync pulse which signifies the beginning of both the SDATA_IN and SDATA_OUT serial streams. SYNC must be synchronous to BIT_CLK. This active low signal causes a hardware reset which returns the control registers to their default conditions. ID0 and ID1 set the codec address for multiple codec use where ID0 is the LSB. Connect these pins to DVdd or GND as required. If these pins are not connected (NC), they default to Master Codec setting (same as connecting both pins to GND). These pins are of the same polarity as their internal ID0, ID1 registers. If pin 45 is connected to GND, then ID0 will be set to ″0″ internally. Connection to DVdd corresponds to a ″1″ internally. ID0 and ID1 set the codec address for multiple codec use where ID1 is the MSB. Connect these pins to DVdd or GND as required. If these pins are not connected (NC), they default to Master Codec setting (same as connecting both pins to GND). These pins are of the same polarity as their internal ID0, ID1 registers. If pin46 is connected to GND, then ID1 will be set to ″0″ internally. Connection to DVdd corresponds to a ″1″ internally. BIT_CLK 6 I/O SDATA_IN SYNC RESET# 8 10 11 O I I ID0 45 I ID1 46 I Power Supplies and References Name AVDD AVSS DVDD DVSS VREF VREFOUT AFILT1 AFILT2 Pin 25 26 1,9 4,7 27 28 29 30 I/O I I I I O O O O Analog supply. Analog ground. Digital supply. Digital ground. Nominal 2.2V reference output. Not intended to sink or source current. Bypassing of this pin should be done with short traces to maximize performance. Nominal 2.2V reference output. Can source up to 5mA of current and can be used to bias a microphone. This pin is not used and should be left open (NC). However, a capacitor to ground on this pin is permitted - it will not affect performance. This pin is not used and should be left open (NC). However, a capacitor to ground on this pin is permitted - it will not affect performance. These pins are used to complete the National 3D Sound circuit. Connect a 0.022µF capacitor between pins 3DP and 3DN. The National 3D Sound can be turned on and off via bit D13 in control register 20h. This is a fixed-depth type stereo enhance circuit, thus writing to register 22h has no effect. If National 3D Sound is not needed, then these pins should be left as no connect (NC). Functional Description 3DP, 3DN 33,34 O 9 www.national.com Typical Performance Characteristics ADC Noise Floor DAC Noise Floor Analog Loopthru Noise Floor DS100987-15 DS100987-16 DS100987-18 ADC Frequency Response DAC Frequency Response True Line Level Out Noise Floor (Analog Loopthrough) DS100987-19 DS100987-20 DS100987-18 www.national.com 10 LM4548 Register Map Name Reset Master Volume Mute Mute X Mute Mute Mute Mute Mute Mute Mute Mute X Mute X POP X X X ID1 X SR15 SR15 0 0 1 0 1 0 0 0 1 0 SR14 SR13 SR12 SR11 SR14 SR13 SR12 SR11 SR10 SR10 1 0 X X X X X X SR9 SR9 1 1 ID0 X X X X X PR6 PR5 PR4 PR3 PR2 PR1 PR0 0 X SR8 SR8 0 1 X X X X X X X X X 0 X SR7 SR7 0 0 X X X X X X X X X 3D X X X MIX MS LPBK X X X X 0 X SR6 SR6 1 0 X X X X X X X X X X X X GL3 GL2 GL1 GL0 X X X X X X X X X X SR5 SR5 0 0 X X X X SL2 SL1 SL0 X X X X X GL4 GL3 GL2 GL1 GL0 X X X X X X X X X X X X SR4 SR4 1 0 X X GL4 GL3 GL2 GL1 GL0 X X X GR4 GR4 X X GL4 GL3 GL2 GL1 GL0 X X X GR4 X X GL4 GL3 GL2 GL1 GL0 X X X GR4 GR3 GR3 GR3 GR3 X GR3 X X X X REF 0 X SR3 SR3 0 0 X X GL4 GL3 GL2 GL1 GL0 X X X GR4 GR3 X X X X X X X X 20dB X GN4 GN3 GN2 GR2 GR2 GR2 GR2 GR2 SR2 GR2 X X X X ANL X X SR2 SR2 0 0 X X X X X X X X X X GN4 GN3 GN2 X X X X X X X X X X PV3 PV2 PV1 X X X X X X X X X X X X X X PV0 GN1 GN1 GR1 GR1 GR1 GR1 GR1 SR1 GR1 X X X X DAC 0 X SR1 SR1 1 0 X X X X X X X X X X MM4 MM3 MM2 MM1 MM0 X X GN0 GN0 GR0 GR0 GR0 GR0 GR0 SR0 GR0 X X X X ADC 1 VRA SR0 SR0 1 0 X X ML4 ML3 ML2 ML1 ML0 X X X MR4 MR3 MR2 MR1 MR0 Mute X X ML4 ML3 ML2 ML1 ML0 X X X MR4 MR3 MR2 MR1 MR0 8008h 8000h 8000h 0000h 0000h 8008h 8008h 8808h 8808h 8808h 8808h 8808h 0000h 8000h 0000h 0000h 0000h 0000h na X001h XXX0h BB80h BB80h 4E53h 4300h X 0 0 0 1 1 0 1 0 1 0 1 0 0 0 0 0d50h D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Default REG 00h 02h 04h Master Volume Mono Reserved Phone Volume Mic Volume Line In Volume CD Volume Video Volume Aux Volume PCM Out Vol Record Select Record Gain Reserved True Line Level Out Volume 06h 08h 0Ah PC_BEEP Volume 0Ch 0Eh 10h 12h 14h 16h 18h 1Ah 11 1Ch 1Eh 20h General Purpose 22h Reserved Powerdown Ctrl/Stat 3D Control (3D is fixed depth) 24h 26h 28h Extended Audio ID 2Ah Extended Audio Status/Control 2Ch PCM Front DAC Rate 32h PCM ADC Rate 5Ah Vendor ID1 Vendor ID2 Vendor Reserved 7Ah Vendor Reserved 7Ch www.national.com 7Eh Application Information AC Link Serial Interface Protocol DS100987-4 FIGURE 3. AC 97 Bidirectional Audio Frame DS100987-6 FIGURE 4. AC Link Audio Output Frame AC Link Output Frame: SDATA_OUT (output from controller, input to LM4548) The audio output frame (output from AC ’97 Controller) contains control and PCM data targeted for the LM4548 control registers and stereo DAC. The Tag slot, slot 0, contains 16 bits that tell the AC Link interface circuitry on the LM4548 the validity of the following data slots. A new audio output frame is signaled with a low to high transition of SYNC. SYNC is synchronous to the rising edge of BIT_CLK. On the next rising edge of BIT_CLK, the AC ’97 Controller drives SDATA_OUT with the first bit of slot 0. The LM4548 samples SDATA_OUT on the falling edge of BIT_CLK. The AC ’97 Controller will continue outputting the SDATA_OUT stream on each successive rising edge of BIT_CLK. SDATA_OUT Slot 0: Tag Phase The first bit of slot 0 is designated the ″Valid Frame″ bit. If this bit is 1, it indicates that the current data frame contains at least one slot of valid data and the LM4548 will further sample the next four bits to determine which frames do in fact have valid data. Valid slots are signified by a 1 in their respective slot bit position. Bit 15 DS100987-5 FIGURE 5. Start of Audio Output Frame Description Valid Frame Control register address Control register data Left Playback PCM Data Comment 1 = This frame has valid data. 1 = Control Address is valid. 1 = Control Data is valid. 1 = Left PCM Data is valid. 14 13 12 www.national.com 12 Application Information Bit 11 Description Right Playback PCM Data (Continued) Bits 19:4 3:0 Description Control Register Write Data Reserved Comment Set bits to ″0″ if read operation Set to ″0″ Comment 1 = Right PCM Data is valid. SDATA_OUT Slot 1: Control Address Slot 1 is used both to write to the LM4548 registers as well as read back a register’s current value. The MSB of Slot 1 (bit 19) signifies whether the current control operation is a read or a write. Bits 18 through 12 are used to specify the register address of the read or write operation. The least significant twelve bits are reserved and should be stuffed with zeros by the AC’97 controller. Bits 19 18:12 11:0 Description Read/Write Control Register Reserved Comment 0 = Read, 1 = Write Identifies the Control Register Set to ″0″ SDATA_OUT Slot 3: PCM Playback Left Channel Slot 3 is a 20 bit field used to transmit data intended for the left DAC on the LM4548. Any unused bits should be padded with zeros. The LM4548 DAC’s have 18 bit resolution and thus will use the first 18 bits of the 20 bit PCM stream. Bits 19:0 Description PCM Audio Data for Left DAC Comment Set unused bits to ″0″ SDATA_OUT Slot 2: Control Data Slot 2 is used to transmit 16 bit control data to the LM4548 in the event that the current operation is a write operation. The least significant four bits should be stuffed with zeros by the AC ’97 controller. If the current operation is a register read, the entire slot, bits 19 through 0 should be stuffed with zeros. SDATA_OUT Slot 4: PCM Playback Right Channel Slot 4 is a 20 bit field used to transmit data intended for the right DAC on the LM4548. Any unused bits should be padded with zeros. The LM4548 DAC’s have 18 bit resolution and thus will use the first 18 bits of the 20 bit PCM stream. Bits 19:0 Description PCM Audio Data for Right DAC Comment Set unused bits to ″0″ SDATA_OUT Slots 5-12: Reserved Set these SDATA_OUT slots to ″0″ as they are not currently implemented and are reserved for future use. DS100987-8 FIGURE 6. AC Link Audio Input Frame AC Link Input Frame: SDATA_IN (input to controller, output from LM4548) The audio input frame (input to the AC ’97 Digital Controller) contains status and PCM data from the LM4548 control registers and stereo ADC. The Tag slot, slot 0, contains 16 bits that tell the AC ’97 Digital Controller whether the LM4548 is ready and the validity of data from certain device subsections. A new audio input frame is signaled with a low to high transition of SYNC. SYNC is synchronous to the rising edge of BIT_CLK. On the next rising edge of BIT_CLK, the LM4548 drives SDATA_IN with the first bit of slot 0. The Digital Controller samples SDATA_IN on the falling edge of BIT_CLK. The LM4548 will continue outputting the SDATA_IN stream on each successive rising edge of BIT_CLK. The LM4548 outputs data MSB first, in a MSB justified format. All reserved bits and slots are stuffed with ″0″ ’s by the LM4548. SDATA_IN Slot 0: Codec Status Bits The first bit of SDATA_IN Slot 0 (bit 15) indicates when the Codec is ready. The digital controller must probe further to see which other subsections are ready. 13 www.national.com Application Information (Continued) Bits 9:2 1,0 Description Other Slot Request bits Reserved Comment Unused Stuff with ″0″ SDATA_IN Slot 2: Status Data The slot returns the control register data. The data returned was initiated by a read request in the previous SDATA_OUT frame, slot 1. Bits 19:4 3:0 DS100987-7 Description Control Register Read Data Reserved Comment Stuffed with ″0″ ’s FIGURE 7. Start of Audio Input Frame Bit 15 14 13 12 11 Description Codec Ready Bit Slot 1 data valid Slot 2 data valid Slot 3 data valid Slot 4 data valid Comment 0=Not Ready, 1=Ready Status Address is valid Status Data is valid Left Audio PCM Data is valid Right Audio PCM Data is valid SDATA_IN Slot 3: PCM Record Left Channel This slot contains the left ADC sample data. The signal to be digitized is selected via register 1Ah and subsequently routed through the Input Mux for recording by the left ADC. This is a 20-bit slot, where the digitized 18-bit PCM data is output from the codec MSB first and the last remaining 2 bits will zeros. Bits 19:2 1:0 Description PCM Record Left Channel data Reserved Comment 18 bit audio sample from left ADC Stuffed with ″0″’s SDATA_IN Slot 1: Status Address / Slot Request Bits This slot echoes the control register which a read was requested on. The address echoed was initiated by a read request in the previous SDATA_OUT frame, slot 1. Bits 11 and 10 are slot request bits that support Sample Rate Conversion (SRC) functionality. If bit 11 is set to 0, then the controller should respond with a valid PCM left sample in slot 3 of the next frame. If bit 10 is set to 0, then the controller should respond with a valid PCM right sample in slot 4 of the next frame. If bits 11 or 10 are set to 1, the controller should not send data in the next frame. Bits 9 through 2 are unused. Bits 1 and 0 are reserved and should be set to 0. Bits 19 18:12 Description Reserved Control Register Index Comment Stuffed with ″0″ Echo of Control Register for which data is being returned. 0 = Controller should send valid slot 3 data in the next frame, 1 = Controller should not send slot 3 data in the next frame 0 = Controller should send valid slot 4 data in the next frame, 1 = Controller should not send slot 4 data in the next frame SDATA_IN Slot 4: PCM Record Right Channel This slot contains the right ADC sample data. The signal digitized is selected via register 1Ah and subsequently routed through the Input Mux for recording by the right ADC. This is a 20-bit slot, where the digitized 18-bit PCM data is output from the codec MSB first and the last remaining 2 bits will zeros. Bits 19:2 1:0 Description PCM Record Right Channel data Reserved Comment 18 bit audio sample from right ADC Stuffed with ″0″’s SDATA_IN Slots 5-12: Reserved These SDATA_IN slots are set to ″0″ as they are reserved for future use. AC Link Low Power Mode 11 Slot 3 Request bit (PCM left) 10 Slot 4 Request bit (PCM right) DS100987-9 FIGURE 8. AC Link Powerdown Timing www.national.com 14 Application Information Register Descriptions (Continued) SL2:SL0 0 1 2 3 4 5 6 7 SR2:SR0 0 1 2 3 4 5 6 7 Left Record Source Mic CD In (L) Video In (L) Aux In (L) Line In (L) Stereo Mix (L) Mono Mix (L) Phone Right Record Source Mic CD In (R) Video In (R) Aux In (R) Line In (R) Stereo Mix (R) Mono Mix (R) Phone Reset Register (00h) Writing any value to this register causes a register reset which changes all of the registers back to their default values. If a read is performed on this register, the LM4548 will return a value of 0D50h indicating that National 3D Sound is implemented, 18bit data is supported for both the ADC’s and DAC’s, and the volume control for True Line Level Out is supported. Master Volume Registers (02h, 04h, 06h) These registers allow the output levels from LINE_OUT, LNLVL_OUT and MONO_OUT to be attenuated or muted. There are 6-bits of volume control, plus one mute bit. It is a 5-bit volume range, where each step is nominally 1.5dB and each output can be individually muted by either setting the most significant bit (Mx5), and/or the mute bit (D15) to ″1.″ Mute 0 0 0 1 Mx5:Mx0 00 0000 01 1111 1X XXXX XX XXXX Function 0dB attenuation 46.5dB attenuation 46.5dB attenuation mute Default: 8000h PC Beep Register (0Ah) This register controls the level of the PC_BEEP input. The PC_BEEP can be both attenuated and muted via register 0Ah. Step size is nominally 3dB. The signal present after the attenuation and mute block is summed into both the left and right channels. Mute 0 0 1 Default: 0000h Mixer Input Volume Registers (Index 0Ch - 18h) These registers set the input volume levels including mute. Each volume control is 5 bit which provides from a range of +12dB gain to 34.5dB attenuation in 1.5dB steps. For stereo ports, the left and right levels can be independently set. Muting a given port is accomplished by setting the MSB to 1. Setting the MSB to 1 for stereo ports mutes both the left and right channel. Register 0Eh has an additional 20dB boost for a microphone level input. This is enabled by setting bit 6 of register 0Eh to 1. Mute 0 0 0 1 Gx4:Gx0 00000 01000 11111 XXXXX Function +12dB gain 0dB gain 34.5dB attenuation mute PV3:0 0000 1111 XXXX Function 0dB attenuation 45dB attenuation mute Record (Input) Gain Register (1Ch) This registers controls the Record (Input) Gain level for the stereo input selected via the Record Select Control Register (1Ah). The gain can be programmed from 0dB to +22.5dB in 1.5dB steps. The level for the left and right channel can be individually controlled. The input can also be muted by setting the MSB to 1. Mute 0 0 1 Default: 8000h General Purpose Register (20h) This register controls many miscellaneous functions implemented on the LM4548. The miscellaneous functions include POP which allows the PCM to bypass the National 3D Sound circuitry, 3D which enables or disables the National 3D Sound circuitry, MIX which selects the MONO_OUT source, MS which selects the microphone mux source and LPBK which connects the output of the stereo ADC to input of the stereo DAC. LPBK provides for a digital loopthru path when enabled. BIT POP 3D MIX MS LPBK Function PCM out path and mute, 0 = pre 3D, 1 = post 3D National 3D Sound on / off 1 = on Mono output select 0 = Mix, 1 = Mic Mic select 0 = Mic1 1 = Mic2 ADC/DAC loopback Gx3:Gx0 1111 0000 XXXX Function 22.5dB gain 0dB gain mute Default: 8008h (mono regs.), 8808h (stereo regs.) Record Select Register (1Ah) This register independently controls the source for the right and left channel which will be recorded by the stereo ADC. The default value is 0000h which corresponds to Mic in. 15 Powerdown Control / Status Register (26h) This read/write register is used to monitor subsystem readiness and also to program the LM4548 powerdown states. The lower half of this register is read only with a ″1″, indicating the subsection is ready. Writing to the lower 8 bits will have no effect. www.national.com Application Information (Continued) SR15:SR0 2B11h 3E80h 5622h AC44h BB80h Sample Rate (Hz) 11025 16000 22050 44100 48000 When the AC Link ″Codec Ready″ indicator bit (SDATA_IN slot 0, bit 15) is a ″1″, it indicates that the AC Link and AC ’97 registers are in a fully operational state. The AC ’97 Controller must further probe the Powerdown Control / Status Register to determine exactly which subsections are ready. BIT REF ANL DAC ADC Function Vref’s up to nominal level Analog mixers ready DAC section ready to accept data ADC section ready to transmit data Reserved Registers Do not write to these registers as they are reserved. Supported powerdown modes. BIT PRO PR1 PR2 PR3 PR4 PR5 PR6 Function PCM in ADC’s and Input Mux powerdown PCM out DAC’s powerdown Analog Mixer powerdown (VREF still on) Analog Mixer powerdown (VREF off) Digital Interface (AC Link) powerdown (external clk off) Internal Clk disable not used Extended Audio ID Register (28h) This read only register identifies which AC97 Extended Audio features are supported. The LM4548 provides for VRA (Variable Rate Audio) and Multiple Codec support. VRA is indicated by a ″1″ in the LSB of register 28h. The two MSB’s, ID1 and ID0, show the current codec configuration as connected via external pins 45 and 46. Pin46 (ID1) NC (not connected) GND GND DVdd DVdd Pin45 (ID0) NC (not connected) GND DVdd GND DVdd Reg 28h ID1 0 0 0 1 1 Reg 28h ID0 0 0 1 0 1 Codec Mode Primary Primary Secondary 1 Secondary 2 Secondary 3 Extended Audio Status/Control Register (2Ah) This read/write register provides status and control of the Variable Sample Rate function. Setting the LSB of this register to ″1″ enables Variable Rate Audio (VRA) mode and allows DAC and ADC sample rates to be programmed via registers 2Ch and 32h. BIT VRA Function 0 = VRA off (48kHz fixed), 1 = VRA on Sample Rate Control Registers (2Ch, 32h) These read/write registers are used to set the sample rate for the left and right channels of the DAC (2Ch) and the ADC (32h). When Variable Rate Audio is enabled via bit-0 of Register 2Ah, the sample rates can be programmed, in 1Hz increments, to be any value from 4kHz to 48kHz. Below is a list of the most common sample rates and their corresponding register values. SR15:SR0 1F40h Sample Rate (Hz) 8000 www.national.com 16 17 LM4548 AC ’97 Rev 2 Codec with Sample Rate Conversion and National 3D Sound Physical Dimensions inches (millimeters) unless otherwise noted 48-Lead , TQFP, 7 X 7 X 1.4mm, JEDEC (M) Order Number LM4548VH NS Package Number VBH48A LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component is any component of a life support 1. Life support devices or systems are devices or sysdevice or system whose failure to perform can be reatems which, (a) are intended for surgical implant into sonably expected to cause the failure of the life support the body, or (b) support or sustain life, and whose faildevice or system, or to affect its safety or effectiveness. ure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. National Semiconductor Corporation Americas Tel: 1-800-272-9959 Fax: 1-800-737-7018 Email: support@nsc.com National Semiconductor Europe Fax: +49 (0) 1 80-530 85 86 Email: europe.support@nsc.com Deutsch Tel: +49 (0) 1 80-530 85 85 English Tel: +49 (0) 1 80-532 78 32 Français Tel: +49 (0) 1 80-532 93 58 Italiano Tel: +49 (0) 1 80-534 16 80 National Semiconductor Asia Pacific Customer Response Group Tel: 65-2544466 Fax: 65-2504466 Email: sea.support@nsc.com National Semiconductor Japan Ltd. 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