LM5101A

LM5100A/B/C, LM5101A/B/C 3A, 2A and 1A High Voltage High-Side and Low-Side Gate Drivers November 2006 LM5100A/B/C LM5101A/B/C 3A, 2A and 1A High Voltage High-Side and Low-Side Gate Drivers General Description The LM5100A/B/C and LM5101A/B/C High Voltage Gate Drivers are designed to drive both the high-side and the low-side N-Channel MOSFETs in a synchronous buck or a half-bridge configuration. The floating high-side driver is capable of operating with supply voltages up to 100V. The “A” versions provide a full 3A of gate drive while the “B” and “C” versions provide 2A and 1A respectively. The outputs are independently controlled with CMOS input thresholds (LM5100A/B/C) or TTL input thresholds (LM5101A/B/C). An integrated high voltage diode is provided to charge the highside gate drive bootstrap capacitor. A robust level shifter operates at high speed while consuming low power and providing clean level transitions from the control logic to the high-side gate driver. Under-voltage lockout is provided on both the low-side and the high-side power rails. These devices are available in the standard SOIC - 8 pin and the LLP - 10 pin packages. Features n Drives both a high-side and low-side N-Channel MOSFETs n Independent high and low driver logic inputs n Bootstrap supply voltage up to 118V DC n Fast propagation times (25 ns typical) n Drives 1000 pF load with 8 ns rise and fall times n Excellent propagation delay matching (3 ns typical) n Supply rail under-voltage lockout n Low power consumption n Pin compatible with HIP2100/HIP2101 Typical Applications n n n n n Current Fed push-pull converters Half and Full Bridge power converters Synchronous buck converters Two switch forward power converters Forward with Active Clamp converters Package n SOIC-8 n LLP-10 (4 mm x 4 mm) Simplified Block Diagram 20203103 FIGURE 1. © 2006 National Semiconductor Corporation DS202031 www.national.com LM5100A/B/C, LM5101A/B/C Input/Output Options Part Number LM5100A LM5101A LM5100B LM5101B LM5100C LM5101C Input Thresholds CMOS TTL CMOS TTL CMOS TTL Peak Output Current 3A 3A 2A 2A 1A 1A Connection Diagrams 20203101 20203102 FIGURE 2. Ordering Information Ordering Number LM5100A/LM5101A M LM5100A/LM5101A MX LM5100A /LM5101A SD LM5100A/LM5101A SDX LM5100B/LM5101B MA LM5100B/LM5101B MAX LM5100B/LM5101B SD LM5100B/LM5101B SDX LM5100C/LM5101C MA LM5100C/LM5101C MAX LM5100C /LM5101C SD LM5100C/LM5101C SDX Package Type SOIC 8 SOIC 8 LLP 10 LLP 10 SOIC 8 SOIC 8 LLP 10 LLP 10 SOIC 8 SOIC 8 LLP 10 LLP 10 NSC Package Drawing M08A M08A SDC 10A SDC 10A M08A M08A SDC 10A SDC 10A M08A M08A SDC 10A SDC 10A Supplied As 95 units shipped in anti static rails 2500 shipped in Tape & Reel 1000 shipped in Tape & Reel 4500 shipped in Tape & Reel 95 units shipped in anti static rails 2500 shipped in Tape & Reel 1000 shipped in Tape & Reel 4500 shipped in Tape & Reel 95 units shipped in anti static rails 2500 shipped in Tape & Reel 1000 shipped in Tape & Reel 4500 shipped in Tape & Reel www.national.com 2 LM5100A/B/C, LM5101A/B/C Pin Descriptions Pin # SO-8 1 2 LLP-10 1 2 Name VDD HB Description Positive gate drive supply High-side gate driver bootstrap rail High-side gate driver output High-side MOSFET source connection High-side driver control input Application Information Locally decouple to VSS using low ESR/ESL capacitor located as close to the IC as possible. Connect the positive terminal of the bootstrap capacitor to HB and the negative terminal to HS. The bootstrap capacitor should be placed as close to the IC as possible. Connect to the gate of high-side MOSFET with a short, low inductance path. Connect to the bootstrap capacitor negative terminal and the source of the high-side MOSFET. The LM5100A/B/C inputs have CMOS type thresholds. The LM5101A/B/C inputs have TTL type thresholds. Unused inputs should be tied to ground and not left open. The LM5100A/B/C inputs have CMOS type thresholds. The LM5101A/B/C inputs have TTL type thresholds. Unused inputs should be tied to ground and not left open. All signals are referenced to this ground. Connect to the gate of the low-side MOSFET with a short, low inductance path. 3 4 5 3 4 7 HO HS HI 6 8 LI Low-side driver control input 7 8 9 10 VSS LO Ground return Low-side gate driver output Note: For LLP-10 package, it is recommended that the exposed pad on the bottom of the package be soldered to ground plane on the PC board, and that ground plane should extend out from beneath the IC to help dissipate heat. Pins 5 and 6 have no connection. 3 www.national.com LM5100A/B/C, LM5101A/B/C Absolute Maximum Ratings (Note 1) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. VDD to VSS HB to HS LI or HI Input LO Output HO Output HS to VSS (Note 6) HB to VSS Junction Temperature −0.3V to +18V −0.3V to +18V −0.3V to VDD +0.3V −0.3V to VDD +0.3V VHS −0.3V to VHB +0.3V −5V to +100V 118V +150˚C Storage Temperature Range ESD Rating HBM (Note 2) −55˚C to +150˚C 2 kV Recommended Operating Conditions VDD HS HB HS Slew Rate Junction Temperature +9V to +14V −1V to 100V VHS +8V to VHS +14V < 50 V/ns −40˚C to +125˚C Electrical Characteristics Limits in standard type are for TJ = 25˚C only; limits in boldface type apply over the junction temperature (TJ) range of -40˚C to +125˚C. Minimum and Maximum limits are guaranteed through test, design, or statistical correlation. Typical values represent the most likely parametric norm at TJ = 25˚C, and are provided for reference purposes only. Unless otherwise specified, VDD = VHB = 12V, VSS = VHS = 0V, No Load on LO or HO (Note 4). Symbol SUPPLY CURRENTS IDD IDDO IHB IHBO IHBS IHBSO VIL VIL VIHYS VIHYS RI VDDR VDDH VHBR VHBH VDL VDH RD VDD Quiescent Current, LM5100A/B/C VDD Quiescent Current, LM5101A/B/C VDD Operating Current Total HB Quiescent Current Total HB Operating Current HB to VSS Current, Quiescent HB to VSS Current, Operating Input Voltage Threshold LM5100A/B/C Input Voltage Threshold LM5101A/B/C Input Voltage Hysteresis LM5100A/B/C Input Voltage Hysteresis LM5101A/B/C Input Pulldown Resistance VDD Rising Threshold VDD Threshold Hysteresis HB Rising Threshold HB Threshold Hysteresis Low-Current Forward Voltage High-Current Forward Voltage Dynamic Resistance LM5100A/B/C, LM5101A/B/C Low-Level Output Voltage LM5100A/LM5101A Low-Level Output Voltage LM5100B/LM5101B Low-Level Output Voltage LM5100C/LM5101C IVDD-HB = 100 µA IVDD-HB = 100 mA IVDD-HB = 100 mA 5.7 100 6.0 LI = HI = 0V LI = HI = 0V f = 500 kHz LI = HI = 0V f = 500 kHz HS = HB = 100V f = 500 kHz Rising Edge Rising Edge 4.5 1.3 0.1 0.25 2.0 0.06 1.6 0.1 0.4 5.4 1.8 500 50 200 6.9 0.5 6.6 0.4 0.52 0.8 1.0 0.85 1 1.65 7.1 400 7.4 6.3 2.3 0.2 0.4 3 0.2 3 10 mA mA mA mA µA mA V V mV mV kΩ V V V V V V Ω Parameter Conditions Min Typ Max Units INPUT PINS UNDER VOLTAGE PROTECTION BOOT STRAP DIODE LO & HO GATE DRIVER VOL IHO = ILO = 100 mA 0.12 0.16 0.28 0.25 0.4 0.65 V www.national.com 4 LM5100A/B/C, LM5101A/B/C Electrical Characteristics (Continued) Limits in standard type are for TJ = 25˚C only; limits in boldface type apply over the junction temperature (TJ) range of -40˚C to +125˚C. Minimum and Maximum limits are guaranteed through test, design, or statistical correlation. Typical values represent the most likely parametric norm at TJ = 25˚C, and are provided for reference purposes only. Unless otherwise specified, VDD = VHB = 12V, VSS = VHS = 0V, No Load on LO or HO (Note 4). Parameter High-Level Output Voltage LM5100A/LM5101A High-Level Output Voltage LM5100B/LM5101B High-Level Output Voltage LM5100C/LM5101C Conditions IHO = ILO = 100 mA VOH = VDD– LO or VOH = HB - HO Min Typ Max Units Symbol LO & HO GATE DRIVER VOH 0.24 0.28 0.60 0.45 0.60 1.10 V IOHL Peak Pullup Current LM5100A/LM5101A Peak Pullup Current LM5100B/LM5101B Peak Pullup Current LM5100C/LM5101C HO, LO = 0V 3 2 1 A IOLL Peak Pulldown Current LM5100A/LM5101A Peak Pulldown Current LM5100B/LM5101B Peak Pulldown Current LM5100C/LM5101C HO, LO = 12V 3 2 1 A THERMAL RESISTANCE θJA Junction to Ambient SOIC-8 LLP-10 (Note 3) 170 40 ˚C/W Switching Characteristics Limits in standard type are for TJ = 25˚C only; limits in boldface type apply over the junction temperature (TJ) range of -40˚C to +125˚C. Minimum and Maximum limits are guaranteed through test, design, or statistical correlation. Typical values represent the most likely parametric norm at TJ = 25˚C, and are provided for reference purposes only. Unless otherwise specified, VDD = VHB = 12V, VSS = VHS = 0V, No Load on LO or HO (Note 4). Symbol tLPHL Parameter LO Turn-Off Propagation Delay LM5100A/B/C LO Turn-Off Propagation Delay LM5101A/B/C tLPLH LO Turn-On Propagation Delay LM5100A/B/C LO Turn-On Propagation Delay LM5101A/B/C tHPHL HO Turn-Off Propagation Delay LM5100A/B/C HO Turn-Off Propagation Delay LM5101A/B/C tHPLH LO Turn-On Propagation Delay LM5100A/B/C LO Turn-On Propagation Delay LM5101A/B/C tMON Delay Matching: LO on & HO off LM5100A/B/C Delay Matching: LO on & HO off LM5101A/B/C tMOFF Delay Matching: LO off & HO on LM5100A/B/C Delay Matching: LO on & HO off LM5101A/B/C tRC, tFC Either Output Rise/Fall Time CL = 1000 pF HI Rising to HO Rising HI Falling to HO Falling LI Rising to LO Rising Conditions LI Falling to LO Falling Min Typ 20 22 20 26 20 22 20 26 1 4 1 4 8 Max 45 ns 56 45 ns 56 45 ns 56 45 ns 56 10 10 10 ns 10 ns ns Units 5 www.national.com LM5100A/B/C, LM5101A/B/C Switching Characteristics (Continued) Limits in standard type are for TJ = 25˚C only; limits in boldface type apply over the junction temperature (TJ) range of -40˚C to +125˚C. Minimum and Maximum limits are guaranteed through test, design, or statistical correlation. Typical values represent the most likely parametric norm at TJ = 25˚C, and are provided for reference purposes only. Unless otherwise specified, VDD = VHB = 12V, VSS = VHS = 0V, No Load on LO or HO (Note 4). Parameter Output Rise Time (3V to 9V) LM5100A/LM5101A Output Rise Time (3V to 9V) LM5100B/LM5101B Output Rise Time (3V to 9V) LM5100C/LM5101C Conditions CL = 0.1 µF Min Typ 430 ns 570 990 CL = 0.1 µF 260 430 715 50 IF = 100 mA, IR = 100 mA 37 ns ns ns Max Units Symbol tR tF Output Fall Time (3V to 9V) LM5100A/LM5101A Output Fall Time (3V to 9V) LM5100B/LM5101B Output Fall Time (3V to 9V) LM5100C/LM5101C tPW tBS Minimum Input Pulse Width that Changes the Output Bootstrap Diode Reverse Recovery Time Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the component may occur. Operating Ratings are conditions under which operation of the device is guaranteed. Operating Ratings do not imply guaranteed performance limits. For guaranteed performance limits and associated test conditions, see the Electrical Characteristics tables. Note 2: The human body model is a 100 pF capacitor discharged through a 1.5kΩ resistor into each pin. 2 kV for all pins except Pin 2, Pin 3 and Pin 4 which are rated at 1000V. Note 3: 4 layer board with Cu finished thickness 1.5/1/1/1.5 oz. Maximum die size used. 5x body length of Cu trace on PCB top. 50 x 50mm ground and power planes embedded in PCB. See Application Note AN-1187. Note 4: Min and Max limits are 100% production tested at 25˚C. Limits over the operating temperature range are guaranteed through correlation using Statistical Quality Control (SQC) methods. Limits are used to calculate National’s Average Outgoing Quality Level (AOQL). Note 5: The θJA is not a given constant for the package and depends on the printed circuit board design and the operating environment. Note 6: In the application the HS node is clamped by the body diode of the external lower N-MOSFET, therefore the HS node will generally not exceed -1V. However, in some applications, board resistance and inductance may result in the HS node exceeding this stated voltage transiently. If negative transients occur, the HS voltage must never be more negative than VDD-15V. For example if VDD = 10V, the negative transients at HS must not exceed -5V. www.national.com 6 LM5100A/B/C, LM5101A/B/C Typical Performance Characteristics Peak Sourcing Current vs VDD Peak Sinking Current vs VDD 20203127 20203128 Sink Current vs Output Voltage Source Current vs Output Voltage 20203129 20203130 LM5100A/B/C IDD vs Frequency LM5101A/B/C IDD vs Frequency 20203110 20203109 7 www.national.com LM5100A/B/C, LM5101A/B/C Typical Performance Characteristics Operating Current vs Temperature (Continued) IHB vs Frequency 20203111 20203114 Quiescent Current vs Supply Voltage Quiescent Current vs Temperature 20203118 20203119 Undervoltage Rising Thresholds vs Temperature Undervoltage Threshold Hysteresis vs Temperature 20203122 20203117 www.national.com 8 LM5100A/B/C, LM5101A/B/C Typical Performance Characteristics Bootstrap Diode Forward Voltage (Continued) LM5100A/B/C Input Threshold vs Temperature 20203123 20203115 LM5101A/B/C Input Threshold vs Temperature LM5100A/B/C Input Threshold vs VDD 20203124 20203125 LM5101A/B/C Input Threshold vs VDD LM5100A/B/C Propagation Delay vs Temperature 20203126 20203112 9 www.national.com LM5100A/B/C, LM5101A/B/C Typical Performance Characteristics LM5101A/B/C Propagation Delay vs Temperature (Continued) LO & HO Gate Drive - High Level Output Voltage vs Temperature 20203120 20203113 LO & HO Gate Drive - Low Level Output Voltage vs Temperature LO & HO Gate Drive - Output High Voltage vs VDD 20203121 20203131 LO & HO Gate Drive - Output Low Voltage vs VDD 20203132 www.national.com 10 LM5100A/B/C, LM5101A/B/C Timing Diagram 20203104 FIGURE 3. Layout Considerations The optimum performance of high and low-side gate drivers cannot be achieved without taking due considerations during circuit board layout. Following points are emphasized. 1. Low ESR / ESL capacitors must be connected close to the IC, between VDD and VSS pins and between the HB and HS pins to support the high peak currents being drawn from VDD during turn-on of the external MOSFET. 2. To prevent large voltage transients at the drain of the top MOSFET, a low ESR electrolytic capacitor must be connected between MOSFET drain and ground (VSS). 3. In order to avoid large negative transients on the switch node (HS pin), the parasitic inductances in the source of top MOSFET and in the drain of the bottom MOSFET (synchronous rectifier) must be minimized. 4. Grounding Considerations: a) The first priority in designing grounding connections is to confine the high peak currents that charge and discharge the MOSFET gate into a minimal physical area. This will decrease the loop inductance and minimize noise issues on the gate terminal of the MOSFET. The MOSFETs should be placed as close as possible to the gate driver. b) The second high current path includes the bootstrap capacitor, the bootstrap diode, the local ground referenced bypass capacitor and low-side MOSFET body diode. The bootstrap capacitor is recharged on a cycle-by-cycle basis through the bootstrap diode from the ground referenced VDD bypass capacitor. The recharging occurs in a short time interval and involves high peak current. Minimizing this loop length and area on the circuit board is important to ensure reliable operation. losses are related to the switching frequency (f), output load capacitance on LO and HO (CL), and supply voltage (VDD) and can be roughly calculated as: PDGATES = 2 • f • CL • VDD2 There are some additional losses in the gate drivers due to the internal CMOS stages used to buffer the LO and HO outputs. The following plot shows the measured gate driver power dissipation versus frequency and load capacitance. At higher frequencies and load capacitance values, the power dissipation is dominated by the power losses driving the output loads and agrees well with the above equation. This plot can be used to approximate the power losses due to the gate drivers. Gate Driver Power Dissipation (LO + HO) VDD = 12V, Neglecting Diode Losses 20203105 Power Dissipation Considerations The total IC power dissipation is the sum of the gate driver losses and the bootstrap diode losses. The gate driver The bootstrap diode power loss is the sum of the forward bias power loss that occurs while charging the bootstrap capacitor and the reverse bias power loss that occurs during reverse recovery. Since each of these events happens once per cycle, the diode power loss is proportional to frequency. 11 www.national.com LM5100A/B/C, LM5101A/B/C Power Dissipation Considerations (Continued) Larger capacitive loads require more energy to recharge the bootstrap capacitor resulting in more losses. Higher input voltages (VIN) to the half bridge result in higher reverse recovery losses. The following plot was generated based on calculations and lab measurements of the diode recovery time and current under several operating conditions. This can be useful for approximating the diode power dissipation. The total IC power dissipation can be estimated from the previous plots by summing the gate drive losses with the bootstrap diode losses for the intended application. Diode Power Dissipation VIN = 50V 20203106 www.national.com 12 LM5100A/B/C, LM5101A/B/C Physical Dimensions inches (millimeters) unless otherwise noted Controlling dimension is inch. Values in [ ] are millimeters. Notes: Unless otherwise specified. 1. 2. 3. Standard lead finish to be 200 microinches/5.08 micrometers minimum lead/tin (solder) on copper. Dimension does not include mold flash. Reference JEDEC registration MS-012, Variation AA, dated May 1990. SOIC-8 Outline Drawing NS Package Number M08A 13 www.national.com LM5100A/B/C, LM5101A/B/C 3A, 2A and 1A High Voltage High-Side and Low-Side Gate Drivers Physical Dimensions inches (millimeters) unless otherwise noted (Continued) Notes: Unless otherwise specified. 1. For solder thickness and composition, see “Solder Information” in the packaging section of the National Semiconductor web page (www.national.com). 2. Maximum allowable metal burr on lead tips at the package edges is 76 microns. 3. No JEDEC registration as of May 2003. LLP-10 Outline Drawing NS Package Number SDC10A THE CONTENTS OF THIS DOCUMENT ARE PROVIDED IN CONNECTION WITH NATIONAL SEMICONDUCTOR CORPORATION (″NATIONAL″) PRODUCTS. NATIONAL MAKES NO REPRESENTATIONS OR WARRANTIES WITH RESPECT TO THE ACCURACY OR COMPLETENESS OF THE CONTENTS OF THIS PUBLICATION AND RESERVES THE RIGHT TO MAKE CHANGES TO SPECIFICATIONS AND PRODUCT DESCRIPTIONS AT ANY TIME WITHOUT NOTICE. NO LICENSE, WHETHER EXPRESS, IMPLIED, ARISING BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. TESTING AND OTHER QUALITY CONTROLS ARE USED TO THE EXTENT NATIONAL DEEMS NECESSARY TO SUPPORT NATIONAL’S PRODUCT WARRANTY. EXCEPT WHERE MANDATED BY GOVERNMENT REQUIREMENTS, TESTING OF ALL PARAMETERS OF EACH PRODUCT IS NOT NECESSARILY PERFORMED. NATIONAL ASSUMES NO LIABILITY FOR APPLICATIONS ASSISTANCE OR BUYER PRODUCT DESIGN. BUYERS ARE RESPONSIBLE FOR THEIR PRODUCTS AND APPLICATIONS USING NATIONAL COMPONENTS. PRIOR TO USING OR DISTRIBUTING ANY PRODUCTS THAT INCLUDE NATIONAL COMPONENTS, BUYERS SHOULD PROVIDE ADEQUATE DESIGN, TESTING AND OPERATING SAFEGUARDS. EXCEPT AS PROVIDED IN NATIONAL’S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, NATIONAL ASSUMES NO LIABILITY WHATSOEVER, AND NATIONAL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY RELATING TO THE SALE AND/OR USE OF NATIONAL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS PRIOR WRITTEN APPROVAL OF THE CHIEF EXECUTIVE OFFICER AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: Life support devices or systems are devices which (a) are intended for surgical implant into the body, or (b) support or sustain life and whose failure to perform when properly used in accordance with instructions for use provided in the labeling can be reasonably expected to result in a significant injury to the user. A critical component is any component in a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system or to affect its safety or effectiveness. National Semiconductor and the National Semiconductor logo are trademarks or registered trademarks of National Semiconductor Corporation. All other brand or product names may be trademarks or registered trademarks of their respective holders. Copyright © 2006 National Semiconductor Corporation. For the most current product information visit us at www.national.com. LM5100A/B/C, LM5101A/B/C 3A, 2A and 1A High Voltage High-Side and Low-Side Gate Drivers National Semiconductor Americas Customer Support Center Email: new.feedback@nsc.com Tel: 1-800-272-9959 www.national.com National Semiconductor Europe Customer Support Center Fax: +49 (0) 180-530 85 86 Email: europe.support@nsc.com Deutsch Tel: +49 (0) 69 9508 6208 English Tel: +44 (0) 870 24 0 2171 Français Tel: +33 (0) 1 41 91 8790 National Semiconductor Asia Pacific Customer Support Center Email: ap.support@nsc.com National Semiconductor Japan Customer Support Center Fax: 81-3-5639-7507 Email: jpn.feedback@nsc.com Tel: 81-3-5639-7560