LM5110-2MX

LM5110 Dual 5A Compound Gate Driver with Negative Output Voltage Capability October 2003 LM5110 Dual 5A Compound Gate Driver with Negative Output Voltage Capability General Description The LM5110 Dual Gate Driver replaces industry standard gate drivers with improved peak output current and efficiency. Each “compound” output driver stage includes MOS and bipolar transistors operating in parallel that together sink more than 5A peak from capacitive loads. Combining the unique characteristics of MOS and bipolar devices reduces drive current variation with voltage and temperature. Separate input and output ground pins provide Negative Drive Capability allowing the user to drive MOSFET gates with positive and negative VGS voltages. The gate driver control inputs are referenced to a dedicated input ground (IN_REF). The gate driver outputs swing from VCC to the output ground VEE which can be negative with respect to IN_REF. The ability to hold MOSFET gates off with a negative VGS voltage reduces losses when driving low threshold voltage MOSFETs often used as synchronous rectifiers. When driving with conventional positive only gate voltage, the IN_REF and VEE pins are connected together and referenced to a common ground. Under-voltage lockout protection and a shutdown input pin are also provided. The drivers can be operated in parallel with inputs and outputs connected to double the drive current capability. This device is available in the SOIC-8 and the thermally-enhanced LLP-10 packages. n 5A sink/3A source current capability n Two channels can be connected in parallel to double the drive current n Independent inputs (TTL compatible) n Fast propagation times (25 ns typical) n Fast rise and fall times (14 ns/12 ns rise/fall with 2 nF load) n Dedicated input ground pin (IN_REF) for split supply or single supply operation n Outputs swing from VCC to VEE which can be negative relative to input ground n Available in dual non-inverting, dual inverting and combination configurations n Shutdown input provides low power mode n Supply rail under-voltage lockout protection n Pin-out compatible with industry standard gate drivers Typical Applications n n n n Synchronous Rectifier Gate Drivers Switch-mode Power Supply Gate Driver Solenoid and Motor Drivers Power Level Shifter Features n Independently drives two N-Channel MOSFETs n Compound CMOS and bipolar outputs reduce output current variation Package n SOIC-8 n LLP-10 (4 mm x 4 mm) Ordering Information Order Number LM5110-1/2/3 M LM5110-1/2/3 MX LM5110-1/2/3 SD LM5110-1/2/3 SDX Package Type SOIC-8 SOIC-8 LLP-10 LLP-10 NSC Package Drawing M08A M08A SDC10A SDC10A Supplied As Shipped in anti-static units 2500 shipped in Tape & Reel 1000 shipped in Tape & Reel 4500 shipped in Tape & Reel © 2003 National Semiconductor Corporation DS200792 www.national.com LM5110 Pin Configurations 20079201 20079202 SOIC-8 LLP-10 NC - NOT CONNECTED Block Diagram 20079203 Block Diagram of LM5110 www.national.com 2 LM5110 Typical Application 20079204 Simplified Power Converter Using Synchronous Rectifiers with Negative Off Gate Voltage 3 www.national.com LM5110 Pin Description Pin Description SOIC-8 1 LLP-10 1 IN_REF Ground reference for control inputs Connect to VEE for standard positive only output voltage swing. Connect to system logic ground reference for positive and negative output voltage swing. TTL compatible thresholds. Connect to either power ground or a negative gate drive supply. TTL compatible thresholds. Capable of sourcing 3A and sinking 5A. Voltage swing of this output is from VCC to VEE. Locally decouple to VEE and IN_REF. Capable of sourcing 3A and sinking 5A. Voltage swing of this output is from VCC to VEE . Pull below 1.5V to activate low power shutdown mode. Name Description Application Information 2 3 4 5 6 7 8 2 3 4 7 8 9 10 IN_A VEE IN_B OUT_B VCC OUT_A. nSHDN ‘A’ side control input Power ground of the driver outputs ‘B’ side control input Output for the ‘B’ side driver. Positive supply Output for the ‘A’ side driver. Shutdown input pin Note: Pins 5 and 6 are No Connect for LLP-10 package. Configuration Table Part Number LM5110-1M LM5110-2M LM5110-3M LM5110-1SD LM5110-2SD LM5110-3SD “A” Output Configuration Non-Inverting Inverting Inverting Non-Inverting Inverting Inverting “B” Output Configuration Non-Inverting Inverting Non-Inverting Non-Inverting Inverting Non-Inverting SOIC- 8 SOIC- 8 SOIC- 8 LLP-10 LLP-10 LLP-10 Package www.national.com 4 LM5110 Absolute Maximum Ratings (Note 1) IN_REF to VEE Storage Temperature Range, (TSTG) Maximum Junction Temperature, (TJ(max)) Operating Junction Temperature ESD Rating −0.3V to 5V −55˚C to +150˚C +150˚C +125˚C 2kV If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. VCC to VEE VCC to IN_REF IN to IN_REF, nSHDN to IN_REF −0.3V to 15V −0.3V to 15V −0.3V to 15V Electrical Characteristics TJ = −40˚C to +125˚C, VCC = 12V, VEE = IN_REF = 0V, nSHDN = VCC, No Load on OUT_A or OUT_B, unless otherwise specified. Symbol VCCR VCCH ICC Parameter VCC Operating Range VCC Under Voltage Lockout (rising) VCC Under Voltage Lockout Hysteresis VCC Supply Current (ICC) IN_A = IN_B = 0V (5110-1) IN_A = IN_B = VCC (5110-2) IN_A = VCC, IN_B = 0V (5110-3) ICCSD VIH VIL HYS IIL IIH VCC Shutdown Current (ICC) Logic High Logic Low Input Hysteresis Input Current Low Input Current High IN_A=IN_B=VCC (5110-1-2-3) IN_A=IN_B=VCC (5110-1) IN_A=IN_B=VCC (5110-2) IN_A=VCC (5110-3) IN_B=VCC (5110-3) SHUTDOWN INPUT ISD VSDR VSDH ROH ROL ISource ISink Pull-up Current Shutdown Threshold Shutdown Hysteresis Output Resistance High Output Resistance Low Peak Source Current Peak Sink Current IOUT = −10 mA IOUT = + 10 mA OUTA/OUTB = VCC/2, 200 ns Pulsed Current OUTA/OUTB = VCC/2, 200 ns Pulsed Current nSHDN = 0 V nSHDN rising 0.8 −18 1.5 165 30 1.4 3 5 50 2.5 −25 2.2 µA V mV Ω Ω A A −1 10 −1 -1 10 0.8 nSHDN = 0V CONTROL INPUTS 1.75 1.35 400 0.1 18 0.1 0.1 18 1 25 1 1 25 µA 2.2 V V mV Conditions VCC−IN_REF and VCC−VEE VCC−IN_REF Min 3.5 2.3 2.9 230 1 1 1 18 2 2 2 25 µA mA Typ Max 14 3.5 Units V V mV OUTPUT DRIVERS 5 www.national.com LM5110 Electrical Characteristics Symbol td1 td2 tr tf Parameter (Continued) TJ = −40˚C to +125˚C, VCC = 12V, VEE = IN_REF = 0V, nSHDN = VCC, No Load on OUT_A or OUT_B, unless otherwise specified. Conditions CLOAD = 2 nF, see Figure 1 Min Typ Max Units SWITCHING CHARACTERISTICS Propagation Delay Time Low to High, IN rising (IN to OUT) 25 25 14 12 40 40 25 25 ns ns ns ns Propagation Delay Time High to CLOAD = 2 nF, see Figure 1 Low, IN falling (IN to OUT) Rise Time Fall Time CLOAD = 2.0 nF, see Figure 1 CLOAD = 2 nF, see Figure 1 TJ = 150˚C LATCHUP PROTECTION AEC - Q100, Method 004 500 mA Note 1: Absolute Maximum Ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions under which operation of the device is intended to be functional. For guaranteed specifications and test conditions, see the Electrical Characteristics. Timing Waveforms 20079205 20079206 (a) FIGURE 1. (a) Inverting, (b) Non-Inverting (b) www.national.com 6 LM5110 Typical Performance Characteristics Supply Current vs Frequency Supply Current vs Capacitive Load 20079210 20079211 Rise and Fall Time vs Supply Voltage Rise and Fall Time vs Temperature 20079212 20079213 Rise and Fall Time vs Capacitive Load Delay Time vs Supply Voltage 20079214 20079215 7 www.national.com LM5110 Typical Performance Characteristics Delay Time vs Temperature (Continued) RDSON vs Supply Voltage 20079216 20079217 UVLO Thresholds and Hysteresis vs Temperature 20079218 Detailed Operating Description LM5110 dual gate driver consists of two independent and identical driver channels with TTL compatible logic inputs and high current totem-pole outputs that source or sink current to drive MOSFET gates. The driver output consist of a compound structure with MOS and bipolar transistor operating in parallel to optimize current capability over a wide output voltage and operating temperature range. The bipolar device provides high peak current at the critical threshold region of the MOSFET VGS while the MOS devices provide rail-to-rail output swing. The totem pole output drives the MOSFET gate between the gate drive supply voltage VCC and the power ground potential at the VEE pin. The control inputs of the drivers are high impedance CMOS buffers with TTL compatible threshold voltages. The negative supply of the input buffer is connected to the input ground pin IN_REF. An internal level shifting circuit connects the logic input buffers to the totem pole output drivers. The level shift circuit and separate input/output ground pins provide the option of single supply or split supply configurations. When driving MOSFET gates from a single positive supply, the IN_REF and VEE pins are both connected to the power www.national.com 8 ground. The LM5110 pinout was designed for compatibility with industry standard gate drivers in single supply gate driver applications. Pin 1 (IN_REF) on the LM5110 is a no-connect on standard driver IC’s. Connecting pin 1 to pin 3 (VEE) on the printed circuit board accommodates the pin-out of both the LM5110 and competitive drivers. The isolated input/output grounds provide the capability to drive the MOSFET to a negative VGS voltage for a more robust and reliable off state. In split supply configuration, the IN_REF pin is connected to the ground of the controller which drives the LM5110 inputs. The VEE pin is connected to a negative bias supply that can range from the IN-REF as much as 14V below the VCC gate drive supply. The maximum recommended voltage difference between VCC and IN_REF or between VCC and VEE is 14V. The minimum voltage difference between VCC and IN_REF is 3.5V. Enhancement mode MOSFETs do not inherently require a negative bias on the gate to turn off the FET. However, certain applications may benefit from the capability of negative VGS voltage during turn-off including: 1. when the gate voltages cannot be held safely below the threshold voltage due to transients or coupling in the printed circuit board. LM5110 Detailed Operating Description (Continued) 2. 2. 3. when driving low threshold MOSFETs at high junction temperatures when high switching speeds produce capacitive gatedrain current that lifts the internal gate potential of the MOSFET high peak currents being drawn from VCC during turn-on of the MOSFET. Proper grounding is crucial. The drivers need a very low impedance path for current return to ground avoiding inductive loops. The two paths for returning current to ground are a) between LM5110 IN-REF pin and the ground of the circuit that controls the driver inputs, b) between LM5110 VEE pin and the source of the power MOSFET being driven. All these paths should be as short as possible to reduce inductance and be as wide as possible to reduce resistance. All these ground paths should be kept distinctly separate to avoid coupling between the high current output paths and the logic signals that drive the LM5110. A good method is to dedicate one copper plane in a multi-layered PCB to provide a common ground surface. 3. With the rise and fall times in the range of 10 ns to 30 ns, care is required to minimize the lengths of current carrying conductors to reduce their inductance and EMI from the high di/dt transients generated by the LM5110. 4. The LM5110 SOIC footprint is compatible with other industry standard drivers. Simply connect IN_REF pin of the LM5110 to VEE (pin 1 to pin 3) to operate the LM5110 in a standard single supply configuration. 5. If either channel is not being used, the respective input pin (IN_A or IN_B) should be connected to either IN_REF or VCC to avoid spurious output signals. If the shutdown feature is not used, the nSHDN pin should be connected to VCC to avoid erratic behavior that would result if system noise were coupled into a floating ’nSHDN’ pin. The two driver channels of the LM5110 are designed as identical cells. Transistor matching inherent to integrated circuit manufacturing ensures that the ac and dc performance of the channels are nearly identical. Closely matched propagation delays allow the dual driver to be operated as a single driver if inputs and output pins are connected. The drive current capability in parallel operation is 2X the drive of either channel. Small differences in switching speed between the driver channels will produce a transient current (shoot-through) in the output stage when two output pins are connected to drive a single load. The efficiency loss for parallel operation has been characterized at various loads, supply voltages and operating frequencies. The power dissipation in the LM5110 increases by less than 1% relative to the dual driver configuration when operated as a single driver with inputs and outputs connected. An Under-voltage lockout (UVLO) circuit is included in the LM5110, which senses the voltage difference between VCC and the input ground pin, IN_REF. When the VCC to IN_REF voltage difference falls below 2.7V both driver channels are disabled. The driver will resume normal operation when the VCC to IN_REF differential voltage exceeds approximately 2.9V. UVLO hysteresis prevents chattering during brown-out conditions. The Shutdown pin (nSHDN) is a TTL compatible logic input provided to enable/disable both driver channels. When nSHDN is in the logic low state, the LM5110 is switched to a low power standby mode with total supply current less than 25 µA. This function can be effectively used for start-up, thermal overload, or short circuit fault protection. It is recommended that this pin be connected to VCC when the shutdown function is not being used. The shutdown pin has an internal 18µA current source pull-up to VCC. The input pins of non-inverting drivers have an internal 18µA current source pull-down to IN-REF. The input pins of inverting driver channels have neither pull-up nor pull-down current sources. The LM5110 is available in dual non-inverting (-1), dual inverting (-2) and the combination inverting plus noninverting (-3) configurations. All three configurations are offered in the SOIC-8 and LLP-10 plastic packages. Thermal Performance INTRODUCTION The primary goal of thermal management is to maintain the integrated circuit (IC) junction temperature (TJ) below a specified maximum operating temperature to ensure reliability. It is essential to estimate the maximum TJ of IC components in worst case operating conditions. The junction temperature is estimated based on the power dissipated in the IC and the junction to ambient thermal resistance θJA for the IC package in the application board and environment. The θJA is not a given constant for the package and depends on the printed circuit board design and the operating environment. DRIVE POWER REQUIREMENT CALCULATIONS IN LM5110 The LM5110 dual low side MOSFET driver is capable of sourcing/sinking 3A/5A peak currents for short intervals to drive a MOSFET without exceeding package power dissipation limits. High peak currents are required to switch the MOSFET gate very quickly for operation at high frequencies. Layout Considerations Attention must be given to board layout when using LM5110. Some important considerations include: 1. A Low ESR/ESL capacitor must be connected close to the IC and between the VCC and VEE pins to support 9 www.national.com LM5110 Thermal Performance (Continued) 20079207 FIGURE 2. The schematic above shows a conceptual diagram of the LM5110 output and MOSFET load. Q1 and Q2 are the switches within the gate driver. RG is the gate resistance of the external MOSFET, and CIN is the equivalent gate capacitance of the MOSFET. The gate resistance Rg is usually very small and losses in it can be neglected. The equivalent gate capacitance is a difficult parameter to measure since it is the combination of CGS (gate to source capacitance) and CGD (gate to drain capacitance). Both of these MOSFET capacitances are not constants and vary with the gate and drain voltage. The better way of quantifying gate capacitance is the total gate charge QG in coloumbs. QG combines the charge required by CGS and CGD for a given gate drive voltage VGATE. Assuming negligible gate resistance, the total power dissipated in the MOSFET driver due to gate charge is approximated by PDRIVER = VGATE x QG x FSW Where FSW = switching frequency of the MOSFET. As an example, consider the MOSFET MTD6N15 whose gate charge specified as 30 nC for VGATE = 12V. The power dissipation in the driver due to charging and discharging of MOSFET gate capacitances at switching frequency of 300 kHz and VGATE of 12V is equal to PDRIVER = 12V x 30 nC x 300 kHz = 0.108W. If both channels of the LM5110 are operating at equal frequency with equivalent loads, the total losses will be twice as this value which is 0.216W. In addition to the above gate charge power dissipation, transient power is dissipated in the driver during output transitions. When either output of the LM5110 changes state, current will flow from VCC to VEE for a very brief interval of time through the output totem-pole N and P channel MOSFETs. The final component of power dissipation in the driver is the power associated with the quiescent bias current consumed by the driver input stage and Under-voltage lockout sections. Characterization of the LM5110 provides accurate estimates of the transient and quiescent power dissipation components. At 300 kHz switching frequency and 30 nC load used in the example, the transient power will be 8 mW. The 1 mA nominal quiescent current and 12V VGATE supply produce a 12 mW typical quiescent power. Therefore the total power dissipation PD = 0.216 + 0.008 + 0.012 = 0.236W. We know that the junction temperature is given by TJ = PD x θJA + TA Or the rise in temperature is given by TRISE = TJ − TA = PD x θJA For SOIC-8 package θJA is estimated as 170˚C/W for the conditions of natural convection. Therefore TRISE is equal to TRISE = 0.236 x 170 = 40.1˚C For LLP-10 package, the integrated circuit die is attached to leadframe die pad which is soldered directly to the printed circuit board. This substantially decreases the junction to ambient thermal resistance (θJA). θJA as low as 40˚C/W is achievable with the LLP10 package. The resulting TRISE for the dual driver example above is thereby reduced to just 9.5 degrees. CONTINUOUS CURRENT RATING OF LM5110 The LM5110 can deliver pulsed source/sink currents of 3A and 5A to capacitive loads. In applications requiring continuous load current (resistive or inductive loads), package power dissipation, limits the LM5110 current capability far below the 5A sink/3A source capability. Rated continuous current can be estimated both when sourcing current to or sinking current from the load. For example when sinking, the maximum sink current can be calculated as where RDS(on) is the on resistance of lower MOSFET in the output stage of LM5110. Consider TJ(max) of 125˚C and θJA of 170˚C/W for an SO-8 package under the condition of natural convection and no air flow. If the ambient temperature (TA) is 60˚C, and the RD- www.national.com 10 LM5110 Thermal Performance (Continued) S(on) of the LM5110 output at TJ(max) is 2.5Ω, this equation yields ISINK(max) of 391mA which is much smaller than 5A peak pulsed currents. Similarly, the maximum continuous source current can be calculated as where VDIODE is the voltage drop across hybrid output stage which varies over temperature and can be assumed to be about 1.1V at TJ(max) of 125˚C. Assuming the same parameters as above, this equation yields ISOURCE(max) of 347mA. 11 www.national.com LM5110 Physical Dimensions unless otherwise noted inches (millimeters) NOTES: UNLESS OTHERWISE SPECIFIED 1. STANDARD LEAD FINISH TO BE 200 MICROINCHES/5.08 MICROMETERS MINIMUM LEAD/TIN(SOLDER) ON COPPER. 2. DIMENSION DOES NOT INCLUDE MOLD FLASH. 3. REFERENCE JEDEC REGISTRATION MS-012, VARIATION AA, DATED MAY 1990. 8-Lead SOIC Package NS Package Number M08A www.national.com 12 LM5110 Dual 5A Compound Gate Driver with Negative Output Voltage Capability Physical Dimensions inches (millimeters) unless otherwise noted (Continued) NOTES: UNLESS OTHERWISE SPECIFIED 1. FOR SOLDER THICKNESS AND COMPOSITION, SEE “SOLDER INFORMATION” IN THE PACKAGING SECTION OF THE NATIONAL SEMICONDUCTOR WEB PAGE (www.national.com). 2. MAXIMUM ALLOWABLE METAL BURR ON LEAD TIPS AT THE PACKAGE EDGES IS 76 MICRONS. 3. NO JEDEC REGISTRATION AS OF MAY 2003. 10-Lead LLP Package NS Package Number SDC10A LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. 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