LM94

LM94 TruTherm™ Hardware Monitor with PI Loop Fan Control for Server Management April 2006 LM94 TruTherm™ Hardware Monitor with PI Loop Fan Control for Server Management 1.0 General Description The LM94 hardware monitor has a two wire digital interface compatible with SMBus 2.0. Using a Σ∆ ADC, the LM94 measures the temperature of four remote diode connected transistors as well as its own die and 16 power supply voltages. The LM94 has new TruTherm technology that supports precision thermal diode measurements of processors on sub-micron processes. To set fan speed, the LM94 has two PWM outputs that are each controlled by up to six temperature zones. The fancontrol algorithm can be based on a lookup table, PI (proportional/integral) control loop, or a combination of both. The LM94 includes digital filters that can be invoked to smooth temperature readings for better control of fan speed such that acoustical noise is minimized. The LM94 has four tachometer inputs to measure fan speed. Limit and status registers for all measured values are included. The LM94 builds upon the functionality of previous motherboard server management ASICs, such as the LM93. It also adds measurement and control support for dynamic Vccp monitoring for VRD10/11 and PROCHOT. It is designed to monitor a dual processor Xeon class motherboard with a minimum of external components. n 2 PWM fan speed control outputs n 4 fan tachometer inputs n Dual processor thermal throttling (PROCHOT) monitoring n Dual dynamic VID monitoring (6/7 VIDs per processor) supports VRD10.2/11 n 8 general purpose I/Os: — 4 can be configured as fan tachometer inputs — 2 can be configured to connect to processor THERMTRIP — 2 are standard GPIOs that could be used to monitor IERR signal n 2 general purpose inputs that can be used to monitor the 7th VID signal for VRD11 n Limit register comparisons of all monitored values n 2-wire serial digital interface, SMBus 2.0 compliant — Supports byte/block read and write — Selectable slave address (tri-level pin selects 1 of 3 possible addresses) — ALERT output supports interrupt or comparator modes n 2.5V reference voltage output n 56-pin TSSOP package n XOR-tree test mode 2.0 Features n n n n n n n n n n n n 8-bit Σ∆ ADC Monitors 16 power supplies Monitors 4 remote thermal diodes and 2 LM60 New TruTherm technology support for precision thermal diode measurements Internal ambient temperature sensing Programmable autonomous fan control based on temperature readings with fan boost support Fan boost support on tachometer limit error event Fan control based on 13-step lookup table or PI Control Loop or combination of both PI fan control loop supports Tcontrol Temperature reading digital filters 0.5˚C digital temperature sensor resolution 0.0625˚C filtered temperature resolution for fan control 3.0 Key Specifications Voltage Measurement Accuracy Temperature Resolution Temperature Sensor Accuracy Temperature Range: — LM94 Operational — Remote Temp Accuracy n Power Supply Voltage n Power Supply Current n n n n ± 2% FS (max) 9-bits, 0.5˚C ± 2.5 ˚C (max) 0˚C to +85˚C 0˚C to +125˚C +3.0V to +3.6V 1.6 mA 4.0 Applications n Servers n Workstations n Multi-processor based equipment 5.0 Ordering Information Order Number NS Package Number Transport media LM94CIMT LM94CIMTX MTD56 MTD56 34 units in rail 1000 units in tape-and-reel I2C is a registered trademark of the Philips Corporation. © 2006 National Semiconductor Corporation DS201124 www.national.com LM94 6.0 Block Diagram single chip ASIC solution. The block diagram of LM94 hardware is illustrated below. The hardware implementation is a 20112401 www.national.com 2 LM94 7.0 Application Baseboard management of a dual processor server. Two LM94s may be required to manage a quad processor board. The system diagram below shows a dual processor server 2 Way Xeon Server Management 20112405 3 www.national.com LM94 8.0 Connection Diagram 56 Pin TSSOP 20112402 NS Package MTD56 Top View NS Order Numbers: LM94CIMT (34 units per rail), or LM94CIMTX (1000 units per tape-and-reel) www.national.com 4 LM94 9.0 Pin Descriptions Symbol GPIO_0/TACH1 GPIO_1/TACH2 GPIO_2/TACH3 GPIO_3/TACH4 GPIO_4 / P1_THERMTRIP GPIO_5 / P2_THERMTRIP GPIO_6 Pin # 1 2 3 4 5 Type Digital I/O (Open-Drain) Digital I/O (Open-Drain) Digital I/O (Open-Drain) Digital I/O (Open-Drain) Digital I/O (Open-Drain) Digital I/O (Open-Drain) Digital I/O (Open-Drain) Digital I/O (Open-Drain) Digital Input Digital Input Digital Input Function Can be configured as fan tach input or a general purpose open-drain digital I/O. Can be configured as fan tach input or a general purpose open-drain digital I/O. Can be configured as fan tach input or a general purpose open-drain digital I/O. Can be configured as fan tach input or a general purpose open-drain digital I/O.. A general purpose open-drain digital I/O. Can be configured to monitor a CPU’s THERMTRIP signal to mask other errors. Supports TTL input logic levels and AGTL compatible input logic levels. A general purpose open-drain digital I/O. Can be configured to monitor a CPU’s THERMTRIP signal to mask other errors. Supports TTL input logic levels and AGTL compatible input logic levels. Can be used to detect the state of CPU1 IERR or a general purpose open-drain digital I/O. Supports TTL input logic levels and AGTL compatible input logic levels. Can be used to detect the state of CPU2 IERR or a general purpose open-drain digital I/O. Supports TTL input logic levels and AGTL compatible input logic levels. CPU1 voltage regulator HOT. Supports TTL input logic levels and AGTL compatible input logic levels. CPU2 voltage regulator HOT. Supports TTL input logic levels and AGTL compatible input logic levels. CPU2 VID6 input. Could also be used as a general purpose input to trigger an error event. Supports TTL input logic levels and AGTL compatible input logic levels. CPU1 VID6 input. Could also be used as a general purpose input to trigger an error event. Supports TTL input logic levels and AGTL compatible input logic levels. Bidirectional System Management Bus Data. Output configured as 5V tolerant open-drain. SMBus 2.0 compliant. System Management Bus Clock. Driven by an open-drain output, and is 5V tolerant. SMBus 2.0 Compliant. Open-drain ALERT output used in an interrupt driven system to signal that an error event has occurred. Masked error events do not activate the ALERT output. When in XOR tree test mode, functions as XOR Tree output. Open-drain reset output when power is first applied to the LM94. Used as a reset for devices powered by 3.3V stand-by. After reset, this pin becomes a reset input. If this pin is not used, connection to an external resistive pull-up is required to prevent LM94 malfunction. Analog Ground. Digital ground and analog ground need to be tied together at the chip then both taken to a low noise system ground. A voltage difference between analog and digital ground may cause erroneous results. 2.5V used for external ADC reference, or as a VREF reference voltage 6 7 GPIO_7 8 VRD1_HOT VRD2_HOT P2_VID6/GPI8 9 10 11 P1_VID6/GPI9 12 Digital Input SMBDAT SMBCLK ALERT/XtestOut 13 14 15 Digital I/O (Open-Drain) Digital Input Digital Output (Open-Drain) RESET 16 Digital I/O (Open-Drain) AGND 17 GROUND Input VREF 18 Analog Output 5 www.national.com LM94 9.0 Pin Descriptions Symbol REMOTE1− Pin # 19 (Continued) Type Remote Thermal Diode_1- Input (CPU 1 THERMDC) Function This is the negative input (current sink) from both of the CPU1 thermal diodes. Connected to THERMDC pin of Pentium processor or the emitter of a diode connected MMBT3904 NPN transistor. Serves as the negative input into the A/D for thermal diode voltage measurements. A 100 pF capacitor is optional and can be connected between REMOTE1− and REMOTE1+. This is a positive connection to the first CPU1 thermal diode. Serves as the positive input into the A/D for thermal diode voltage measurements. It also serves as a current source output that forward biases the thermal diode. Connected to THERMDA pin of Pentium processor or the base of a diode connected MMBT3904 NPN transistor. A 100 pF capacitor is optional and can be connected between REMOTE1− and each REMOTE1+. This is the negative input (current sink) from both of the CPU2 thermal diodes. Connected to THERMDC pins of Pentium processor or the emitter of a diode connected MMBT3904 NPN transistor. Serves as the negative input into the A/D for thermal diode voltage measurements. A 100 pF capacitor is optional and can be connected between REMOTE2− and each REMOTE2+. This is a positive connection to the first CPU2 thermal diode. Serves as the positive input into the A/D for thermal diode voltage measurements. It also serves as a current source output that forward biases the thermal diode. Connected to THERMDA pin of Pentium processor or the base of a diode connected MMBT3904 NPN transistor. A 100 pF capacitor is optional and can be connected between REMOTE2− and REMOTE2+. Analog Input for +12V Rail 1 monitoring, for CPU1 voltage regulator. External attenuation resistors required such that 12V is attenuated to 0.927V for nominal 3⁄4 scale reading. This pin may also serve as the second positive thermal diode input for CPU1. Analog Input for +12V Rail 2 monitoring, for CPU2 voltage regulator. External attenuation resistors required such that 12V is attenuated to 0.927V for nominal 3⁄4 scale reading. This pin may also serve as the second positive thermal diode input for CPU2. Analog Input for +12V Rail 3, for Memory/3GIO slots. External attenuation resistors required such that 12V is attenuated to 0.927V for nominal 3⁄4 scale reading. Analog input for 1.2V monitoring, nominal 3⁄4 scale reading Analog input for 1.5V monitoring, nominal 3⁄4 scale reading Analog input for 1.5V monitoring, nominal 3⁄4 scale reading Analog input for +Vccp (processor voltage) monitoring. Analog input for +Vccp (processor voltage) monitoring. Analog input for +3.3V monitoring, nominal 3⁄4 scale reading Analog input for +5V monitoring silver box supply monitoring, nominal 3⁄4 scale reading REMOTE1a+ 20 Remote Thermal Diode_1+ I/O (CPU1 THERMDA1) REMOTE2− 21 Remote Thermal Diode_2 - Input (CPU2 THERMDC) REMOTE2a+ 22 Remote Thermal Diode_2 + I/O (CPU2 THERMDA1) AD_IN1/REMOTE1b+ 23 Analog Input (+12V1 or CPU1 THERMDA2) Analog Input (+12V2 or CPU2 THERMDA2) Analog Input (+12V3) AD_IN2/REMOTE2b+ 24 AD_IN3 25 AD_IN4 AD_IN5 AD_IN6 AD_IN7 (P1_Vccp) AD_IN8 (P2_Vccp) AD_IN9 AD_IN10 26 27 28 29 30 31 32 Analog Input (FSB_Vtt) Analog Input (3GIO / PXH / MCH_Core) Analog Input (ICH_Core) Analog Input (CPU1_Vccp) Analog Input (CPU2_Vccp) Analog Input (+3.3V) Analog Input (+5V) www.national.com 6 LM94 9.0 Pin Descriptions Symbol AD_IN11 Pin # 33 (Continued) Type Analog Input (SCSI_Core) Function Analog input for +2.5V monitoring, nominal 3⁄4 scale reading. This pin may also be used to monitor an analog temperature sensor such as the LM60, since readings from this input can be routed to the fan control logic. Analog input for +1.969V monitoring, nominal 3⁄4 scale reading. Analog input for +0.984V monitoring, nominal 3⁄4 scale reading. Analog input for +0.984V S/B monitoring, nominal 3⁄4 scale reading. Analog input for -12V monitoring. External resistors required to scale to positive level. Full scale reading at 1.236V, , nominal 3⁄4 scale reading. This pin may also be used to monitor an analog temperature sensor such as the LM60, since readings from this input can be routed to the fan control logic. This input selects the lower two bits of the LM94 SMBus slave address. VDD power input for LM94. Generally this is connected to +3.3V standby power. The LM94 can be powered by +3.3V if monitoring in low power states is not required, but power should be applied to this input before any other pins. This pin also serves as the analog input to monitor the 3.3V stand-by (SB) voltage. It is necessary to bypass this pin with a 0.1 µF in parallel with 100 pF. A bulk capacitance of 10 µF should be in the near vicinity. The 100 pF should be closest to the power pin. Digital Ground. Digital ground and analog ground need to be tied together at the chip then both taken to a low noise system ground. A voltage difference between analog and digital ground may cause erroneous results. Fan control output 1. Fan control output 2 Voltage Identification signal from the processor. Supports TTL input logic levels and AGTL compatible input logic levels. Voltage Identification signal from the processor. Supports TTL input logic levels and AGTL compatible input logic levels. Voltage Identification signal from the processor. Supports TTL input logic levels and AGTL compatible input logic levels. Voltage Identification signal from the processor. Supports TTL input logic levels and AGTL compatible input logic levels. Voltage Identification signal from the processor. Supports TTL input logic levels and AGTL compatible input logic levels. Voltage Identification signal from the processor. Supports TTL input logic levels and AGTL compatible input logic levels. Connected to CPU1 PROCHOT (processor hot) signal through a bidirectional level shifter. Supports TTL input logic levels and AGTL compatible input logic levels. Connected to CPU2 PROCHOT (processor hot) signal through a bidirectional level shifter. Supports TTL input logic levels and AGTL compatible input logic levels. AD_IN12 AD_IN13 AD_IN14 AD_IN15 34 35 36 37 Analog Input (Mem_Core) Analog Input (Mem_Vtt) Analog Input (Gbit_Core) Analog Input (-12V) Address Select 3.3V SB (AD_IN16) 38 39 3 level analog input POWER (VDD) +3.3V standby power GND 40 GROUND PWM1 PWM2 P1_VID0/P1_VID7 P1_VID1 P1_VID2 P1_VID3 P1_VID4 P1_VID5 P1_PROCHOT 41 42 43 44 45 46 47 48 49 Digital Output (Open-Drain) Digital Output (Open-Drain) Digital Input Digital Input Digital Input Digital Input Digital Input Digital Input Digital I/O (Open-Drain) Digital I/O (Open-Drain) P2_PROCHOT 50 7 www.national.com LM94 9.0 Pin Descriptions Symbol P2_VID0/P2_VID7 P2_VID1 P2_VID2 P2_VID3 P2_VID4 P2_VID5 Pin # 51 52 53 54 55 56 (Continued) Type Digital Input Digital Input Digital Input Digital Input Digital Input Digital Input Function Voltage Identification signal from the processor. Supports TTL input logic levels and AGTL compatible input logic levels. Voltage Identification signal from the processor. Supports TTL input logic levels and AGTL compatible input logic levels. Voltage Identification signal from the processor. Supports TTL input logic levels and AGTL compatible input logic levels. Voltage Identification signal from the processor. Supports TTL input logic levels and AGTL compatible input logic levels. Voltage Identification signal from the processor. Supports TTL input logic levels and AGTL compatible input logic levels. Voltage Identification signal from the processor. Supports TTL input logic levels and AGTL compatible input logic levels. The over-score indicates the signal is active low (“Not”). 10.0 Recommended Implementation 20112406 Recommended implementation without thermal diode connections www.national.com 8 LM94 10.0 Recommended Implementation (Continued) 20112407 Note: 100 pF cap across each thermal diode is optional and should be placed close to the LM94, if used. The maximum capacitance between thermal diode pins is 300 pF. Thermal diode recommended implementation 11.0 Functional Description The LM94 provides 16 channels of voltage monitoring, 4 remote thermal diode monitors, an internal/local ambient temperature sensor, 2 PROCHOT monitors, 4 fan tachometers, 8 GPIOs, THERMTRIP monitor for masking error events, 2 sets of 7 VID inputs, an ALERT output and all the associated limit registers on a single chip, and communicates to the rest of the baseboard over the System Management Bus (SMBus). The LM94 also provides 2 PWM outputs and associated fan control logic for controlling the speed of system fans. There are two sets of fan control logic, a lookup table and a PI (proportional/integral) loop controller. The lookup table and PI controller are interactive, such that the fans run at the fastest required speed. Upon a temperature or fan tach error event, the PWM outputs may be programmed such that they automatically boost to 100% duty cycle. A timer is included that sets the minimum time that the fans are in the boost condition when activated by a fan tach error. The LM94 incorporates National Semiconductor’s TruTherm technology for precision “Remote Diode” readings of processors on 90nm process geometry or smaller. Readings from the external thermal diodes and the internal temperature sensor are made available as an 9-bit two’s-complement digital value with the LSb representing 0.5˚C. Filtered temperature readings are available as a 12-bit two’scomplement digital value with the LSb representing 0.0625˚C. All but 4 of the analog inputs include internal scaling resistors. External scaling resistors are required for measuring ± 12V. The inputs are converted to 8-bit digital values such that a nominal voltage appears at 3⁄4 scale for positive voltages and 1⁄4 scale for negative voltages. The analog inputs are intended to be connected to both baseboard resident VRDs and to standard voltage rails supplied by a SSI compliant power supply. The LM94 has logic that ties a set of dynamically moving VID inputs to their associated Vccp analog input for real time window comparison fault determination. Voltage mapping for VRD10, VRD10 extended and VRD11are supported by the LM94. When VRD10 mode is selected GPI8 and GPI9 can be used to detect external error flags whose state is be reflected in the status registers. Error events are captured in two sets of mirrored status registers (BMC Error Status Registers and Host Status Registers) allowing two controllers access to the status information without any interference. The LM94’s ALERT output supports interrupt mode or comparator mode of operation. The comparator mode is only functional for thermal monitoring. The LM94 provides a number of internal registers, which are detailed in the register section of this document. 12.0 Please contact your local sales office for complete LM94 applications information. 13.0 Registers 13.1 REGISTER WARNINGS In most cases, reserved registers and register bits return zero when read. This should not be relied upon, since reserved registers can be used for future expansion of the LM94 functions. Some registers have “N/D” for their default value. This means that the power-up default of the register is not defined. In the case of value registers, care should be taken to ensure that software does not read a value register until the associated measurement function has acquired a measurement. This applies to temperatures, voltages, fan RPM, and PROCHOT monitoring. 9 www.national.com LM94 13.0 Registers (Continued) 13.2 REGISTER SUMMARY TABLE Register Key Term N/D N/A R R/W RWC Lock x XOR Test SMBus Test Reserved “REMOTE DIODE” MODE SELECT x Transistor Mode Select 05h Selects Diode Mode (default) or Transistor Mode for “Remote Diode” measurements Measured value of remote thermal diode temperature channel 1b Measured value of remote thermal diode temperature channel 2b Filtered value of remote thermal diode temperature channel 1b Filtered value of remote thermal diode temperature channel 2b 8- bit value of the PWM1 duty cycle. 8-bit value of the PWM2 duty cycle Lower byte of the high resolution PWM1 duty cycle register Upper byte of the high resolution PWM1 duty cycle register Lower byte of the high resolution PWM2 duty cycle register Upper byte of the high resolution PWM2 duty cycle register Register Name Description Not Defined Not Applicable Read Only Read or Write Read or Write to Clear Address 00h 01h 02h-04h Description Used to set the XOR test tree mode SMBus read/write test register FACTORY REGISTERS VALUE REGISTER SECTION 1 Zone 1b (CPU1 Diode b) Temp Zone 2b (CPU2 Diode b) Temp Zone 1b (CPU1 Diode b) Filtered Temp Zone 2b (CPU2 Diode b) Fitlered Temp PWM1 8-bit Duty Cycle Value PWM2 8-bit Duty Cycle Value x x x x PWM1 Duty Cycle Override (low byte) PWM1 Duty Cycle Override (high byte) PWM2 Duty Cycle Override (low byte) PWM2 Duty Cycle Override (high byte) Z1a_LSB Z1a_MSB Z1b_LSB Z1b_MSB Z2a_LSB Z2a_MSB 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh HIGH RESOLUTION PWM OVERIDE REGISTERS EXTENDED RESOLUTION TEMPERATURE VALUE REGISTERS 10h 11h 12h 13h 14h 15h Zone 1a (CPU1) extended resolution unfiltered temperature value register, least-significant byte Zone 1a (CPU1) extended resolution unfiltered temperature value register, most-significant byte Zone 1b (CPU1) extended resolution unfiltered temperature value register, least-significant-byte Zone 1b (CPU1) extended resolution unfiltered temperature value register, most-significant byte Zone 2a (CPU2) extended resolution unfiltered temperature value register, least-significant-byte Zone 2a (CPU2) extended resolution unfiltered temperature value register, most-significant byte www.national.com 10 LM94 13.0 Registers Lock Z2b_LSB Z2b_MSB Z1a_F_LSB Z1a_F_MSB Z1b_F_LSB Z1b_F_MSB Z2a_F_LSB Z2a_F_MSB Z2b_F_LSB Z2b_F_MSB Z3_LSB Z3_MSB Z4_LSB Z4_MSB (Continued) Address 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh 20h 21h 22h 23h Description Zone 2b (CPU2) extended resolution unfiltered temperature value register, least-significant-byte Zone 2b (CPU2) extended resolution unfiltered temperature value register, most-significant byte Zone 1a (CPU1) extended resolution filtered temperature value register, least-significant byte Zone 1a (CPU1) extended resolution filtered temperature value register, most-significant byte Zone 1b (CPU1) extended resolution filtered temperature value register, least-significant-byte Zone 1b (CPU1) extended resolution filtered temperature value register, most-significant byte Zone 2a (CPU2) extended resolution filtered temperature value register, least-significant-byte Zone 2a (CPU2) extended resolution filtered temperature value register, most-significant byte Zone 2b (CPU2) extended resolution filtered temperature value register, least-significant-byte Zone 2b (CPU2) extended resolution filtered temperature value register, most-significant byte Zone 3 (Internal) extended resolution temperature value register, least-significant byte Zone 3 (Internal) extended resolution temperature value register, least-significant byte Zone 4 (External Digital) extended resolution temperature value register, most-significant byte Zone 4 (External Digital) extended resolution temperature value register, least-significant byte Register Name EXTENDED RESOLUTION TEMPERATURE VALUE REGISTERS Reserved 24h-30h PI LOOP AND FAN CONTROL SETUP REGISTERS x x x x x x x x x x x x x Temperature Source Select PWM Filter Settings PWM1 Filter Shutoff Threshold PWM2 Filter Shutoff Threshold PI/LUT Fan Control Bindings PI Controller Minimum PWM and Hysteresis Zone 1 Tcontrol Zone 2 Tcontrol Zone 1 Toff Zone 2 Toff P Coefficient I Coefficient PI Exponents Manufacturer ID 31h 32h 33h 34h 35h 36h 37h 38h 39h 3Ah 3Bh 3Ch 3Dh 3Eh Selects the temperature source for some temperature zones. Sets the IIR filter coefficients for the PWM outputs for low resolution sources PWM1 Filter Shutoff Threshold PWM2 Filter Shutoff Threshold PI/LUT fan control binding configuration PI Controller Minimum PWM and Hysteresis settings Zone 1 (CPU1) PI Controller Target Temperature (Tcontrol) Zone 2 (CPU2) PI Controller Target Temperature (Tcontrol) Zone 1 (CPU1) PI Controller Off Temperature (Toff) Zone 2 (CPU2) PI Controller Off Temperature (Toff) PI controller proportional coefficient PI controller integral coefficient PI controller coefficient exponents Contains manufacturer ID code DEVICE IDENTIFICATION REGISTERS 11 www.national.com LM94 13.0 Registers Lock (Continued) Address 3Fh 40h 41h 42h 43h 44h 45h 46h 47h 48h 49h 4Ah 4Bh 4Ch 4Dh 4Eh 4Fh 50h 51h 52h 53h 54h 55h 56h 57h 58h 59h 5Ah 5Bh 5Ch 5Dh 5Eh 5Fh 60h 61h 62h 63h 64h 65h 66h 67h Measured P1_PROCHOT throttle percentage Description Contains code for major and minor revisions BMC error status register 1 BMC error register 2 BMC error register 3 BMC error register 4 BMC error register for P1_PROCHOT BMC error register for P2_PROCHOT BMC error register for GPIs BMC error register for Fans HOST error status register 1 HOST error register 2 HOST error register 3 HOST error register 4 HOST error register for P1_PROCHOT HOST error register for P2_PROCHOT HOST error register for GPIs HOST error register for Fans Measured value of remote thermal diode temperature channel 1a Measured value of remote thermal diode temperature channel 2a Measured temperature from on-chip sensor Measured temperature from external temperature sensor Filtered value of remote thermal diode temperature channel 1a Filtered value of remote thermal diode temperature channel 2a Measured value of AD_IN1 Measured value of AD_IN2 Measured value of AD_IN3 Measured value of AD_IN4 Measured value of AD_IN5 Measured value of AD_IN6 Measured value of AD_IN7 Measured value of AD_IN8 Measured value of AD_IN9 Measured value of AD_IN10 Measured value of AD_IN11 Measured value of AD_IN12 Measured value of AD_IN13 Measured value of AD_IN14 Measured value of AD_IN15 Measured value of AD_IN16 (VDD 3.3V S/B) Register Name Version/Stepping PI LOOP AND FAN CONTROL SETUP REGISTERS BMC ERROR STATUS REGISTERS B_Error Status 1 B_Error Status 2 B_Error Status 3 B_Error Status 4 B_P1_PROCHOT Error Status B_P2_PROCHOT Error Status B_GPI Error Status B_Fan Error Status HOST ERROR STATUS REGISTERS H_Error Status 1 H_Error Status 2 H_Error Status 3 H_Error Status 4 H_P1_PROCHOT Error Status H_P2_PROCHOT Error Status H_GPI Error Status H_Fan Error Status VALUE REGISTERS SECTION 2 Zone 1a (CPU1) Temp Zone 2a (CPU2) Temp Zone 3 (Internal) Temp Zone 4 (External Digital) Temp Zone 1a (CPU1) Filtered Temp Zone 2a (CPU2) Filtered Temp AD_IN1 Voltage AD_IN2 Voltage AD_IN3 Voltage AD_IN4 Voltage AD_IN5 Voltage AD_IN6 Voltage AD_IN7 Voltage AD_IN8 Voltage AD_IN9 Voltage AD_IN10 Voltage AD_IN11 Voltage AD_IN12 Voltage AD_IN13 Voltage AD_IN14 Voltage AD_IN15 Voltage AD_IN16 Voltage Reserved Current P1_PROCHOT www.national.com 12 LM94 13.0 Registers Lock (Continued) Address 68h 69h 6Ah 6Bh 6Ch 6Dh 6Eh 6Fh 70h 71h 72h 73h 74h 75h 76h-77h Description Average P1_PROCHOT throttle percentage Measured P2_PROCHOT throttle percentage Average P2_PROCHOT throttle percentage Current GPIO state Current VID value of Processor 1 Current VID value of Processor 2 Measured FAN Tach 1 LSB Measured FAN Tach 1 MSB Measured FAN Tach 2 LSB Measured FAN Tach 2 MSB Measured FAN Tach 3 LSB Measured FAN Tach 3 MSB Measured FAN Tach 4 LSB Measured FAN Tach 4 MSB Register Name Average P1_PROCHOT Current P2_PROCHOT Average P2_PROCHOT GPI State P1_VID P2_VID FAN Tach 1 LSB FAN Tach 1 MSB FAN Tach 2 LSB FAN Tach 2 MSB FAN Tach 3 LSB FAN Tach 3 MSB FAN Tach 4 LSB FAN Tach 4 MSB Reserved VALUE REGISTERS SECTION 2 TEMPERATURE LIMIT REGISTERS Zone 1 (CPU1) Low Temp Zone 1 (CPU1) High Temp Zone 2 (CPU2) Low Temp Zone 2 (CPU2) High Temp Zone 3 (Internal) Low Temp Zone 3 (Internal) High Temp Zone 4 (External Digital) Low Temp Zone 4 (External Digital) High Temp x x x x Fan Boost Temp Zone 1 Fan Boost Temp Zone 2 Fan Boost Temp Zone 3 Fan Boost Temp Zone 4 Zone1 and Zone 2 Hysteresis Zone 3 and Zone 4 Hysteresis Reserved 78h 79h 7Ah 7Bh 7Ch 7Dh 7Eh 7Fh 80h 81h 82h 83h 84h 85h 86h-8Dh Low limit for external thermal diode temperature channel 1 (D1) measurement High limit for external thermal diode temperature channel 1 (D1) measurement Low limit for external thermal diode temperature channel 2 (D2) measurement High limit for external thermal diode temperature channel 2 (D2) measurement Low limit for local temperature measurement High limit for local temperature measurement Low limit for external digital temperature sensor High limit for external digital temperature sensor Zone 1 (CPU1) fan boost temperature Zone 2 (CPU2) fan boost temperature Zone 3 (Internal) fan boost temperature Zone 4 (External Digital) fan boost temperature Zone 1 and Zone 2 hysteresis for limit comparisons Zone 3 and Zone 4 hysteresis for limit comparisons ZONE 1b and 2b TEMPERATURE READING ADJUSTMENT REGISTERS Zone 1b Temp Adjust Zone 2b Temp Adjust 8Eh 8Fh Allows all Zone 1b temperature measurements to be adjusted by a programmable offset. Allows all Zone 2b temperature measurements to be adjusted by a programmable offset. 13 www.national.com LM94 13.0 Registers Lock (Continued) Address 90h 91h 92h 93h 94h 95h 96h 97h 98h 99h 9Ah 9Bh 9Ch 9Dh 9Eh 9Fh A0h A1h A2h A3h A4h A5h A6h A7h A8h A9h AAh ABh ACh ADh AEh AFh B0h B1h B2h B3h Description Low limit for analog input 1 measurement High limit for analog input 1 measurement Low limit for analog input 2 measurement High limit for analog input 2 measurement Low limit for analog input 3 measurement High limit for analog input 3 measurement Low limit for analog input 4 measurement High limit for analog input 4 measurement Low limit for analog input 5 measurement High limit for analog input 5 measurement Low limit for analog input 6 measurement High limit for analog input 6 measurement Low limit for analog input 7 measurement High limit for analog input 7 measurement Low limit for analog input 8 measurement High limit for analog input 8 measurement Low limit for analog input 9 measurement High limit for analog input 9 measurement Low limit for analog input 10 measurement High limit for analog input 10 measurement Low limit for analog input 11 measurement High limit for analog input 11 measurement Low limit for analog input 12 measurement High limit for analog input 12 measurement Low limit for analog input 13 measurement High limit for analog input 13 measurement Low limit for analog input 14 measurement High limit for analog input 14 measurement Low limit for analog input 15 measurement High limit for analog input 15 measurement Low limit for analog input 16 measurement High limit for analog input 16 measurement User settable limit for P1_PROCHOT User settable limit for P2_PROCHOT VID offset values for window comparator for CPU1 Vccp (AD_IN7) VID offset values for window comparator for CPU2 Vccp (AD_IN8) FAN Tach 1 Limit LSB FAN Tach 1 Limit MSB FAN Tach 2 Limit LSB FAN Tach 2 Limit MSB FAN Tach 3 Limit LSB FAN Tach 3 Limit MSB FAN Tach 4 Limit LSB Register Name AD_IN1 Low Limit AD_IN1 High Limit AD_IN2 Low Limit AD_IN2 High Limit AD_IN3 Low Limit AD_IN3 High Limit AD_IN4 Low Limit AD_IN4 High Limit AD_IN5 Low Limit AD_IN5 High Limit AD_IN6 Low Limit AD_IN6 High Limit AD_IN7 Low Limit AD_IN7 High Limit AD_IN8 Low Limit AD_IN8 High Limit AD_IN9 Low Limit AD_IN9 High Limit AD_IN10 Low Limit AD_IN10 High Limit AD_IN11 Low Limit AD_IN11 High Limit AD_IN12 Low Limit AD_IN12 High Limit AD_IN13 Low Limit AD_IN13 High Limit AD_IN14 Low Limit AD_IN14 High Limit AD_IN15 Low Limit AD_IN15 High Limit AD_IN16 Low Limit AD_IN16 High Limit P1_PROCHOT User Limit P2_PROCHOT User Limit Vccp1 Limit Offsets Vccp2 Limit Offsets OTHER LIMIT REGISTERS FAN Tach 1 Limit LSB FAN Tach 1 Limit MSB FAN Tach 2 Limit LSB FAN Tach 2 Limit MSB FAN Tach 3 Limit LSB FAN Tach 3 Limit MSB FAN Tach 4 Limit LSB B4h B5h B6h B7h B8h B9h BAh www.national.com 14 LM94 13.0 Registers Lock (Continued) Address BBh BCh FAN Tach 4 Limit MSB Controls the hysteresis for voltage limit comparisons. Also selects filtered or unfiltered temperature usage for temperature limit comparisons and fan control. Enables smart tach detection. Also selects 0.5˚C or 1.0˚C resolution for fan control. Control the input threshold levels for the P1_VIDx, P2_VIDx and GPIO_x inputs. Controls the ramp rate of the PWM duty cycle when VRDx_HOT is asserted, as well as the ramp rate when PROCHOT exceeds the user threshold. Fan Boost Hysteresis for zones 1 and 2 Fan Boost Hysteresis for zones 3 and 4 Configures Spike Smoothing for zones 1 and 2 Controls MinPWM and hysteresis setting for LUT 1 and 2 auto-fan control Controls MinPWM and hysteresis setting for LUT 3 and 4 auto-fan control Controls the output state of the GPIO pins Controls assertion of P1_PROCHOT or P2_PROCHOT Configures the time window over which the PROCHOT inputs are measured Controls PWM control source bindings. Controls PWM override and output polarity Controls PWM spin-up duration and duty cycle Frequency control for PWM1. Controls PWM control source bindings. Controls PWM override and output polarity Controls PWM spin-up duration and duty cycle Frequency control for PWM2 Base temperature to which look-up table offset is applied for LUT 1 Base temperature to which look-up table offset is applied for LUT 2 Base temperature to which look-up table offset is applied for LUT 3 Base temperature to which look-up table offset is applied for LUT 4 Step 2 LUT 1/2 and LUT 3/4 Offset Temperatures Step 3 LUT 1/2 and LUT 3/4 Offset Temperatures Step 4 LUT 1/2 and LUT 3/4 Offset Temperatures Step 5 LUT 1/2 and LUT 3/4 Offset Temperatures Description Register Name FAN Tach 4 Limit MSB OTHER LIMIT REGISTERS SETUP REGISTERS Special Function Control 1 Special Function Control 2 x x GPI / VID Level Control PWM Ramp Control BDh BEh BFh x x x x x Fan Boost Hysteresis (Zones 1/2) Fan Boost Hysteresis (Zones 3/4) Zones 1/2 Spike Smoothing Control LUT 1/2 MinPWM and Hysteresis LUT 3/4 MinPWM and Hysteresis C0h C1h C2h C3h C4h GPO PROCHOT Control PROCHOT Time Interval C5h C6h C7h x x x x x x x x x x x x PWM1 Control 1 PWM1 Control 2 PWM1 Control 3 PWM1 Control 4 PWM2 Control 1 PWM2 Control 2 PWM2 Control 3 PWM2 Control 4 LUT 1 Base Temperature LUT 2 Base Temperature LUT 3 Base Temperature LUT 4 Base Temperature C8h C9h CAh CBh CCh CDh CEh CFh D0h D1h D2h D3h x x x x Step 2 Temp Offset Step 3 Temp Offset Step 4 Temp Offset Step 5 Temp Offset D4h D5h D6h D7h 15 www.national.com LM94 13.0 Registers Lock x x x x x x x x SETUP REGISTERS (Continued) Address D8h D9h DAh DBh DCh DDh DEh DFh E0h E1h E2h E3h E4h E5h E6h E7h E8h E9h EAh EBh ECh EDh Description Step 6 LUT 1/2 and LUT 3/4 Offset Temperatures Step 7 LUT 1/2 and LUT 3/4 Offset Temperatures Step 8 LUT 1/2 and LUT 3/4 Offset Temperatures Step 9 LUT 1/2 and LUT 3/4 Offset Temperatures Step 10 LUT 1/2 and LUT 3/4 Offset Temperatures Step 11 LUT 1/2 and LUT 3/4 Offset Temperatures Step 12 LUT 1/2 and LUT 3/4 Offset Temperatures Step 13 LUT 1/2 and LUT 3/4 Offset Temperatures Controls the tachometer input to PWM output binding Controls the fan boost function upon a tach error Gives Master error status, ASF reset control and Max PWM control Configures various outputs and provides START bit Used to communicate the system sleep state to the LM94 Sleep state S1 GPI error mask register Sleep state S1 fan tach error mask register Sleep state S3 GPI error mask register Sleep state S3 fan tach error mask register Sleep state S3 temperature or voltage error mask register Sleep state S4/5 GPI error mask register Sleep state S4/5 temperature or voltage error mask register Error mask register for GPI faults Error mask register for VRDx_HOT, GPI, and dynamic Vccp limit checking. Register Name Step 6 Temp Offset Step 7 Temp Offset Step 8 Temp Offset Step 9 Temp Offset Step 10 Temp Offset Step 11 Temp Offset Step 12 Temp Offset Step 13 Temp Offset TACH to PWM Binding x x x Tach Boost Control LM94 Status/Control LM94 Configuration Sleep State Control S1 GPI Mask S1 Fan Mask S3 GPI Mask S3 Fan Mask S3 Temperature/Voltage Mask S4/5 GPI Mask S4/5 Temperature/Voltage Mask SLEEP STATE CONTROL AND MASK REGISTERS OTHER MASK REGISTERS GPI Error Mask Miscellaneous Error Mask ZONE 1a AND 2a TEMPERATURE READING ADJUSTMENT REGISTERS Zone 1a Temp Adjust Zone 2a Temp Adjust BLOCK COMMANDS Block Write Command Block Read Command Fixed Block 0 Fixed Block 1 Fixed Block 2 Fixed Block 3 Fixed Block 4 Fixed Block 5 Fixed Block 6 Fixed Block 7 Fixed Block 8 Fixed Block 9 Fixed Block 10 F0h F1h F2h F3h F4h F5h F6h F7h F8h F9h FAh FBh FCh SMBus Block Write Command Code SMBus Block Write/Read Process call Fixed block code address 40h, size 8 bytes Fixed block code address 48h, size 8 bytes Fixed block code address 50h, size 6 bytes Fixed block code address 56h, size 16 bytes Fixed block code address 67h, size 4 bytes Fixed block code address 6Eh, size 8 bytes Fixed block code address 78h, size 12 bytes Fixed block code address 90h, size 32 bytes Fixed block code address B4h, size 8 bytes Fixed block code address C8h, size 8 bytes Fixed block code address D0h, size 16 bytes EEh EFh Allows all Zone 1a temperature measurements to be adjusted by a programmable offset Allows all Zone 2a temperature measurements to be adjusted by a programmable offset www.national.com 16 LM94 13.0 Registers Lock BLOCK COMMANDS Fixed Block 11 Reserved (Continued) Address FDh FEh-FFh Description Fixed block code address E5h, size 9 bytes Reserved for future commands Register Name Please contact your local sales office for complete LM94 applications information. 17 www.national.com LM94 14.0 Absolute Maximum Ratings (Notes 1, 2) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Positive Supply Voltage (VDD) Voltage on Any Digital Input or Output Pin Voltage on +5V Input 6.0V −0.3V to 6.0V (Except Analog Inputs) −0.3V to +6.667V ESD Susceptibility (Note 4) Human Body Model Machine Model Charged Device Model Storage Temperature 3 kV 300V 750V −65˚C to +150˚C Soldering process must comply with National’s reflow temperature profile specifications. Refer to www.national.com/packaging/. (Note 5) 15.0 Operating Ratings (Notes 1, 2) TMIN ≤ TA ≤ TMAX Operating Temperature Range Nominal Supply Voltage Supply Voltage Range (VDD) VID0-VID5 Digital Input Voltage Range Package Thermal Resistance (Note 6) 0˚C ≤ TA ≤ +85˚C 3.3V +3.0V to +3.6V −0.05V to +5.5V −0.05V to (VDD + 0.05V) 79˚C/W Voltage at Positive Remote Diode Inputs, AD_IN1, AD_IN2, AD_IN3, and AD_IN15 Inputs −0.3V to (VDD + 0.05V) Voltage at Other Analog Voltage Inputs Input Current at Thermal Diode Negative Inputs Input Current at any pin (Note 3) Package Input Current (Note 3) Maximum Junction Temperature (Note 9) (TJMAX) −0.3V to +6.0V ± 1 mA ± 10mA ± 100 mA 150 ˚C DC Electrical Characteristics The following limits apply for +3.0 VDC to +3.6 VDC, unless otherwise noted. Bold face limits apply for TA = TJ over TMIN to TMAX of the operating range; all other limits TA = TJ = 25˚C unless otherwise noted. TA is the ambient temperature of the LM94; TJ is the junction temperature of the LM94; TD is the junction temperature of the thermal diode. Symbol Parameter Conditions Typical (Note 9) Limits (Note 10) Units (Limits) POWER SUPPLY CHARACTERISTICS Power Supply Current Converting, Interface and Fans Inactive, Peak Current Converting, Interface and Fans Inactive, Average Current Power-On Reset Threshold Voltage TEMPERATURE-TO-DIGITAL CONVERTER CHARACTERISTICS Local Temperature Accuracy Over Full Range Local Temperature Resolution Remote Thermal Diode Temperature Accuracy Over Full Range; targeted for a typical Pentium processor on 90 nm or 65 nm process(Note 8) Remote Thermal Diode Temperature Accuracy; targeted for a typical Pentium processor on 90nm or 65nm process (Note 8) Remote Temperature Resolution Thermal Diode Source Current Thermal Diode Current Ratio TC www.national.com 2 2.75 mA (max) 1.6 1.6 2.7 mA V (min) V (max) ˚C (max) ˚C (max) ˚C 2 0˚C ≤ TA ≤ 85˚C TA = +55˚C 0˚C ≤ TA ≤ 85˚C and 0˚C ≤ TD ≤ 100˚C 0˚C ≤ TA ≤ 85˚C and TD =70˚C 0˚C ≤ TA ≤ 85˚C and 25˚C ≤ TD ≤ 70˚C ±2 ±1 1 ±3 ± 2.5 ±3 ± 2.5 ±1 1 ˚C (max) ˚C (max) ˚C ˚C 230 µA (max) µA 100 ms (max) High Level Low Level 172 10.75 16 Total Monitoring Cycle Time 18 LM94 DC Electrical Characteristics (Continued) The following limits apply for +3.0 VDC to +3.6 VDC, unless otherwise noted. Bold face limits apply for TA = TJ over TMIN to TMAX of the operating range; all other limits TA = TJ = 25˚C unless otherwise noted. TA is the ambient temperature of the LM94; TJ is the junction temperature of the LM94; TD is the junction temperature of the thermal diode. Symbol Parameter Conditions Typical (Note 9) Limits (Note 10) Units (Limits) % of FS (max) LSB %/V (of FS) 100 200 140 60 ms (max) kΩ (min) nA (max) ANALOG-TO-DIGITAL VOLTAGE MEASUREMENT CONVERTER CHARACTERISTICS TUE DNL PSS TC Total Unadjusted Error (Note 12) Differential Non-Linearity Power Supply (VDD) Sensitivity Total Monitoring Cycle Time Input Resistance for Inputs with Dividers AD_IN1- AD_IN3 and AD_IN15 Analog Input Leakage Current (Note 13) REFERENCE OUTPUT (VREF) CHARACTERISTICS Tolerance VREF Output Voltage (Note 14) Load Regulation DIGITAL OUTPUTS: PWM1, PWM2 IOL VOL VOL Maximum Current Sink Output Low Voltage Output Low Voltage (Note excessive current flow causes self-heating and degrades the internal temperature accuracy.) High Level Output Leakage Current Maximum Total Sink Current for all Digital Outputs Combined Digital Output Capacitance Input High Voltage Except Address Select Input Low Voltage Except Address Select Input High Voltage for Address Select Input Mid Voltage for Address Select Input Low Voltage for Address Select DC Hysteresis Input High Current Input Low Current Digital Input Capacitance VIN = VDD VIN = 0V 20 0.3 −10 10 20 2.1 0.8 90% VDD 43% VDD 57% VDD 10% VDD IOUT = 8.0 mA IOUT = 4.0 mA IOUT = 6 mA VOUT = VDD 0.1 8 0.4 mA (min) V (max) ISOURCE = −2 mA ISINK = 2 mA 2.500 0.1 ±2 ±1 ±1 ±1 2.525 2.475 % (max) V (max) V (min) % DIGITAL OUTPUTS: ALL 0.4 0.55 10 32 V (min) V (min) µA (max) mA (max) pF V (min) V (max) V (min) V (min) V (max) V (max) V µA (min) µA (max) pF IOH IOTMAX CO VIH VIL VIH VIM VIL VHYST IIH IIL CIN DIGITAL INPUTS: ALL DIGITAL INPUTS: P1_VIDx, P2_VIDx, GPI_9, GPI_8, GPIO_7, GPIO_6, GPIO_5, GPIO_4 (When respective bit set in Register BEh GPI/VID Level Control) VIH VIL Alternate Input High Voltage (AGTL+ Compatible) Alternate Input Low Voltage (AGTL+ Compatible) 0.8 0.4 V (min) V (max) 19 www.national.com LM94 AC Electrical Characteristics The following limits apply for +3.0 VDC to +3.6 VDC, unless otherwise noted. Bold face limits apply for TA = TJ = TMIN to TMAX of the operating range; all other limits TA = TJ = 25˚C unless otherwise noted. Symbol Parameter Conditions Typical (Note 9) 14 2 22.5 Limits (Note 10) Units (Limits) bits pulses kHz FAN RPM-TO-DIGITAL CHARACTERISTICS Counter Resolution Number of fan tach pulses count is based on Counter Frequency Accuracy PWM OUTPUT CHARACTERISTICS Frequency Tolerances Duty-Cycle Tolerance RESET INPUT/OUTPUT CHARACTERISTICS Output Pulse Width Upon Power Up Minimum Input Pulse Width Reset Output Fall Time SMBus TIMING CHARACTERISTICS fSMBCLK tBUF tHD;STA SMBCLK (Clock) Clock Frequency SMBus Free Time between Stop and Start Conditions Hold time after (Repeated) Start Condition. After this period, the first clock is generated. Repeated Start Condition Setup Time Stop Condition Setup Time Data Input Setup Time to SMBCLK High Data Output Hold Time after SMBCLK Low SMBCLK Low Period SMBCLK High Period Rise Time Fall Time Timeout SMBDAT or SMBCLK low time required to reset the Serial Bus Interface to the Idle State Time in which a device must be operational after power-on reset Capacitance Load on SMBCLK and SMBDAT VDD > +2.8V 31 25 35 10 100 4.7 kHz (min) kHz (max) µs (min) 1.6V to 0.4V Logic Levels 250 330 10 1 ms (min) ms (max) µs (min) µs (max) ±6 ±6 ±6 % (max) % (max) % (max) ±2 4.0 4.7 4.0 250 300 1075 4.7 50 4.0 50 1 300 µs (min) µs (min) µs (min) ns (min) ns (min) ns (max) µs (min) µs (max) µs (min) µs (max) µs (max) ns (max) ms ms (min) ms (max) tSU;STA tSU;STO tSU;DAT tHD;DAT tLOW tHIGH tR tF tTIMEOUT tPOR CL 500 ms (max) 400 pF (max) www.national.com 20 LM94 16.0 Timing Waveform 20112403 17.0 Electrical Notes Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions. Note 2: All voltages are measured with respect to GND, unless otherwise noted. Note 3: When the input voltage (VIN) at any pin exceeds the power supplies (VIN < (GND or AGND) or VIN > VDD, except for analog voltage inputs), the current at that pin should be limited to 10 mA. The 100 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 10 mA to ten. Parasitic components and/or ESD protection circuitry are shown below for the LM94’s pins. Care should be taken not to forward bias the parasitic diode, D1, present on pins D+ and D− as shown in circuits C and D. Doing so by more than 50 mV may corrupt temperature measurements. D1 and the ESD Clamp are connected between V+ (VDD, AD_IN16) and GND as shown in circuit B. SNP stands for snap-back device. Symbol GPIO_0/TACH1 GPIO_1/TACH2 GPIO_2/TACH3 GPIO_3/TACH4 GPIO_4 / P1_THERMTRIP GPIO_5 / P2_THERMTRIP GPIO_6 GPIO_7 VRD1_HOT VRD2_HOT SCSI_TERM1 SCSI_TERM2 SMBDAT SMBCLK ALERT/XtestOut RESET AGND Pin # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 Circuit A A A A A A A A A A A A A A A A B (Internally shorted to GND pin.) A C D C D All Input Circuits Circuit A Circuit B VREF REMOTE1– REMOTE1+ REMOTE2– REMOTE+ 18 19 20 21 22 21 www.national.com LM94 17.0 Electrical Notes Symbol AD_IN1 AD_IN2 AD_IN3 AD_IN4 AD_IN5 AD_IN6 AD_IN7 AD_IN8 AD_IN9 AD_IN10 AD_IN11 AD_IN12 AD_IN13 AD_IN14 AD_IN15 ADDR_SEL AD_IN16/VDD (V+) GND (Continued) Pin # 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 Circuit D D D E E E E E E E E E E E D A B B (Internally shorted to AGND.) A A A A A A A A A A A A A A A A Circuit E Circuit D Circuit C All Input Circuits PWM1 PWM2 P1_VID0 P1_VID1 P1_VID2 P1_VID3 P1_VID4 P1_VID5 P1_PROCHOT P2_PROCHOT P2_VID0 P2_VID1 P2_VID2 P2_VID3 P2_VID4 P2_VID5 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 Note 4: Human body model, 100 pF discharged through a 1.5 kΩ resistor. Machine model, 200 pF discharged directly into each pin. Charged device model (CDM) simulates a pin slowly acquiring charge (such as from a device sliding down the feeder in an automated assembler) then rapidly being discharged. Note 5: Reflow temperature profiles are different for lead-free and non lead-free packages. Note 6: The maximum power dissipation must be de-rated at elevated temperatures and is dictated by TJMAX, θJA and the ambient temperature, TA. The maximum allowable power dissipation at any temperature is PD MAX= (TJMAX − TA) / θJA. The θJAfor the LM94 when mounted to 1 oz. copper foil PCB the θJA with different air flow is listed in the following table. Air Flow 0 m/s 1.14 m/s (225 LFPM) 2.54 m/s (500 LFPM) Junction to Ambient Thermal Resistance, θJA 79 ˚C/W 62 ˚C/W 52 ˚C/W Note 7: See the URL "http://www.national.com/packaging/" for other recommendations and methods of soldering surface mount devices. Note 8: At the time of first pubication of this specification (Jan 2006), this specification applies to either Pentium or Xeon Processors on 90nm or 65nm process when TruTherm is selected. When TruTherm is deselected this specification applies to an MMBT3904. This specification does include the error caused by the variability of the diode ideality and series resistance parameters. Note 9: Typical parameters are at TJ = TA = 25 ˚C and represent most likely parametric norm. www.national.com 22 LM94 17.0 Electrical Notes (Continued) Note 10: Limits are guaranteed to National’s AOQL (Average Outgoing Quality Level). Note 11: TUE (Total Unadjusted Error) includes Offset, Gain and Linearity errors of the ADC. Note 12: Total Monitoring Cycle Time includes all temperature and voltage conversions. Note 13: Leakage current approximately doubles every 20 ˚C. Note 14: A total digital I/O current of 40 mA can cause 6 mV of offset in Vref. Note 15: Timing specifications are tested at the TTL logic levels, VIL = 0.4V for a falling edge and VIH = 2.4V for a rising edge. TRI-STATE output voltage is forced to 1.4V. 23 www.national.com LM94 TruTherm™ Hardware Monitor with PI Loop Fan Control for Server Management 18.0 Physical Dimensions inches (millimeters) unless otherwise noted 56-Lead Molded TSSOP Package, JEDEC Registration Number MO-153 Variation EE, Order Number LM94CIMT or LM94CIMTX, NS Package Number MTD56 National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications. For the most current product information visit us at www.national.com. LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. BANNED SUBSTANCE COMPLIANCE National Semiconductor manufactures products and uses packing materials that meet the provisions of the Customer Products Stewardship Specification (CSP-9-111C2) and the Banned Substances and Materials of Interest Specification (CSP-9-111S2) and contain no ‘‘Banned Substances’’ as defined in CSP-9-111S2. Leadfree products are RoHS compliant. National Semiconductor Americas Customer Support Center Email: new.feedback@nsc.com Tel: 1-800-272-9959 www.national.com National Semiconductor Europe Customer Support Center Fax: +49 (0) 180-530 85 86 Email: europe.support@nsc.com Deutsch Tel: +49 (0) 69 9508 6208 English Tel: +44 (0) 870 24 0 2171 Français Tel: +33 (0) 1 41 91 8790 National Semiconductor Asia Pacific Customer Support Center Email: ap.support@nsc.com National Semiconductor Japan Customer Support Center Fax: 81-3-5639-7507 Email: jpn.feedback@nsc.com Tel: 81-3-5639-7560 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.