LMC6041AIM

LMC6041 CMOS Single Micropower Operational Amplifier December 1994 LMC6041 CMOS Single Micropower Operational Amplifier General Description Ultra-low power consumption and low input-leakage current are the hallmarks of the LMC6041. Providing input currents of only 2 fA typical, the LMC6041 can operate from a single supply, has output swing extending to each supply rail, and an input voltage range that includes ground. The LMC6041 is ideal for use in systems requiring ultra-low power consumption. In addition, the insensitivity to latch-up, high output drive, and output swing to ground without requiring external pull-down resistors make it ideal for single-supply battery-powered systems. Other applications for the LMC6041 include bar code reader amplifiers, magnetic and electric field detectors, and hand-held electrometers. This device is built with National’s advanced Double-Poly Silicon-Gate CMOS process. See the LMC6042 for a dual, and the LMC6044 for a quad amplifier with these features. Features n n n n n Low supply current: 14 µA (Typ) Operates from 4.5V to 15.5V single supply Ultra low input current: 2 fA (Typ) Rail-to-rail output swing Input common-mode range includes ground Applications n n n n n n n Battery monitoring and power conditioning Photodiode and infrared detector preamplifier Silicon based transducer systems Hand-held analytic instruments pH probe buffer amplifier Fire and smoke detection systems Charge amplifier for piezoelectric transducers Connection Diagram 8-Pin DIP/SO DS011136-1 Ordering Information Temperature Range Package 8-Pin Small Outline 8-Pin Molded DIP Industrial −40˚C to +85˚C LMC6041AIM LMC6041IM LMC6041AIN LM6041IN N08E M08A Rail Tape and Reel Rail NSC Drawing Transport Media © 1999 National Semiconductor Corporation DS011136 www.national.com Absolute Maximum Ratings (Note 1) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Differential Input Voltage Supply Voltage (V+ − V−) Output Short Circuit to V− Output Short Circuit to V+ Lead Temperature (Soldering, 10 sec.) Storage Temperature Range Junction Temperature ESD Tolerance (Note 4) Current at Input Pin Current at Output Pin Current at Power Supply Pin Voltage at Input/Output Pin Power Dissipation ± 18 mA 35 mA (V+) + 0.3V, (V−) − 0.3V (Note 3) ± Supply Voltage 16V (Note 2) (Note 11) 260˚C −65˚C to +150˚C 110˚C 500V ± 5 mA Operating Ratings Temperature Range LMC6041AI, LMC6041I Supply Voltage Power Dissipation Thermal Resistance (θJA) (Note 10) 8-Pin DIP 8-Pin SO −40˚C ≤ TJ ≤ +85˚C 4.5V ≤ V+ ≤ 15.5V (Note 9) 101˚C/W 165˚C/W Electrical Characteristics Unless otherwise specified, all limits guaranteed for TA = TJ = 25˚C. Boldface limits apply at the temperature extremes. V+ = 5V, V− = 0V, VCM = 1.5V, VO = V+/2, and RL > 1M unless otherwise specified. Typical Symbol VOS TCVOS IB IOS RIN CMRR +PSRR −PSRR CMR Parameter Input Offset Voltage Input Offset Voltage Average Drift Input Bias Current Input Offset Current Input Resistance Common Mode Rejection Ratio Positive Power Supply Rejection Ratio Negative Power Supply Rejection Ratio Input Common-Mode Voltage Range 0V ≤ VCM ≤ 12.0V V+ = 15V 5V ≤ V+ ≤ 15V VO = 2.5V 0V ≤ V− ≤ −10V VO = 2.5V V+ = 5V and 15V for CMRR ≥ 50 dB V+ − 1.9V AV Large Signal Voltage Gain Sinking RL = 25 kΩ (Note 7) Sourcing Sinking 500 1000 250 RL = 100 kΩ (Note 7) Sourcing 1000 0.002 0.001 4 2 4 2 pA max pA max TeraΩ 68 66 75 94 −0.4 68 66 84 83 −0.1 0 V+ − 2.3V V+ − 2.5V 400 300 180 120 200 160 100 60 62 60 62 60 74 73 −0.1 0 V+ − 2.3V V+ − 2.4V 300 200 90 70 100 80 50 40 dB min dB min dB min V max V min V/mV min V/mV min V/mV min V/mV min Conditions (Note 5) 1 1.3 LMC6041AI Limit (Note 6) 3 3.3 LMC6041I Limit (Note 6) 6 6.3 mV max µV/˚C Units (Limit) > 10 75 www.national.com 2 Electrical Characteristics (Continued) Unless otherwise specified, all limits guaranteed for TA = TJ = 25˚C. Boldface limits apply at the temperature extremes. V+ = 5V, V− = 0V, VCM = 1.5V, VO = V+/2, and RL > 1M unless otherwise specified. Typical Symbol VO Parameter Output Swing Conditions V+ = 5V RL = 100 kΩ to V+/2 (Note 5) 4.987 0.004 V+ = 5V RL = 25 kΩ to V+/2 4.980 0.010 V+ = 15V RL = 100 kΩ to V+/2 14.970 0.007 V+ = 15V RL = 25 kΩ to V+/2 14.950 0.022 ISC Output Current V+ = 5V Sourcing, VO = 0V Sinking, VO = 5V ISC Output Current V+ = 15V Sourcing, VO = 0V Sinking, VO = 13V IS Supply Current (Note 11) VO = 1.5V V+ = 15V 22 21 40 39 14 18 LMC6041AI Limit (Note 6) 4.970 4.950 0.030 0.050 4.920 4.870 0.080 0.130 14.920 14.880 0.030 0.050 14.900 14.850 0.100 0.150 16 10 16 8 15 10 24 8 20 24 26 31 LMC6041I Limit (Note 6) 4.940 4.910 0.060 0.090 4.870 4.820 0.130 0.180 14.880 14.820 0.060 0.090 14.850 14.800 0.150 0.200 13 8 13 8 15 10 21 8 26 30 34 39 V min V max V min V max V min V max V min V max mA min mA min mA min mA min µA max µA max Units (Limit) AC Electrical Characteristics Unless otherwise specified, all limits guaranteed for TA = TJ = 25˚C. Boldface limits apply at the temperature extremes. V+ = 5V, V− = 0V, VCM = 1.5V, VO = V+/2, and RL > 1M unless otherwise specified. Typ Symbol SR GBW φm en in T.H.D. Parameter Slew Rate Gain-Bandwidth Product Phase Margin Input-Referred Voltage Noise Input-Referred Current Noise Total Harmonic Distortion F = 1 kHz, AV = −5 RL = 100 kΩ, VO = 2 Vpp 0.01 % F = 1 kHz 0.0002 pA/√Hz F = 1 kHz Conditions (Note 8) (Note 5) 0.02 75 60 83 LMC6041AI Limit (Note 6) 0.015 0.010 LMC6041I Limit (Note 6) 0.010 0.007 V/µs min kHz Deg nV/√Hz Units (Limit) ± 5V Supply 3 www.national.com AC Electrical Characteristics (Continued) Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating conditions indicate conditions for which the device is intended to be functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Note 2: Applies to both single-supply and split-supply operation. Continuous short circuit operation at elevated ambient temperature can result in exceeding the maximum allowed junction temperature of 110˚C. Output currents in excess of ± 30 mA over long term may adversely affect reliability. Note 3: The maximum power dissipation is a function of TJ(max), θJA, and TA. The maximum allowable power dissipation at any ambient temperature is PD = (TJ(max) − TA)/θJA. Note 4: Human body model, 1.5 kΩ in series with 100 pF. Note 5: Typical Values represent the most likely parametric norm. Note 6: All limits are guaranteed at room temperature (standard type face) or at operating temperature extremes (bold face type). Note 7: V+ = 15V, VCM = 7.5V and RL connected to 7.5V. For Sourcing tests, 7.5V ≤ VO ≤ 11.5V. For Sinking tests, 2.5V ≤ VO ≤ 7.5V. Note 8: V+ = 15V. Connected as Voltage Follower with 10V step input. Number specified in the slower of the positive and negative slew rates. Note 9: For operating at elevated temperatures the device must be derated based on the thermal resistance θJA with PD = (TJ − TA)/θJA. Note 10: All numbers apply for packages soldered directly into a PC board. Note 11: Do not connect output to V+ when V+ is greater than 13V or reliability may be adversely affected. Typical Performance Characteristics Supply Current vs Supply Voltage VS = ± 7.5V, TA = 25˚C unless otherwise specified Input Bias Current vs Temperature Offset Voltage vs Temperature of Five Representative Units DS011136-19 DS011136-20 DS011136-21 Input Bias Current vs Input Common-Mode Voltage Input Common-Mode Voltage Range vs Temperature Output Characteristics Current Sinking DS011136-22 DS011136-23 DS011136-24 www.national.com 4 Typical Performance Characteristics specified (Continued) Output Characteristics Current Sourcing VS = ± 7.5V, TA = 25˚C unless otherwise Input Voltage Noise vs Frequency Power Supply Rejection Ratio vs Frequency DS011136-25 DS011136-26 DS011136-27 CMRR vs Frequency CMRR vs Temperature Open-Loop Voltage Gain vs Temperature DS011136-28 DS011136-29 DS011136-30 Open-Loop Frequency Response Gain and Phase Responses vs Load Capacitance Gain and Phase Responses vs Temperature DS011136-31 DS011136-32 DS011136-33 5 www.national.com Typical Performance Characteristics specified (Continued) Gain Error (VOS vs VOUT) VS = ± 7.5V, TA = 25˚C unless otherwise Common-Mode Error vs Common-Mode Voltage of Three Representative Units Non-Inverting Slew Rate vs Temperature DS011136-34 DS011136-35 DS011136-36 Inverting Slew Rate vs Temperature Non-Inverting Large Signal Pulse Response (AV = +1) Non-Inverting Small Signal Pulse Response DS011136-37 DS011136-39 DS011136-38 Inverting Large-Signal Pulse Response Inverting Small Signal Pulse Response Stability vs Capacitive Load (AV = +1) DS011136-40 DS011136-41 DS011136-42 www.national.com 6 Typical Performance Characteristics specified (Continued) Stability vs Capacitive Load (AV = ± 10) VS = ± 7.5V, TA = 25˚C unless otherwise DS011136-43 Applications Hints AMPLIFIER TOPOLOGY The LMC6041 incorporates a novel op-amp design topology that enables it to maintain rail-to-rail output swing even when driving a large load. Instead of relying on a push-pull unity gain output buffer stage, the output stage is taken directly from the internal integrator, which provides both low output impedance and large gain. Special feed-forward compensation design techniques are incorporated to maintain stability over a wider range of operating conditions than traditional micropower op-amps. These features make the LMC6041 both easier to design with, and provide higher speed than products typically found in this ultra-low power class. COMPENSATING FOR INPUT CAPACITANCE It is quite common to use large values of feedback resistance with amplifiers with ultra-low input current, like the LMC6041. Although the LMC6041 is highly stable over a wide range of operating conditions, certain precautions must be met to achieve the desired pulse response when a large feedback resistor is used. Large feedback resistors and even small values of input capacitance, due to transducers, photodiodes, and circuits board parasitics, reduce phase margins. When high input impedance are demanded, guarding of the LMC6041 is suggested. Guarding input lines will not only reduce leakage, but lowers stray input capacitance as well. (See Printed-Circuit-Board Layout for High Impedance Work.) The effect of input capacitance can be compensated for by adding a capacitor. Adding a capacitor, Cf, around the feedback resistor (as in Figure 1 ) such that: or R1 CIN ≤ R2 Cf Since it is often difficult to know the exact value of CIN, Cf can be experimentally adjusted so that the desired pulse response is achieved. Refer to the LMC660 and the LMC662 for a more detailed discussion on compensating for input capacitance. CAPACITIVE LOAD TOLERANCE Direct capacitive loading will reduce the phase margin of many op-amps. A pole in the feedback loop is created by the combination of the op-amp’s output impedance and the capacitive load. This pole induces phase lag at the unity-gain crossover frequency of the amplifier resulting in either an oscillatory or underdamped pulse response. With a few external components, op amps can easily indirectly drive capacitive loads, as shown in Figure 2. DS011136-5 FIGURE 1. Cancelling the Effect of Input Capacitance 7 www.national.com Applications Hints (Continued) ure 4. To have a significant effect, guard rings should be placed on both the top and bottom of the PC board. This PC foil must then be connected to a voltage which is at the same voltage as the amplifer inputs, since no leakage current can flow between two points at the same potential. For example, a PC board trace-to-pad resistance of 1012Ω, which is normally considered a very large resistance, could leak 5 pA if the trace were a 5V bus adjacent to the pad of the input. This would cause a 100 times degradation from the LMC6041’s actual performance. However, if a guard ring is held within 5 mV of the inputs, then even a resistance of 1011Ω would cause only 0.05 pA of leakage current. See Figure 5 for typical connections of guard rings for standard op-amp configurations. DS011136-6 FIGURE 2. LMC6041 Noninverting Gain of 10 Amplifier, Compensated to Handle Capacitive Loads In the circuit of Figure 2, R1 and C1 serve to counteract the loss of phase margin by feeding the high frequency component of the output signal back to the amplifier’s inverting input, thereby preserving phase margin in the overall feedback loop. Capacitive load driving capability is enhanced by using a pull up resistor to V+ (Figure 3 ). Typically a pull up resistor conducting 10 µA or more will significantly improve capacitive load responses. The value of the pull up resistor must be determined based on the current sinking capability of the amplifier with respect to the desired output swing. Open loop gain of the amplifier can also be affected by the pull up resistor (see Electrical Characteristics). DS011136-7 FIGURE 4. Example of Guard Ring in P.C. Board Layout DS011136-18 FIGURE 3. Compensating for Large Capacitive Loads with a Pull Up Resistor PRINTED-CIRCUIT-BOARD LAYOUT FOR HIGH-IMPEDANCE WORK It is generally recognized that any circuit which must operate with less than 1000 pA of leakage current requires special layout of the PC board. When one wishes to take advantage of the ultra-low bias current of the LMC6041, typically less than 2fA, it is essential to have an excellent layout. Fortunately, the techniques of obtaining low leakages are quite simple. First, the user must not ignore the surface leakage of the PC board, even though it may sometimes appear acceptably low, because under conditions of high humidity or dust or contamination, the surface leakage will be appreciable. To minimize the effect of any surface leakage, lay out a ring of foil completely surrounding the LMC6041’s inputs and the terminals of capacitors, diodes, conductors, resistors, relay terminals, etc. connected to the op-amp’s inputs, as in Figwww.national.com 8 Applications Hints (Continued) Typical Single-Supply Applications (V+ = 5.0 VDC) The extremely high input impedance, and low power consumption, of the LMC6041 make it ideal for applications that require battery-powered instrumentation amplifiers. Examples of these type of applications are hand-held pH probes, analytic medical instruments, magnetic field detectors, gas detectors, and silicon based pressure transducers. DS011136-8 Inverting Amplifier DS011136-12 FIGURE 7. Two Op-Amp Instrumentation Amplifier DS011136-9 Follower DS011136-10 Non-Inverting Amplifier FIGURE 5. Typical Connections of Guard Rings The designer should be aware that when it is inappropriate to lay out a PC board for the sake of just a few circuits, there is another technique which is even better than a guard ring on a PC board: Don’t insert the amplifier’s input pin into the board at all, but bend it up in the air and use only air as an insulator. Air is an excellent insulator. In this case you may have to forego some of the advantages of PC board construction, but the advantages are sometimes well worth the effort of using point-to-point up-in-the-air wiring. See Figure 6. The circuit in Figure 7 is recommended for applications where the common-mode input range is relatively low and the differential gain will be in the range of 10 to 1000. This two op-amp instrumentation amplifier features an independent adjustment of the gain and common-mode rejection trim, and a total quiescent supply current of less than 28 µA. To maintain ultra-high input impedance, it is advisable to use ground rings and consider PC board layout an important part of the overall system design (see Printed-Circuit-Board Layout for High Impedance Work). Referring to Figure 7, the input voltages are represented as a common-mode input VCM plus a differential input VD. Rejection of the common-mode component of the input is accomplished by making the ratio of R1/R2 equal to R3/R4. So that where, A suggested design guideline is to minimize the difference of value between R1 through R4. This will often result in improved resistor tempco, amplifier gain, and CMRR over temperature. If RN = R1 = R2 = R3 = R4 then the gain equation can be simplified: DS011136-11 (Input pins are lifted out of PC board and soldered directly to components. All other pins connected to PC board.) Due to the “zero-in, zero-out” performance of the LMC6041, and output swing rail-rail, the dynamic range is only limited to the input common-mode range of 0V to VS–2.3V, worst case at room temperature. This feature of the LMC6041 makes it an ideal choice for low-power instrumentation systems. A complete instrumentation amplifier designed for a gain of 100 is shown in Figure 8. Provisions have been made for low sensitivity trimming of CMRR and gain. FIGURE 6. Air Wiring 9 www.national.com Typical Single-Supply Applications (V+ = 5.0 VDC) (Continued) DS011136-13 FIGURE 8. Low-Power Two-Op-Amp Instrumentation Amplifier DS011136-14 FIGURE 9. Low-Leakage Sample and Hold DS011136-16 FIGURE 11. 1 Hz Square-Wave Oscillator DS011136-15 FIGURE 10. Instrumentation Amplifier DS011136-17 FIGURE 12. AC Coupled Power Amplifier www.national.com 10 Physical Dimensions inches (millimeters) unless otherwise noted 8-Pin Small Outline Order Number LMC6041AIM or LMC6041IM NS Package Number M08A 8-Pin Molded DIP Order Number LMC6041AIN or LMC6041IN NS Package Number N08E 11 www.national.com LMC6041 CMOS Single Micropower Operational Amplifier Notes LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. National Semiconductor Corporation Americas Tel: 1-800-272-9959 Fax: 1-800-737-7018 Email: support@nsc.com www.national.com National Semiconductor Europe Fax: +49 (0) 1 80-530 85 86 Email: europe.support@nsc.com Deutsch Tel: +49 (0) 1 80-530 85 85 English Tel: +49 (0) 1 80-532 78 32 Français Tel: +49 (0) 1 80-532 93 58 Italiano Tel: +49 (0) 1 80-534 16 80 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. National Semiconductor Asia Pacific Customer Response Group Tel: 65-2544466 Fax: 65-2504466 Email: sea.support@nsc.com National Semiconductor Japan Ltd. Tel: 81-3-5639-7560 Fax: 81-3-5639-7507 National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.