LMH0036

LMH0036 SD SDI Reclocker with 4:1 Input Multiplexer August 19, 2008 LMH0036 SD SDI Reclocker with 4:1 Input Multiplexer General Description The LMH0036 SD SDI Reclocker with 4:1 Input Multiplexer retimes serial digital video data conforming to the SMPTE 259M (C) standard. The LMH0036 operates at the serial data rate of 270 Mbps, and also supports DVB-ASI operation at 270 Mbps. The LMH0036 includes an integrated 4:1 input multiplexer for selecting one of four input data streams for retiming. The LMH0036 retimes the incoming data to suppress accumulated jitter. The LMH0036 recovers the serial data-rate clock and optionally provides it as an output. The LMH0036 has two differential serial data outputs; the second output may be selected as a low-jitter, data-rate clock output. Controls and indicators are: serial clock or second serial data output select, manual rate select input, SD indicator output, lock detect output, auto/manual data bypass, and output mute. The serial data inputs, outputs, and serial data-rate clock outputs are differential LVPECL compatible. The CML serial data and serial data-rate clock outputs are suitable for driving 100Ω differentially terminated networks. The control logic inputs and outputs are LVCMOS compatible. The LMH0036 is powered from a single 3.3V supply. Power dissipation is typically 360 mW. The device is housed in a 48pin LLP package. Features ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ Supports SMPTE 259M (C) serial digital video standard Supports 270 Mbps serial data rate operation Supports DVB-ASI at 270 Mbps Single 3.3V supply operation 360 mW typical power consumption Integrated 4:1 multiplexed input Two differential, reclocked outputs Choice of second reclocked output or low-jitter, differential, data-rate clock output Single 27 MHz external crystal or reference clock input Lock Detect indicator output Output mute function for data and clock Auto/Manual reclocker bypass Differential LVPECL compatible serial data inputs and outputs LVCMOS control inputs and indicator outputs 48-Pin LLP package Industrial temperature range: -40°C to +85°C Footprint compatible with the LMH0056 and LMH0356 Applications ■ SDTV serial digital video interfaces for: — — — — Digital video routers and switchers Digital video processing and editing equipment DVB-ASI equipment Video standards and format converters Typical Application 30003101 © 2008 National Semiconductor Corporation 300031 www.national.com LMH0036 Block Diagram 30003103 www.national.com 2 LMH0036 Connection Diagram 30003102 The exposed die attach pad is the primary negative electrical terminal for this device. It must be connected to the negative power supply voltage. 48-Pin LLP Order Number LMH0036SQ See NS Package Number SQA48A 3 www.national.com LMH0036 Pin Descriptions Pin 1 2 4 5 7 8 10 11 15 16 18 22 24 28 29 32 33 36 37 43 44 45 46 47 48 SDI0 SDI0 SDI1 SDI1 SDI2 SDI2 SDI3 SDI3 BYPASS/AUTO BYPASS OUTPUT MUTE XTAL IN/EXT CLK XTAL OUT LOCK DETECT SCO/SDO2 SCO/SDO2 SDO SDO SD SCO_EN LF1 LF2 NC RSVD SEL0 SEL1 Name Data Input 0 True. Data Input 0 Complement. Data Input 1 True. Data Input 1 Complement Data Input 2 True. Data Input 2 Complement. Data Input 3 True. Data Input 3 Complement. Bypass/Auto Bypass mode select. Bypasses reclocking when high. This pin has an internal pulldown. Data and Clock Output Mute input. Mutes the output when low. This pin has an internal pullup. Crystal or External Oscillator input. Crystal Oscillator output. PLL Lock Detect output (active high). Serial Clock or Serial Data Output 2 complement. Serial Clock or Serial Data Output 2 true. Data Output complement. Data Output true. SD indicator output. Output is high when locked to 270 Mbps. Serial Clock or Serial Data 2 Output select. Sets second output to output the clock when high and the data when low. This pin has an internal pulldown. Loop Filter. Loop Filter. No Connect. Not bonded internally. Reserved. Do not connect or connect to ground. Data Input select input. This pin has an internal pulldown. Data Input select input. This pin has an internal pulldown. Positive power supply input. Description 3, 6, 12, 14, 30, 31, 34, 35 VCC DAP, 13, 17, 19, 20, 21, 23, 25, 26, 27, 38, 39, 40, 41, 42 VEE Negative power supply input. www.national.com 4 LMH0036 Absolute Maximum Ratings (Note 1) It is anticipated that this device will not be offered in a military qualified version. If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. Supply Voltage (VCC–VEE) Logic Supply Voltage (Vi) Logic Input Current (single input): Vi = VEE−0.15V Vi = VCC+0.15V Logic Output Voltage (Vo) Logic Output Source/Sink Current Serial Data Input Voltage (VSDI) Serial Data Output Sink Current (ISDO) Package Thermal Resistance 4.0V VEE−0.15V to VCC +0.15V −5 mA +5 mA VEE−0.15V to VCC +0.15V ±8 mA VCC to VCC−2.0V 24 mA  θJA 48-pin LLP  θJC 48-pin LLP Storage Temp. Range Junction Temperature Lead Temperature (Soldering 4 Sec) ESD Rating (HBM) ESD Rating (MM) ESD Rating (CDM) 26.1°C/W 1.9°C/W −65°C to +150°C +150°C +260°C (Pb-free) 8 kV 400V 1250V Recommended Operating Conditions Supply Voltage (VCC–VEE) Logic Input Voltage Differential Serial Input Voltage Serial Data or Clock Output Sink Current (ISO) Operating Free Air Temperature (TA) 3.3V ±5% VEE to VCC 800 mV ±10% 16 mA max. −40°C to +85°C DC Electrical Characteristics Over Supply Voltage and Operating Temperature ranges, unless otherwise specified. (Notes 2, 3) Symbol VIH VIL IIH IIL VOH VOL VSDID VCMI VSDOD VCMO ICC Parameter Input Voltage High Level Input Voltage Low Level Input Current High Level Input Current Low Level VIH = VCC VIL = VEE All logic level outputs SDI VSDID = 200 mV 100Ω differential load 100Ω differential load 270 Mbps, NTSC color bar pattern SDI SDO, SCO SDO, SCO 2 VEE + 0.6 200 VEE+1.2 720 800 VCC− VSDOD 109 1600 VCC−0.2 880 Conditions Reference Logic level inputs Min 2 VEE 47 −18 Typ Max VCC 0.8 65 −25 Units V V µA µA V V mVP-P V mVP-P V mA Output Voltage High Level IOH = −2 mA Output Voltage Low Level IOL = +2 mA Serial Input Voltage, Differential Input Common Mode Voltage Serial Output Voltage, Differential Output Common Mode Voltage Power Supply Current, 3.3V supply, Total 5 www.national.com LMH0036 AC Electrical Characteristics Over Supply Voltage and Operating Temperature ranges, unless otherwise specified. (Note 3) Symbol BRSD TOLJIT TOLJIT tJIT BWLOOP FCO tJIT Parameter Serial Data Rate Serial Input Jitter Tolerance Serial Input Jitter Tolerance Serial Data Output Jitter Loop Bandwidth Serial Clock Output Frequency Serial Clock Output Jitter Serial Clock Output Alignment with respect to Data Interval Serial Clock Output Duty Cycle TACQ tr, tf tr, tf tr, tf tr, tf FREF FTOL Acquisition Time Input rise/fall time Input rise/fall time Output rise/fall time Output rise/fall time Reference Clock Frequency Ref. Clock Freq. Tolerance (Notes 4, 6) 10%–90% 20%–80% 10%–90% 20%–80%,(Note 5) Logic inputs SDI Logic outputs SCO, SDO 1.5 90 27 ±50 1.5 SDO, SCO 40 SCO 60 % Conditions SMPTE 259M (C) 270 Mbps, (Notes 7, 8, 9) 270 Mbps, (Notes 7, 8, 10) 270 Mbps, (Notes 8, 11) 270 Mbps, 6 >0.6 0.02 300 270 2 3 0.08 Min Typ 270 Max Units Mbps UIP-P UIP-P UIP-P kHz MHz psRMS 45 55 15 3 1500 3 130 % ms ns ps ns ps MHz ppm Note 1: “Absolute Maximum Ratings” are those parameter values beyond which the life and operation of the device cannot be guaranteed. The stating herein of these maximums shall not be construed to imply that the device can or should be operated at or beyond these values. The table of “Electrical Characteristics” specifies acceptable device operating conditions. Note 2: Current flow into device pins is defined as positive. Current flow out of device pins is defined as negative. All voltages are referenced to VEE (equal to zero volts). Note 3: Typical values are stated for: VCC = +3.3V, TA = +25°C. Note 4: Specification is guaranteed by design. Note 5: RL = 100Ω differential. Note 6: Measured from first SDI transition until Lock Detect (LD) output goes high (true). Note 7: Peak-to-peak amplitude with sinusoidal modulation per SMPTE RP 184-1996 paragraph 4.1. The test data signal shall be color bars. Note 8: This parameter is guaranteed by characterization over voltage and temperature limits. Note 9: Refer to “A1” in Figure 1 of SMPTE RP 184-1996. Note 10: Refer to “A2” in Figure 1 of SMPTE RP 184-1996. Note 11: Serial Data Output Jitter is total output jitter with 0.2UIP-P input jitter. www.national.com 6 LMH0036 Device Description The LMH0036 SD SDI Reclocker with 4:1 Input Multiplexer is used in many types of digital video signal processing equipment. The LMH0036 supports the SMPTE 259M (C) standard, with a corresponding serial data rate of 270 Mbps. DVBASI data at 270 Mbps may also be retimed. The LMH0036 retimes the serial data stream to suppress accumulated jitter. It provides two low-jitter, differential, serial data outputs. The second output may be selected to output either serial data or a low-jitter serial data-rate clock. Controls and indicators are: serial data-rate clock or second serial data output select, manual rate select input, SD indicator output, lock detect output, auto/manual data bypass and output mute. Serial data inputs are CML and LVPECL compatible. Serial data and data-rate clock outputs are differential CML and produce LVPECL compatible levels. The output buffer design can drive AC or DC-coupled, terminated 100Ω differential loads. The differential output level is 800 mVP-P ±10% into 100Ω AC or DC-coupled differential loads. Logic inputs and outputs are LVCMOS compatible. The device package is a 48–pin LLP with an exposed die attach pad. The exposed die attach pad is electrically connected to device ground (VEE) and is the primary negative electrical terminal for the device. This terminal must be connected to the negative power supply or circuit ground. Serial Data Inputs, Serial Data and Clock Outputs SERIAL DATA INPUT AND OUTPUTS The differential serial data inputs, SDI0-SDI3, accept 270 Mbps serial digital video data. The serial data inputs are dif- ferential LVPECL compatible. These inputs are intended to be DC interfaced to devices such as the LMH0074 adaptive cable equalizer. These inputs are not internally terminated or biased. The inputs may be AC-coupled if a suitable input bias voltage is provided. The LMH0036 provides four independent, multiplexed data inputs. The active input channel is selected via the SEL0 and SEL1 pins, as shown in Table 1. Figure 1 shows the equivalent input circuit for SDI[3:0] and SDI[3:0]. The LMH0036 has two, retimed, differential, serial data outputs, SDO and SCO/SDO2. These outputs provide low jitter, differential, retimed data to devices such as the LMH0001 or LMH0002 cable driver. Output SCO/SDO2 is multiplexed and can provide either a second serial data output or a serial datarate clock output. Figure 2 shows the equivalent output circuit for SDO, SDO, SCO/SDO2, and SCO/SDO2. The SCO_EN input controls the operating mode for the SCO/ SDO2 output. When the SCO_EN input is high the SCO/ SDO2 output provides a serial data-rate clock. When SCO_EN is low, the SCO/SDO2 output provides retimed serial data. Both differential serial data outputs, SDO and SCO/SDO2, are muted when the OUTPUT MUTE input is a logic low level. SCO/SDO2 also mutes when the Bypass mode is activated when this output is operating as the serial clock output. When muted, SDO and SDO (or SDO2 and SDO2) will assume opposite differential output levels. The CML serial data outputs are differential LVPECL compatible. These outputs have internal 50Ω pull-ups and are suitable for driving AC or DCcoupled, 100Ω center-tapped, AC grounded or 100Ω uncenter-tapped, differentially terminated networks. 30003108 FIGURE 1. Equivalent SDI Input Circuit (SDI[3:0], SDI[3:0]) 7 www.national.com LMH0036 30003109 FIGURE 2. Equivalent SDO Output Circuit (SDO, SDO, SCO/SDO2, SCO/SDO2) SERIAL DATA CLOCK/SERIAL DATA 2 OUTPUT The Serial Data Clock/Serial Data 2 Output is controlled by the SCO_EN input and provides either a second retimed serial data output or a low jitter differential clock output appropriate to the serial data rate being processed. When operating as a serial clock output, the rising edge of the clock will be positioned within the corresponding serial data bit interval within 10% of the center of the data interval. Differential output SCO/SDO2 functions as the second serial data output when the SCO_EN input is a logic-low level. This output functions as the serial data-rate clock output when the SCO_EN input is a logic-high level. The SCO_EN input has an internal pull-down device and the default state of SCO_EN is low (serial data output 2 enabled). SCO/SDO2 is muted when the OUTPUT MUTE input is a logic low level. When the Bypass mode is activated and this output is functioning as a serial clock output, the output will also be muted. If an unsupported data rate is used while in Auto Bypass mode with this output functioning as a serial clock output, the output is invalid. LOCK DETECT The Lock Detect (LD) output, when high, indicates that data is being received and the PLL is locked. LD may be connected to the OUTPUT MUTE input to mute the data and clock outputs when no data signal is being received. Note that when the Bypass/Auto Bypass input is set high, Lock Detect will remain low. See Table 2. OUTPUT MUTE The OUTPUT MUTE input, when low, mutes the serial data and clock outputs. It may be connected to Lock Detect or externally driven to mute or un-mute the outputs. If OUTPUT MUTE is connected to LD, then the data and clock outputs are muted when the PLL is not locked. This function overrides the Bypass function: see Table 2. OUTPUT MUTE has an internal pull-up device to enable the output by default. BYPASS/AUTO BYPASS The Bypass/Auto Bypass input, when high, forces the device to output the data without reclocking it. When this input is low, the device automatically bypasses the reclocking function when the device is in an unlocked condition or the detected data rate is a rate which the device does not support. Note that when the Bypass/Auto Bypass input is set high, Lock Detect will remain low. See Table 2. BYPASS/AUTO BYPASS has an internal pull-down device. Control Inputs and Indicator Outputs SERIAL DATA INPUT SELECTOR The Serial Data Input Selector (SEL [1:0]) allows the user to select the active input channel. Table 1 shows the input selected for a given state of SEL [1:0]. TABLE 1. Data Input Select Codes SEL [1:0] Code 00 01 10 11 Selected Input SDI0 SDI1 SDI2 SDI3 www.national.com 8 LMH0036 TABLE 2. Control Functionality LOCK DETECT 0 1 X 0 1 OUTPUT MUTE 1 1 0 LOCK DETECT LOCK DETECT BYPASS/AUTO BYPASS X 0 X X 0 DEVICE STATUS PLL unlocked, reclocker bypassed PLL locked to supported data rate, reclocker not bypassed Outputs muted Outputs muted PLL locked to supported data rate, reclocker not bypassed is locked and the Lock Detect output is high. The SD output is undefined for a short time after lock detect assertion or deassertion due to a data change on the SDI input. See Figure 3 for a timing diagram showing the relationship between SDI, Lock Detect, and SD. SD The SD output indicates that the LMH0036 is locked and processing SD data rates. It may be used to control another device such as the LMH0002 cable driver. When this output is high it indicates that the data rate is 270 Mbps. The SD output is a registered function and is only valid when the PLL 30003105 FIGURE 3. SDI, Lock Detect, and SD Timing SCO_EN Input SCO_EN enables the SCO/SDO2 differential output to function either as a serial data-rate clock or second serial data output. SCO/SDO2 functions as a serial data-rate clock when SCO_EN is high. This pin has an internal pull-down device. The default state (low) enables the SCO/SDO2 output as a second serial data output. CRYSTAL OR EXTERNAL CLOCK REFERENCE The LMH0036 uses a 27 MHz crystal or external clock signal as a timing reference input. A 27 MHz parallel resonant crystal and load network may be connected to the XTAL IN/EXT CLK and XTAL OUT pins. Alternatively, a 27 MHz LVCMOS compatible clock signal may be input to XTAL IN/EXT CLK. Parameters for a suitable crystal are given in Table 3. TABLE 3. Crystal Parameters Parameter Frequency Frequency Stability 27 MHz ±100 ppm @ recommended drive level Value Parameter Operating Mode Load Capacitance Shunt Capacitance Series Resistance Recommended Drive Level Maximum Drive Level Operating Temperature Range Value Fundamental mode, Parallel Resonant 20 pF 7 pF 40Ω max. 100 µW 500 µW −10°C to +60°C 9 www.national.com LMH0036 Application Information Figure 4 shows a application circuit for the LMH0036. 30003104 FIGURE 4. Application Circuit BYPASS/AUTO BYPASS has an internal pulldown to enable Auto Bypass mode by default. This pin may be pulled high to force the LMH0036 to bypass all data. OUTPUT MUTE has an internal pullup to enable the outputs by default. This pin may be pulled low to mute the outputs. The XTAL IN/EXT CLK and XTAL OUT pins are shown with a 27 MHz crystal and the proper loading. The crystal should match the parameters described in Table 3. Alternately, a 27MHz LVCMOS compatible clock signal may be input to XTAL IN/EXT CLK. The active high LOCK DETECT output provides an indication that proper data is being received and the PLL is locked. The SD output may be used to drive the SD/HD pin of an SDI cable driver (such as the LMH0002) in order to properly set the cable driver’s edge rate for SMPTE compliance. It defaults to low when the LMH0036 is not locked. SCO_EN has an internal pulldown to set the second output (SCO/SDO2) to output data. This pin may be pulled high to set the second output as a serial clock. The external loop filter capacitor (between LF1 and LF2) should be 56 nF. This is the only supported value; the loop filter capacitor should not be changed. SEL0 and SEL1 have internal pulldowns to select the SDI0 input by default. The inputs are LVPECL compatible. The LMH0036 has a wide input common mode range and in most cases the input should be DC coupled. For DC coupling, the inputs must be kept within the common mode range specified in DC Electrical Characteristics. Figure 5 shows an example of a DC coupled interface between the LMH0074 cable equalizer and the LMH0036. The LMH0074 output common mode voltage and voltage swing are within the range of the input common mode voltage and voltage swing of the LMH0036. All that is required is a 100Ω differential termination as shown. The resistor should be placed as close as possible to the LMH0036 input. If desired, this network may be terminated with two 50Ω resisters and a center tap capacitor to ground in place of the single 100Ω resistor. 10 www.national.com LMH0036 The outputs are LVPECL compatible. SDO is the primary data output and SCO/SDO2 is a second output that may be set as the serial clock or a second data output. Both outputs are always active. The LMH0036 output should be DC coupled to the input of the receiving device as long as the common mode ranges of both devices are compatible. Figure 6 shows an example of a DC coupled interface between the LMH0036 and LMH0001 cable driver. All that is required is a 100Ω differential termination as shown. The re- sistor should be placed as close to the LMH0302 input as possible. If desired, this network may be terminated with two 50Ω resisters and a center tap capacitor to ground in place of the single 100Ω resistor. The LMH0036 has multiple ground connections, however; the primary ground connection is through the large exposed DAP. The DAP must be connected to ground for proper operation of the LMH0036. 30003106 FIGURE 5. DC Input Interface 30003107 FIGURE 6. DC Output Interface 11 www.national.com LMH0036 Physical Dimensions inches (millimeters) unless otherwise noted 48-Pin LLP Order Number LMH0036SQ NS Package Number SQA48A www.national.com 12 LMH0036 Notes 13 www.national.com LMH0036 SD SDI Reclocker with 4:1 Input Multiplexer Notes For more National Semiconductor product information and proven design tools, visit the following Web sites at: Products Amplifiers Audio Clock Conditioners Data Converters Displays Ethernet Interface LVDS Power Management Switching Regulators LDOs LED Lighting PowerWise Serial Digital Interface (SDI) Temperature Sensors Wireless (PLL/VCO) www.national.com/amplifiers www.national.com/audio www.national.com/timing www.national.com/adc www.national.com/displays www.national.com/ethernet www.national.com/interface www.national.com/lvds www.national.com/power www.national.com/switchers www.national.com/ldo www.national.com/led www.national.com/powerwise www.national.com/sdi www.national.com/tempsensors www.national.com/wireless WEBENCH Analog University App Notes Distributors Green Compliance Packaging Design Support www.national.com/webench www.national.com/AU www.national.com/appnotes www.national.com/contacts www.national.com/quality/green www.national.com/packaging www.national.com/quality www.national.com/refdesigns www.national.com/feedback Quality and Reliability Reference Designs Feedback THE CONTENTS OF THIS DOCUMENT ARE PROVIDED IN CONNECTION WITH NATIONAL SEMICONDUCTOR CORPORATION (“NATIONAL”) PRODUCTS. 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