LP38512_09

LP38512-1.8 1.5A Fast-Transient Response Low-Dropout Linear Voltage Regulator March 6, 2009 LP38512-1.8 1.5A Fast-Transient Response Low-Dropout Linear Voltage Regulator with Error Flag General Description The LP38512-1.8 Fast-Transient Response Low-Dropout Voltage Regulator offers the highest-performance in meeting AC and DC accuracy requirements for powering Digital Cores. The LP38512-1.8 uses a proprietary control loop that enables extremely fast response to change in line conditions and load demands. Output Voltage DC accuracy is guaranteed at 2.5% over line, load and full temperature range from -40°C to +125°C. The LP38512-1.8 is designed for inputs from the 2.5V, 3.3V, and 5.0V rail, is stable with 10 μF ceramic capacitors, and has a fixed 1.8V output. An Error Flag feature monitors the output voltage and notifies the system processor when the output voltage falls more than 15% below the nominal value. The LP38512-1.8 provides excellent transient performance to meet the demand of high performance digital core ASICs, DSPs, and FPGAs found in highly-intensive applications such as servers, routers/switches, and base stations. Features ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ 2.25V to 5.5V Input Voltage Range 1.8V Fixed Output Voltage 1.5A Output Load Current ±2.5% Accuracy over Line, Load, and Full-Temperature Range from -40°C to +125°C Stable with tiny 10 µF ceramic capacitors 0.20% Output Voltage Load Regulation from 10 mA to 1.5A Enable pin Error Flag Indicates Status of Output Voltage 1uA of Quiescent current in Shutdown 40dB of PSRR at 100 kHz Over-Temperature and Over-Current Protection TO-263 and TO-263 THIN Surface Mount Packages Applications ■ ■ ■ ■ ■ ■ Digital Core ASICs, FPGAs, and DSPs Servers Routers and Switches Base Stations Storage Area Networks DDR2 Memory Typical Application Circuit 20183001 © 2009 National Semiconductor Corporation 201830 www.national.com LP38512-1.8 Ordering Information TABLE 1. Package Marking and Ordering Information Output Voltage 1.8 Order Number LP38512TJ-1.8 LP38512TS-1.8 LP38512TSX-1.8 Package Type TO263-5 THIN TO263-5 TO263-5 Package Marking LP38512TJ-1.8 LP38512TS-1.8 LP38512TS-1.8 Supplied As: Tape and Reel Rail Tape and Reel Connection Diagrams 20183004 20183005 Top View TO-263 5 Pin Package Top View TO-263 THIN 5 Pin Package Pin Descriptions for TO-263 and TO-263 THIN Packages Pin # 1 2 3 4 5 Pin Name EN IN GND OUT ERROR Function Enable. Pull high to enable the output, low to disable the output. This pin has no internal bias and must be tied to the input voltage, or actively driven. Input Supply Pin Ground Regulated Output Voltage Pin ERROR Flag. A high level indicates that VOUT is within typically 15% (VOUT falling) of the nominal regulated voltage. The TO-263 TAB, and the TO-263 THIN DAP, is used as a thermal connection to remove heat from the device to an external heatsink. The TAB/DAP is internally connected to device pin 3, and is electrical ground connection. TAB/DAP TAB/DAP www.national.com 2 LP38512-1.8 Absolute Maximum Ratings (Note 1) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Storage Temperature Range Soldering Temperature (Note 3) TO-220, Wave TO-263 ESD Rating (Note 2) Power Dissipation(Note 4) Input Pin Voltage (Survival) Enable Pin Voltage (Survival) Output Pin Voltage (Survival) ERROR Pin Voltage (Survival) IOUT(Survival) −65°C to +150°C 260°C, 10s 235°C, 30s ±2 kV Internally Limited −0.3V to +6.0V −0.3V to +6.0V −0.3V to +6.0V 0.3V to +6.0V Internally Limited Operating Ratings Input Supply Voltage, VIN Enable Input Voltage, VEN ERROR Pin Voltage Output Current (DC) Junction Temperature (Note 4) (Note 1) 2.25V to 5.5V 0.0V to 5.5V 0.0V to VIN 0 mA to 1.5A −40°C to +125°C Electrical Characteristics Unless otherwise specified: VIN = 2.5V, IOUT = 10 mA, CIN = 10 µF, COUT = 10 µF, VEN = VIN. Limits in standard type are for TJ = 25°C only; limits in boldface type apply over the junction temperature (TJ) range of -40°C to +125°C. Minimum and Maximum limits are guaranteed through test, design, or statistical correlation. Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for reference purposes only. Symbol VOUT ΔVOUT/ΔVIN Parameter Output Voltage Tolerance (Note 7) Output Voltage Line Regulation (Notes 5, 7) Output Voltage Load Regulation (Notes 6, 7) Dropout Voltage (Note 8) Ground Pin Current, Output Enabled Ground Pin Current, Output Disabled ISC Enable Input VEN(ON) VEN(OFF) VEN(HYS) td(OFF) td(ON) IEN Enable ON Threshold Enable OFF Threshold Enable Hysteresis Turn-off delay Turn-on delay Enable Pin Current VEN rising from 0.50V until VOUT = ON VEN falling from 1.60V until VOUT = OFF VEN(ON) - VEN(OFF) Time from VEN < VEN(OFF) to VOUT = OFF, ILOAD = 1.5A Time from VEN >VEN(ON) to VOUT = ON, ILOAD = 1.5A VEN = VIN VEN = 0V 0.90 0.80 0.60 0.50 1.20 1.00 200 1 25 1 -1 1.50 1.60 1.40 1.50 µs nA mV V Short Circuit Current Conditions 2.25V ≤ VIN ≤ 5.5V 10 mA ≤ IOUT ≤ 1.5A Min -1.0 −2.5 Typ 0 0.02 0.06 0.25 0.40 250 7.5 9.5 0.1 2.5 Max +1.0 +2.5 Units % 2.25V ≤ VIN ≤ 5.5V %/V ΔVOUT/ΔIOUT VDO 10 mA ≤ IOUT ≤ 1.5A IOUT = 1.5A IOUT = 10 mA ERROR pin = GND IOUT = 1.5A ERROR pin = GND VEN = 0.50V ERROR pin = GND VOUT = 0V - 340 400 11 12 13 14 3.5 12 - %/A - mV mA IGND µA A 3 www.national.com LP38512-1.8 Symbol ERROR Flag Parameter Conditions VOUT rising threshold where ERROR Flag goes high VOUT falling threshold where ERROR Flag goes low ISINK = 100 µA VERROR = 5.5V Min Typ Max Units VTH Error Flag Threshold (Note 9) ERROR Flag Saturation Voltage ERROR Flag Pin Leakage Current ERROR Flag Delay time 78 74 - 90 85 12.5 1 1 98 % 93 45 mV nA µs VERROR(SAT) Ilk td AC Parameters VIN = 2.5V f = 120Hz VIN = 2.5V f = 1 kHz f = 120Hz BW = 100Hz – 100kHz TJ rising 73 73 2 75 165 10 60 dB nV/√Hz µV (RMS) PSRR Ripple Rejection en Output Noise Density Output Noise Voltage Thermal Shutdown Thermal Resistance Junction to Ambient (Note 4) Thermal Resistance Junction to Case Thermal Characteristics TSD ΔTSD θJ-A θJ-C Thermal Shutdown Hysteresis TJ falling from TSD TO-263 and TO-263 THIN °C °C/W TO-263 and TO-263 THIN - 3 - °C/W Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is intended to be functional, but does not guarantee specific performance limits. For guaranteed specifications and conditions, see the Electrical Characteristics. Note 2: The human body model is a 100pF capacitor discharged through a 1.5kΩ resistor into each pin. Test method is per JESD22-A114. Note 3: Refer to JEDEC J-STD-020C for surface mount device (SMD) package reflow profiles and conditions. Unless otherwise stated, the temperatures and times are for Sn-Pb (STD) only. Note 4: Device operation must be evaluated, and derated as needed, based on ambient temperature (TA), power dissipation (PD), maximum allowable operating junction temperature (TJ(MAX)), and package thermal resistance (θJA). Note 5: Output voltage line regulation is defined as the change in output voltage from the nominal value (ΔVOUT) due to a change in the voltage at the input (ΔVIN). Note 6: Output voltage load regulation is defined as the change in output voltage from the nominal value (ΔVOUT) due to a change in the load current at the output (ΔIOUT). Note 7: The line and load regulation specification contains only the typical number. However, the limits for line and load regulation are included in the output voltage tolerance specification. Note 8: Dropout voltage is defined as the minimum input to output differential voltage at which the output drops 2% below the nominal value. For the LP38512-1.8 the minimum VIN operating voltage is the limiting factor. Note 9: The ERROR Flag thresholds are specified as percentage of the nominal regulated output voltage. See Application Information. www.national.com 4 LP38512-1.8 Typical Performance Characteristics CIN = 10 µF, COUT = 10 µF, IOUT = 10 mA. VOUT vs Temperature Unless otherwise specified: TJ = 25°C, VIN = 2.5V, VEN = VIN, VOUT vs VIN 20183011 20183037 Ground Pin Current (IGND) vs VIN Ground Pin Current (IGND) vs Temperature 20183012 20183013 Ground Pin Current(IGND) vs Temperature, VEN = 0.5V Enable Thresholds vs Temperature 20183014 20183016 5 www.national.com LP38512-1.8 VOUT vs VEN (td(ON)) VOUT vs VEN (td(OFF)) 20183032 20183030 VOUT ERROR Flag Threshold vs Temperature ERROR Flag Low vs Temperature 20183017 20183018 Load regulation vs Temperature Line Regulation vs Temperature 20183020 20183021 www.national.com 6 LP38512-1.8 Current Limit vs Temperature Load Transient, 10 mA to 1.5A COUT = 10 μF Ceramic 20183022 20183023 Load Transient, 10 mA to 1.5A COUT = 10 µF Ceramic + 100 µF Aluminum Load Transient, 500 mA to 1.5A COUT = 10 µF Ceramic 20183024 20183025 Load Transient, 500 mA to 1.5A COUT = 10 μF Ceramic + 100 µF Aluminum Line Transient 20183027 20183026 7 www.national.com LP38512-1.8 PSRR, 10Hz to 1MHz Noise 20183029 20183031 www.national.com 8 LP38512-1.8 Block Diagram 20183007 Application Information EXTERNAL CAPACITORS Like any low-dropout regulator, external capacitors are required to assure stability. These capacitors must be correctly selected for proper performance. Input Capacitor A ceramic input capacitor of at least 10 µF is required. For general usage across all load currents and operating conditions, a 10 µF ceramic input capacitor will provide satisfactory performance. Output Capacitor A ceramic capacitor with a minimum value of 10 µF is required at the output pin for loop stability. It must be located less than 1 cm from the device and connected directly to the output and ground pin using traces which have no other currents flowing through them. As long as the minimum of 10 µF ceramic is met, there is no limitation on any additional capacitance. X7R and X5R dielectric ceramic capacitors are strongly recommended, as they typically maintain a capacitance range within ±20% of nominal over full operating ratings of temperature and voltage. Of course, they are typically larger and more costly than Z5U/Y5U types for a given voltage and capacitance. Z5U and Y5V dielectric ceramics are not recommended as the capacitance will drops severely with applied voltage. A typical Z5U or Y5V capacitor can lose 60% of its rated capacitance with half of the rated voltage applied to it. The Z5U and Y5V also exhibit a severe temperature effect, losing more than 50% of nominal capacitance at high and low limits of the temperature range. REVERSE VOLTAGE A reverse voltage condition will exist when the voltage at the output pin is higher than the voltage at the input pin. Typically this will happen when VIN is abruptly taken low and COUT continues to hold a sufficient charge such that the input to output voltage becomes reversed. A less common condition is when an alternate voltage source is connected to the output. There are two possible paths for current to flow from the output pin back to the input during a reverse voltage condition. While VIN is high enough to keep the control circuity alive, and the Enable pin is above the VEN(ON) threshold, the control circuitry will attempt to regulate the output voltage. Since the input voltage is less than the output voltage the control circuit will drive the gate of the pass element to the full on condition when the output voltage begins to fall. In this condition, reverse current will flow from the output pin to the input pin, limited only by the RDS(ON) of the pass element and the output to input voltage differential. Discharging an output capacitor up to 1000 µF in this manner will not damage the device as the current will rapidly decay. However, continuous reverse current should be avoided. The internal PFET pass element in the LP38512 has an inherent parasitic diode. During normal operation, the input voltage is higher than the output voltage and the parasitic diode is reverse biased. However, if the output voltage to input voltage differential is more than 500 mV (typical) the parasitic diode becomes forward biased and current flows from the output pin to the input through the diode. The current in the parasitic diode should limited to less than 1A continuous and 5A peak. If used in a dual-supply system where the regulator output load is returned to a negative supply, the output pin must be diode clamped to ground. A Schottky diode is recommended for this protective clamp. SHORT-CIRCUIT PROTECTION The LP38512 is short circuit protected, and in the event of a peak over-current condition the short-circuit control loop will rapidly drive the output PMOS pass element off. Once the power pass element shuts down, the control loop will rapidly cycle the output on and off until the average power dissipation causes the thermal shutdown circuit to respond to servo the 9 www.national.com LP38512-1.8 on/off cycling to a lower frequency. Please refer to the POWER DISSIPATION/HEATSINKING section for power dissipation calculations. ENABLE OPERATION The Enable ON threshold is typically 1.2V, and the OFF threshold is typically 1.0V. To ensure reliable operation the Enable pin voltage must rise above the maximum VEN(ON) threshold and must fall below the minimum VEN(OFF) threshold. The Enable threshold has typically 200mV of hysteresis to improve noise immunity. The Enable pin (EN) has no internal pull-up or pull-down to establish a default condition and, as a result, this pin must be terminated either actively or passively. If the Enable pin is driven from a single ended device (such as discrete transistor) a pull-up resistor to VIN, or a pull-down resistor to ground, will be required for proper operation. A 1 kΩ to 100 kΩ resistor can be used as the pull-up or pulldown resistor to establish default condition for the EN pin. The resistor value selected should be appropriate to swamp out any leakage in the external single ended device, as well as any stray capacitance. If the Enable pin is driven from a source that actively pulls high and low (such as a CMOS rail to rail comparator output), the pull-up, or pull-down, resistor is not required. If the application does not require the Enable function, the pin should be connected to directly to the adjacent VIN pin. The status of the Enable pin also affects the behavior of the ERROR Flag. While the Enable pin is high the regulator con- trol loop will be active and the ERROR Flag will report the status of the output voltage. When the Enable pin is taken low the regulator control loop is shutdown, the output is turned off, and the ERROR Flag pin is immediately forced low. ERROR FLAG OPERATION When the LP38512 Enable pin is high, the ERROR Flag pin will produce a logic low signal when the output drops by more than 15% (typical) from the nominal output voltage. The drop in output voltage may be due to low input voltage, current limiting, or thermal limiting. This flag has a built in hysteresis. The output voltage will need to rise to within 10% (typical) of the nominal output voltage for the ERROR Flag to return to a logic high state. It should also be noted that when the Enable pin is pulled low, the ERROR Flag pin is forced to be low as well. The internal ERROR flag comparator has an open drain output stage. Hence, the ERROR pin requires an external pull-up resistor. The value of the pull-up resistor should be in the range of 10 kΩ to 1 MΩ. The ERROR Flag pin should not be pulled-up to any voltage source higher than VIN as current flow through an internal parasitic diode may cause unexpected behavior. The ERROR Flag must be connected to ground if this function is not used. The timing diagram in Figure 1 shows the relationship between the ERROR flag and the output voltage. 20183008 FIGURE 1. ERROR Flag Operation, see Typical Application www.national.com 10 LP38512-1.8 20183034 FIGURE 2. ERROR Flag Operation, biased from VIN POWER DISSIPATION/HEATSINKING A heatsink may be required depending on the maximum power dissipation (PD(MAX)), maximum ambient temperature (TA(MAX)) of the application, and the thermal resistance (θJA) of the package. Under all possible conditions, the junction temperature (TJ) must be within the range specified in the Operating Ratings. The total power dissipation of the device is given by: PD = ( (VIN−VOUT) x IOUT) + (VIN x IGND) (1) where IGND is the operating ground current of the device (specified under Electrical Characteristics). The maximum allowable junction temperature rise (ΔTJ) depends on the maximum expected ambient temperature (TA (MAX)) of the application, and the maximum allowable junction temperature (TJ(MAX)): ΔTJ = TJ(MAX)− TA(MAX) (2) 20183035 FIGURE 3. θJA vs Copper (1 Ounce) Area for TO-263 package As shown in the figure, increasing the copper area beyond 1 square inch produces very little improvement. The minimum value for θJA for the TO-263 package mounted to a two-layer PCB is 32°C/W. Figure 4 shows the maximum allowable power dissipation for TO-263 packages for different ambient temperatures, assuming θJA is 35°C/W and the maximum junction temperature is 125°C. The maximum allowable value for junction to ambient Thermal Resistance, θJA, can be calculated using the formula: θJA = ΔTJ / PD(MAX) (3) HEATSINKING TO-263 PACKAGE The TO-263 and the TO-263 THIN packages use the copper plane on the PCB as a heatsink. The tab, or DAP, of these packages are soldered to the copper plane for heat sinking. Figure 3 shows a curve for the θJA of TO-263 package for different copper area sizes, using a typical PCB with 1 ounce copper and no solder mask over the copper area for heat sinking. 20183036 FIGURE 4. Maximum Power Dissipation vs Ambient Temperature for TO-263 Package 11 www.national.com LP38512-1.8 Physical Dimensions inches (millimeters) unless otherwise noted TO-263, Molded, 5-Lead, 0.067in (1.7mm) Pitch, Surface Mount Package NS Package Number TS5B TO-263 THIN, Molded, 5-Lead, 1.7mm Pitch, Surface Mount Package NS Package Number TJ5A www.national.com 12 LP38512-1.8 Notes 13 www.national.com LP38512-1.8 1.5A Fast-Transient Response Low-Dropout Linear Voltage Regulator Notes For more National Semiconductor product information and proven design tools, visit the following Web sites at: Products Amplifiers Audio Clock and Timing Data Converters Interface LVDS Power Management Switching Regulators LDOs LED Lighting Voltage Reference PowerWise® Solutions Serial Digital Interface (SDI) Temperature Sensors Wireless (PLL/VCO) www.national.com/amplifiers www.national.com/audio www.national.com/timing www.national.com/adc www.national.com/interface www.national.com/lvds www.national.com/power www.national.com/switchers www.national.com/ldo www.national.com/led www.national.com/vref www.national.com/powerwise www.national.com/sdi www.national.com/tempsensors www.national.com/wireless WEBENCH® Tools App Notes Reference Designs Samples Eval Boards Packaging Green Compliance Distributors Design Support www.national.com/webench www.national.com/appnotes www.national.com/refdesigns www.national.com/samples www.national.com/evalboards www.national.com/packaging www.national.com/quality/green www.national.com/contacts www.national.com/quality www.national.com/feedback www.national.com/easy www.national.com/solutions www.national.com/milaero www.national.com/solarmagic www.national.com/AU Quality and Reliability Feedback/Support Design Made Easy Solutions Mil/Aero SolarMagic™ Analog University® THE CONTENTS OF THIS DOCUMENT ARE PROVIDED IN CONNECTION WITH NATIONAL SEMICONDUCTOR CORPORATION (“NATIONAL”) PRODUCTS. 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