LP8720TLX

LP8720 One Step-Down DC/DC and Five Linear Regulators with I2C Compatible Interface November 30, 2009 LP8720 One Step-Down DC/DC and Five Linear Regulators with I2C Compatible Interface General Description The LP8720 is a multi-function, programmable Power Management Unit, optimized for sub block power requirement solution. This device integrates one highly efficient 400 mA step-down DC/DC converter with Dynamic Voltage Scale (DVS), five low noise low dropout (LDO) voltage regulators and a 400 KHz I2C-compatible interface to allow a host controller access to the internal control registers of the LP8720. The LP8720 additionally features programmable power-on sequencing. LDO regulators provide high PSRR and low noise ideally suited for supplying power to both analog and digital loads. The package will be the smallest 2.5 mm x 2.0 mm micro SMD 20–bump package. Features Regulator, IOUT 400 mA High efficiency PFM mode @low IOUT Auto Mode PFM/PWM switch Low inductance 2.2 µH @ 2 MHz clock Dynamic Voltage Scale control ■ I2C-compatible interface for the controlling of internal registers ■ 20–bump 2.5 x 2.0 mm micro SMD package ■ 5 Low Noise LDO’s for up to 300 mA ■ One high-efficiency Synchronous Magnetic Buck Key Specifications ■ ■ ■ ■ Programmable Vout from 0.8V to 2.3V on DC/DC Automatic soft start on DC/DC 200 mV typ Dropout Voltage at 300 mA on LDO’s 2% (typ) Output Voltage accuracy on LDO’s Applications ■ Cellular Handsets ■ Portable hand-held products Typical Application Diagram 30067501 © 2009 National Semiconductor Corporation 300675 www.national.com LP8720 Device Pin Diagram (Micro SMD 20) TOP VIEW 30067502 Package Marking Information 30067503 Ordering Information Order Number LP8720TLE LP8720TLX Package Type micro SMD micro SMD Product Identification 8720 8720 Supplied as 250 Tape & Reel 3000 Tape & Reel Upon request there will be available custom versions – customer can order own default voltages and own startup sequence. For more information please contact local National Semiconductor Corp. sales office. www.national.com 2 LP8720 LP8720 Pin Descriptions Pin Number A4 E4 A2 D1 B4 A3 A1 C1 E1 E3 D2 D4 B1 C4 C3 B3 E2 B2 Name VBATT VINB VIN1 VIN2 LDO1 LDO2 LDO3 LDO4 LDO5 SW FB GNDB GND SDA SCL IRQ_N EN DEFSEL Type P P P P A A A A A A A G G DI/O DI DO DI DI Description Battery Input for LDO1 and all internal circuitry. Battery Input for Buck. Battery Input for LDO2 and LDO3. Battery Input for LDO4 and LDO5. LDO1 Output. LDO2 Output. LDO3 Output. LDO4 Output. LDO5 Output. Buck Output. Buck Feedback. Power Ground for Buck. IC Ground. I2C-compatible Serial Interface Data Input/Output. Open Drain output, external pull up resistor is needed, typ 1.5 kΩ. If not in use then hard wire to GND. I2C-compatible Serial Interface Clock input. External pull up resistor is needed, typ 1.5 kΩ. If not in use then hard wire to GND. Interrupt output, active LOW. Open Drain output, external pull up resistor is needed, typ 10 kΩ. If not in use then hard wire to GND or leave floating. Enable. EN=LO standby. EN=HI power on. Internal pull down resistor 500 kΩ. If not in use then hard wire to VBATT. Control input that sets the default voltages and startup sequence. Must be hard wired to BATT or GND or left floating (Hi-Z) for specific application. When DEFSEL= VBATT then setup 1 is used for default voltages and startup sequence. When DEFSEL= GND then setup 2 is used for default voltages and startup sequence. When DEFSEL= floating (Hi-Z) setup 3 is used for default voltages and startup sequence. Control input that sets the slave address for serial interface. Must be hard wired to BATT or GND or left floating (Hi-Z) for specific application. When IDSEL= VBATT then slave address is 7h’7F When IDSEL= floating (Hi-Z) then slave address is 7h’7C When IDSEL= GND then slave address is 7h’7D Dynamical Voltage Scaling. When DVS=HI then Buck voltage set BUCK_V1 is in use. When DVS=LO then Buck voltage set BUCK_V2 is in use. Buck voltage set BUCK_V1 should be higher than Buck voltage set BUCK_V2. If not in use then hard wire to VBATT or GND. C2 IDSEL DI D3 DVS DI A: D I DI/O G O P Analog Pin Digital Pin Input Pin Digital Input/Output Pin Ground Output Pin Power Connection 3 www.national.com LP8720 Device Description OPERATION MODES POWER-ON-RESET: After VBATT gets above POR higher threshold DEFSEL-pin and IDSEL-pin are read. Then all internal registers of LP8720 are reset to the default values and after that LP8720 goes to STANDBY mode. This process duration max is 500 µs. STANDBY: In STANDBY mode only serial interface is working and all other PMU functions are disabled – PMU is in low power condition. In STANDBY mode LP8720 can be (re)configured via Serial Interface. START UP: START UP sequence is defined by registers contents. START UP sequence starts: 1) If rising edge on EN-pin. 2) After cooling down from thermal shutdown event if EN=HI. It is not recommended to write to LP8720 registers during START UP. If doing so then current START UP sequence may become undefined. IDLE: PMU will enter into IDLE mode (normal operating mode) after end of START UP sequence. In IDLE mode all LDO’s and BUCK can be enabled/disabled via Serial Interface. Also in IDLE mode LP8720 can be (re) configured via Serial Interface. SHUT DOWN: SHUT DOWN sequence is “reverse order of start up sequence” and this is defined by registers contents. SHUT DOWN starts 1) If falling edge on EN-pin. 2) If temperature exceeds thermal shutdown threshold TSD +160°C. It is not recommended to write to LP8720 registers during SHUT DOWN. If doing so then current SHUT DOWN sequence may become undefined. 30067504 Additional Functions SLEEP: If sum of all LDO’s load currents and BUCK load current is no higher than 5mA then user can put PMU to SLEEP. In SLEEP PMU GND current is minimized. In SLEEP LDO’s and BUCK cannot be loaded with big current. There are 2 possibilities to use SLEEP: 1) Control via Serial Interface. 2) Control by DVS-pin. DVS: Dynamic Voltage Scaling allows using 2 voltage sets for BUCK. There are 2 possibilities to use DVS: 1) Control via Serial Interface. 2) Control by DVS-pin. INTERRUPT: If interrupt is not masked then PMU forces IRQ_N low if temperature crossed TSD_EW limit (thermal shutdown early warning) or/and thermal shutdown event took place. IRQ_N is released by reading Interrupt register. www.national.com 4 LP8720 POWER-ON AND POWER-OFF SEQUENCES Start Up Sequence if DEFSEL=VBATT or DEFSEL=Hi-Z 30067505 tBON 150 µs – Reference and bias turn ON. Min 100 µs max 200 µs. tS 25 µs – time step. Time step accuracy is defined by OSC frequency accuracy. Note 1 START UP and SHUT DOWN sequences are defined by registers. Sequences given here are valid if there the registers are not rewritten via Serial Interface. Note 2 The timing showed here define time points when LDO’s and BUCK are enabled/disabled. Enabling /disabling process duration depends on loading conditions. Buck startup duration is 140 µs for no load. LDO startup duration is no more than 35 µs. For details please see LDO’s and BUCK electrical specifications. Note 3 LDO5 and BUCK are disabled. If LDO5 and/or BUCK are enabled via Serial Interface and startup sequence is not changed via Serial interface, then LDO5 and BUCK are disabled with no delay from falling edge on EN-pin. Note 4 At this time point registers 0x09 and 0x0C are reset to POR default values. Note 5 At this time point registers 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07 and 0x08 are reset to POR default values. 5 www.national.com LP8720 Start Up Sequence if DEFSEL=GND 30067506 tBON 150 µs – Reference and bias turn ON. Min 100 µs max 200 µs. tS 25 µs – time step. Time step accuracy is defined by OSC frequency accuracy. Note 1 START UP and SHUT DOWN sequences are defined by registers. Sequences given here are valid if there the registers are not rewritten via Serial Interface. Note 2 The timing showed here define time points when LDO’s and BUCK are enabled/disabled. Enabling /disabling process duration depends on loading conditions. Buck startup duration is 140 µs for no load. LDO startup duration is no more than 35 µs. For details please see LDO’s and BUCK electrical specifications. Note 3 LDO1, LDO2, LDO4, LDO5 and BUCK are disabled. If LDO1, LDO2, LDO4, LDO5 and/or BUCK are enabled via Serial Interface and startup sequence is not changed via Serial interface, then LDO1, LDO2, LDO4, LDO5 and BUCK are disabled with no delay from falling edge on EN-pin. Note 4 At this time point registers 0x09 and 0x0C are reset to POR default values. Note 5 At this time point registers 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07 and 0x08 are reset to POR default values. www.national.com 6 LP8720 Start Up Sequence DEFSEL VBATT GND Hi-Z Start Up Sequence LDO1, 2, 3, 4 enable same time. LDO5 and BUCK enable via Serial Interface. LDO3 enable. LDO1, 2, 4, 5 and BUCK enable via Serial Interface . LDO1, 2, 3, 4 enable same time. LDO5 and BUCK enable via Serial Interface. Shut Down Sequence In reverse order of start up sequence. In reverse order of start up sequence. In reverse order of start up sequence. Default Output Voltages Output LDO1 LDO2 LDO3 LDO4 LDO5 BUCK Max Current [mA] 300 300 300 300 300 400 Default output Voltage [V] and default ON/OFF if EN=HI DEFSEL=VBATT 3.0 ON 2.6 ON 1.8 ON 1.0 ON 3.3 OFF 1.0 OFF DEFSEL=GND 3.0 OFF 3.0 OFF 2.6 ON 2.6 OFF 3.3 OFF 1.2/1.31) OFF DEFSEL=Hi-Z 2.8 ON 2.6 ON 1.8 ON 1.2 ON 3.3 OFF 1.2 OFF Note 1) BUCK voltage is 1.2V if DVS=LO and 1.3V if DVS=HI. 7 www.national.com LP8720 www.national.com Control Register Map When IDSEL= VBATT then slave address is 7h’7F When IDSEL= floating (Hi-Z) then slave address is 7h’7C When IDSEL= GND then slave address is 7h’7D Bit 6 VBATT EXT_DVS_ CONTROL LDO1_ T[1] LDO2_ T[1] LDO3_ T[1] LDO4_ T[1] LDO5_ T[1] BUCK_ T[1] FORCE_ PWM SLEEP_ MODE BUCK_ EN LDO5_ EN LDO4_ EN BUCK_ V2[4] BUCK_ V2[3] BUCK_ V2[2] LDO3_ EN BUCK_ T[0] BUCK_ V1[4] BUCK_ V1[3] BUCK_ V1[2] LDO5_ T[0] LDO5_ V[4] LDO5_ V[3] LDO5_ V[2] LDO4_ T[0] LDO4_ V[4] LDO4_ V[3] LDO4_ V[2] LDO4_ V[1] LDO5_ V[1] BUCK_ V1[1] BUCK_ V2[1] LDO2_ EN LDO2_ PULLDOWN TSD TSD_ INT TSD_ MASK LDO3_ T[0] LDO3_ V[4] LDO3_ V[3] LDO3_ V[2] LDO3_ V[1] LDO2_ T[0] LDO2_ V[4] LDO2_ V[3] LDO2_ V[2] LDO2_ V[1] LDO2_ V[0] LDO3_ V[0] LDO4_ V[0] LDO5_ V[0] BUCK_ V1[0] BUCK_ V2[0] LDO1_ EN LDO1_ T[0] LDO1_ V[4] LDO1_ V[3] LDO1_ V[2] LDO1_ V[1] LDO1_ V[0] EXT_SLEEP_ CONTROL SHORT_ TIMESTEP Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR default DEFSEL GND Hi-Z Addr Name Bit 7 0x00 GENERAL_ SETTINGS 0000 0001 0000 0101 0000 0001 0111 1101 1111 1101 0111 1001 0111 0101 1111 1101 0111 0101 0110 1100 0111 0101 0110 1100 0110 0011 1111 1010 0110 0101 1111 1111 1111 1111 1111 1111 1110 0101 1110 1011 1110 1001 0000 0101 0000 1001 0000 1001 1000 1111 1000 0100 1000 1111 0x01 LDO1_ SETTINGS LDO1_ T[2] 0x02 LDO2_ SETTINGS LDO2_ T[2] 0x03 LDO3_ SETTINGS LDO3_ T[2] 0x04 LDO4_ SETTINGS LDO4_ T[2] 0x05 LDO5_ SETTINGS LDO5_ T[2] 8 0x06 BUCK_ SETTINGS1 BUCK_ T[2] 0x07 BUCK_ SETTINGS2 0x08 ENABLE_ BITS DVS_ V2/V1 0x09 PULLDOWN_ BITS APU_ TSD BUCK_ LDO5_ LDO4_ LDO3_ PULLDOWN PULLDOWN PULLDOWN PULLDOWN LDO1_ 0011 1111 0011 1111 0011 1111 PULLDOWN TSD_EW TSD_EW_ INT TSD_EW_ MASK 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0011 0000 0011 0000 0011 0x0A STATUS_ BITS 0x0B INTERRUPT_ BITS *) 0x0C INTERRUPT_ MASK *) *) Registers STATUS_BITS 0x0A and INTERRUPT_BITS 0x0B are read only. LP8720 Register 0x00 EXT_DVS_CONTROL 1 – DVS-pin control: DVS=HI then BUCK_V1[4:0] DVS=LO then BUCK_V2[4:0] 0 – Serial interface control: DVS_V2/V1=1 then BUCK_V1[4:0] DVS_V2/V1=0 then BUCK_V2[4:0] 1 – DVS-pin control: DVS=HI then normal DVS=LO then SLEEP 0 – Serial interface control: SLEEP_MODE=0 then normal SLEEP_MODE=1 then SLEEP 1 – time step tS=25 µs 0 – time step tS=50 µs By request time step 100 µs/200 µs is available. EXT_SLEEP_CONTROL SHORT_TIMESTEP Registers 0x01 – 0x07 LDO1_V[4:0] LDO2_V[4:0] LDO3_V[4:0] LDO5_V[4:0] 00000 – 1.20V 00001 – 1.25V 00010 – 1.30V 00011 – 1.35V 00100 – 1.40V 00101 – 1.45V 00110 – 1.50V 00111 – 1.55V 00000 – 0.80V 00001 – 0.85V 00010 – 0.90V 00011 – 1.00V 00100 – 1.10V 00101 – 1.20V 00110 – 1.25V 00111 – 1.30V 0000 External resistor divider 00001 – 0.80V 00010 – 0.85V 00011 – 0.90V 00100 – 0.95V 00101 – 1.00V 00110 – 1.05V 00111 – 1.10V 01000 – 1.60V 01001 – 1.65V 01010 – 1.70V 01011 – 1.75V 01100 – 1.80V 01101 – 1.85V 01110 – 1.90V 01111 – 2.00V 01000 – 1.35V 01001 – 1.40V 01010 – 1.45V 01011 – 1.50V 01100 – 1.55V 01101 – 1.60V 01110 – 1.65V 01111 – 1.70V 01000 – 1.15V 01001 – 1.20V 01010 – 1.25V 01011 – 1.30V 01100 – 1.35V 01101 – 1.40V 01110 – 1.45V 01111 – 1.50V 10000 – 2.10V 10001 – 2.20V 10010 – 2.30V 10011 – 2.40V 10100 – 2.50V 10101 – 2.60V 10110 – 2.65V 10111 – 2.70V 10000 – 1.75V 10001 – 1.80V 10010 – 1.85V 10011 – 1.90V 10100 – 2.00V 10101 – 2.10V 10110 – 2.20V 10111 – 2.30V 10000 – 1.55V 10001 – 1.60V 10010 – 1.65V 10011 – 1.70V 10100 – 1.75V 10101 – 1.80V 10110 – 1.85V 10111 – 1.90V 11000 – 2.75V 11001 – 2.80V 11010 – 2.85V 11011 – 2.90V 11100 – 2.95V 11101 – 3.00V 11110 – 3.10V 11111 – 3.30V 11000 – 2.40V 11001 – 2.50V 11010 – 2.60V 11011 – 2.65V 11100 – 2.70V 11101 – 2.75V 11110 – 2.80V 11111 – 2.85V 11000 – 1.95V 11001 – 2.00V 11010 – 2.05V 11011 – 2.10V 11100 – 2.15V 11101 – 2.20V 11110 – 2.25V 11111 – 2.30V LDO4_V[4:0] BUCK_V1[4:0] BUCK_V2[4:0] BUCK_V1[4:0] should be higher (or equal) than BUCK_V2[4:0]. LDO1_T[2:0] LDO2_T[2:0] LDO3_T[2:0] LDO4_T[2:0] LDO5_T[2:0] BUCK_T[2:0] FORCE_PWM 000 – start up delay 0 001 – start up delay = 1 * time step tS 010 – start up delay = 2 * time step tS 011 – start up delay = 3 * time step tS 100 – start up delay = 4 * time step tS 101 – start up delay = 5 * time step tS 110 – start up delay = 6 * time step tS 111 – NO startup For proper startup operation “111 NO start up” should have corresponding bit in ENABLE_BITS register 0x08 set to 0 (disable). 1 – Buck is forced to work in PWM mode 0 – Buck works in automatic PFM/PWM selection mode. 9 www.national.com LP8720 Register 0x08 LDO1_EN LDO2_EN LDO3_EN LDO4_EN LDO5_EN BUCK_EN In STANDBY mode 1 – During next START UP sequence will be enabled. 0 – During next START UP sequence will be NOT enabled. For proper operation output having “111 NO start up” should have corresponding enable bit 0 (disable). In IDLE mode the bit has immediate effect. 1 – Enable 0 – Disable SLEEP_MODE 1 – SLEEP 0 – normal This bit has effect only if EXT_SLEEP_CONTROL=0 (register 0x00) 1 – buck voltage is BUCK_V1[4:0] 0 – buck voltage is BUCK_V2[4:0] This bit has effect only if EXT_DVS_CONTROL=0 (register 0x00) DVS_V2/V1 Register 0x09 LDO1_PULLDOWN LDO2_PULLDOWN LDO3_PULLDOWN LDO4_PULLDOWN LDO5_PULLDOWN BUCK_PULLDOWN APU_TSD 1 – Pull down enabled 0 – Pull down disabled This bit defines either to reset registers or not before LP8720 automatically starts START UP sequence form Thermal Shutdown after cooling down if EN-pin is High. 1 – No change to registers – registers content stays the same as before Thermal Shutdown. 0 – Reset registers to default values before START UP from Thermal Shutdown. Register 0x0A (Read Only) TSD TSD_EW 1 – device is in Thermal Shutdown. 0 – device is NOT in Thermal Shutdown . 1 – device temperature is higher than Thermal Shutdown Early Warning threshold. 0 – device temperature is lower than Thermal Shutdown Early Warning threshold. Register 0x0B (Read Only) TSD_INT TSD_EW 1 – Interrupt that was caused by Thermal Shutdown 0 – No Interrupt that was caused by Thermal Shutdown 1 – Interrupt that was caused by Thermal Shutdown Early Warning 0 – No Interrupt that was caused by Thermal Shutdown Early Warning Note 1: all reads from this register are destructive (all bits are reset to 0 after reading). Note 2: read form this register releases IRQ_N-pin (if was pushed down). Register 0x0C TSD_MASK TSD_EW_MASK 1 – TSD interrupt is masked 0 – TSD interrupt is NOT masked 1 – TSD_EW interrupt is masked 0 – TSD_EW interrupt is NOT masked www.national.com 10 LP8720 Support Functions REFERENCE LP8720 has internal reference block creating all necessary references and biasing for all blocks. OSCILLATOR There is internal oscillator giving clock to the bucks and to logic control. VBATT=3.6V Parameter Typ Min Max Unit Oscillator frequency 2.0 1.9 2.1 MHz eg. by excessive power dissipation. The temperature monitoring function has two threshold values TSD and TSD_EW that result in protective actions. When TSD_EW +125ºC is exceeded, then IRQ_N is set to low and “1” is written to TSD_EW bit in both STATUS register and in INTERRUPT register. If the temperature exceeds TSD +160ºC, then PMU initiates Emergency Shutdown. The POWER UP operation after Thermal Shutdown can be initiated only after the chip has cooled down to the +115ºC threshold Parameter TSD *) TSD_EW *) TSD_EW Hysteresis *) *) Guaranteed by design. Typ 160 125 10 Unit °C °C °C THERMAL SHUTDOWN The Thermal Shutdown (TSD) function monitors the chip temperature to protect the chip from temperature damage caused 11 www.national.com LP8720 Absolute Maximum Ratings (Note 1, Note 2) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. VBATT = VINB, VBATT -0.3V to +6V VIN1, VIN2 -0.3V to VBATT+0.15V, max 6V All other pins -0.3V to VBATT+0.3V, max 6V Junction Temperature (TJ-MAX) 150ºC Storage Temperature -40 to 150ºC Maximum Continuous Power Dissipation PD-MAX (Note 3) 1.75 W ESD (Note 4) 2 kV HBM 200V MM Operating Ratings VBATT = VINB, VBATT VIN1, VIN2 All input-only pins Junction Temperature (TJ) Ambient Temperature (TA) Maximum Power Dissipation (TA = 70ºC), (Note 5) (Note 1, Note 2) 2.7 to 4.5V 2.5V to VBATT 0V to VBATT -40 to 125ºC -40 to 85ºC 1.2 W (Note 9) Thermal Properties Junction-to-Ambient Thermal Resistance (θJA) (Jedec Standard Thermal PCB) Micro SMD 20 45°C/W Current Consumption Unless otherwise noted, VVBATT=VVINB =VVIN1=VVIN2=3.6V, GND=GNDB=0V, CVBATT=CVIN1=CVIN2=2.2 µF, CVINB=10 µF. Typical values and limits appearing in normal type apply for TJ=25°C. Limits appearing in boldface type apply over the entire junction temperature range for operation, TJ= -40 to +125°C. (Note 6) Symbol IQ(STANDBY) IQ(SLEEP) IQ(SLEEP) IQ(SLEEP) IQ(SLEEP) IQ IQ IQ IQ Parameter Battery Standby Current Battery Current in SLEEP Mode @ 0 load Battery Current in SLEEP Mode @ 0 load Battery Current in SLEEP Mode @ 0 load Battery Current in SLEEP Mode @ 0 load Battery Current @ 0 load Battery Current @ 0 load Battery Current @ 0 load Battery Current @ 0 load VBATT = 3.6V BUCK and all LDO’s enabled LDO1, LDO2, LDO3 and LDO4 enabled LDO3 enabled LDO1 and BUCK enabled BUCK and all LDO’s enabled LDO1, LDO2, LDO3 and LDO4 enabled LDO3 enabled LDO1 and BUCK enabled Conditions Typ 0.7 190 170 100 100 270 230 120 120 200 400 150 Limit Min Max 5 270 Units µA µA µA µA µA µA µA µA µA Power on Reset Unless otherwise noted, VVBATT=VVINB =VVIN1=VVIN2=3.6V, GND=GNDB=0V, CVBATT=CVIN1=CVIN2=2.2 µF, CVINB=10 µF. Typical values and limits appearing in normal type apply for TJ=25°C. Limits appearing in boldface type apply over the entire junction temperature range for operation, TJ= -40 to +125°C. (Note 6) Symbol VPOR_HI VPOR_LO Parameter POR higher threshold POR lower threshold VVBATT rising VVBATT falling (Note 7) Conditions Typ 2.2 1.4 Limit Min 2.0 Max 2.4 Units V V www.national.com 12 LP8720 Logic and Control Unless otherwise noted, VVBATT=VVINB =VVIN1=VVIN2=3.6V, GND=GNDB=0V, CVBATT=CVIN1=CVIN2=2.2µF, CVINB=10µF. Typical values and limits appearing in normal type apply for TJ=25°C. Limits appearing in boldface type apply over the entire junction temperature range for operation, TJ= -40 to +125°C. (Note 6) Symbol Parameter Conditions Typ Limit Min Max 0.4 1.2 -5 550 300 +5 900 0.4 NA Units Logic and Control Inputs VIL VIH IIL RPD VOL VOH Input Low Level Input High Level Input Current Pull Down Resistance Output Low Level Output High Level EN, SCL, SDA, DVS EN, SCL, SDA, DVS All logic inputs From EN to GND IRQ_N, SDA, IOUT=2mA IRQ_N, SDA are Open drain outputs. V V µA kΩ V µA Logic and Control Outputs 13 www.national.com LP8720 Buck Converter Unless otherwise noted, VVBATT=VVINB =VVIN1=VVIN2=3.6V, GND=GNDB=0V, CVBATT=CVIN1=CVIN2=2.2 µF, CVINB=10 µF. Typical values and limits appearing in normal type apply for TJ=25°C. Limits appearing in boldface type apply over the entire junction temperature range for operation, TJ= -40 to +125°C. (Note 6, Note 10) Symbol VFB VBUCK VVOUT,PFM Parameter Feedback Voltage Conditions 3.0V ≤ VIN ≤ 4.5V external resistor divider Typ 0.5 1.2 1.5 Limit Min 0.485 1.164 Max 0.515 1.236 Units V V % Output Voltage, PWM Mode 3.0V ≤ VIN ≤ 4.5V Output Voltage regulation in (Note 7) PFM mode relative to regulation in PWM mode Line Regulation Load Regulation Switch Peak Current Limit P channel FET on resistance N channel FET on resistance Internal Oscillator Frequency PWM Mode IOUT = 5mA, PFM-mode VOUT = 1.2V (Note 7) IOUT = 200mA, PWM-mode VOUT = 1.2V (Note 7) 3.0V ≤ VIN ≤ 4.5V IOUT = 10 mA 100mA ≤ IOUT ≤ 300mA PWM Mode @ 400 mA 3.0V ≤ VIN ≤ 4.5V VIN = 3.6V, ID = 100mA VOUT VOUT ILIM_PWM RDSON(P) RDSON(N) fOSC Efficiency 0.14 0.09 900 310 160 2 88 1.9 1.7 500 500 300 2.1 2.3 %/V %/mA mA mΩ mΩ MHz % 90 140 µs TSTUP Start Up Time IOUT = 0, VOUT = 1.2V (Note 7) Buck Output Voltage Programming in Register 0x06 and 0x07 BUCK1_Vx 5h’00 5h’01 5h’02 5h’03 5h’04 5h’05 5h’06 5h’07 5h’08 5h’09 5h’0A 5h’0B 5h’0C 5h’0D 5h’0E 5h’0F VOUT External resistor divider 0.80 0.85 0.90 0.95 1.00 1.05 1.10 1.15 1.20 1.25 1.30 1.35 1.40 1.45 1.50 BUCK1_Vx 5h’10 5h’11 5h’12 5h’13 5h’14 5h’15 5h’16 5h’17 5h’18 5h’19 5h’1A 5h’1B 5h’1C 5h’1D 5h’1E 5h’1F VOUT 1.55 1.60 1.65 1.70 1.75 1.80 1.85 1.90 1.95 2.00 2.05 2.10 2.15 2.20 2.25 2.30 www.national.com 14 LP8720 Output Voltage Selection Using External Resistor Divider Buck1 output voltage can be programmed via the selection of the external feedback resistor network. The formula for output voltage selection is VOUT – output voltage VFB – feedback voltage (0.5V) For any out voltage greater than or equal to 0.8V a transfer function zero should be added by the addition of a capacitor C1. The formula for calculation of C1 is: 30067508 VOUT will be adjusted to make the voltage at FB equal to 0.5V. The resistor from FB to ground RFB2 should be around 200 kΩ to keep the current drawn through the resistor network to a minimum but large enough that it is not susceptible to noise. With RFB2=200 kΩ and VFB at 0.5V, the current through the resistor feedback network will be 2.5 µA. For recommended component values see the table below. VOUT [V] RFB1 [kΩ] RFB2 [kΩ] C1 [pF] L [µH] COUT [µF] 1.0 1.2 1.4 1.5 1.6 1.85 200 280 360 360 440 540 200 200 200 180 200 200 18 12 10 10 8.2 6.8 2.2 2.2 2.2 2.2 2.2 2.2 10 10 10 10 10 10 15 www.national.com LP8720 LDO’s There are all together 5 LDO’s in LP8720 grouped as A-type LDO’s (LDO 2,3) D-type LDO’s (LDO 1,5) LO-type LDO (LDO4) The A-type LDO’s are optimized for supplying of analog loads and have ultra low noise (15 µVRMS) and excellent PSRR (70dB) performance. The D-type LDO’s are optimized for good dynamic performance to supply different fast changing (digital) loads. The LO-type LDO is optimized for low output voltage and for good dynamic performance to supply different fast changing (digital) loads. LDO1, 2, 3 and 5 Output Voltage Programming Data Code LDOx_V 5h’00 5h’01 5h’02 5h’03 5h’04 5h’05 5h’06 5h’07 5h’08 5h’09 5h’0A 5h’0B 5h’0C 5h’0D 5h’0E 5h’0F LDOx [V] 1.20 1.25 1.30 1.35 1.40 1.45 1.50 1.55 1.60 1.65 1.70 1.75 1.80 1.85 1.90 2.00 Data Code LDOx_V 5h’10 5h’11 5h’12 5h’13 5h’14 5h’15 5h’16 5h’17 5h’18 5h’19 5h’1A 5h’1B 5h’1C 5h’1D 5h’1E 5h’1F LDOx [V] 2.10 2.20 2.30 2.40 2.50 2.60 2.65 2.70 2.75 2.80 2.85 2.90 2.95 3.00 3.10 3.30 All LDO’s can be programmed through serial interface for 32 different output voltage value, which are summarized in the in the “LDO Output Voltage Programming” tables below. At the PMU power on, LDO’s start up according to the selected startup sequence and the default voltages after start-up sequence depend on startup setup. See section Power-On and Power-Off Sequences for details. For stability all LDO’s have to have connected to output an external capacitor COUT with recommended value of 1 µF. It is important to select the type of capacitor which capacitance will in no case (voltage, temperature, etc) be outside of limits specified in the LDO electrical characteristics. LDO4 Output Voltage Programming Data Code LDO4_V 5h’00 5h’01 5h’02 5h’03 5h’04 5h’05 5h’06 5h’07 5h’08 5h’09 5h’0A 5h’0B 5h’0C 5h’0D 5h’0E 5h’0F LDO4 [V] 0.80 0.85 0.90 1.00 1.10 1.20 1.25 1.30 1.35 1.40 1.45 1.50 1.55 1.60 1.65 1.70 Data Code LDO4_V 5h’10 5h’11 5h’12 5h’13 5h’14 5h’15 5h’16 5h’17 5h’18 5h’19 5h’1A 5h’1B 5h’1C 5h’1D 5h’1E 5h’1F LDO4 [V] 1.75 1.80 1.85 1.90 2.00 2.10 2.20 2.30 2.40 2.50 2.60 2.65 2.70 2.75 2.80 2.85 www.national.com 16 LP8720 A-Type LDO Electrical Characteristics Unless otherwise noted, VVBATT=VVINB =VVIN1=VVIN2=3.6V, GND=GNDB=0V, CVBATT=CVIN1=CVIN2=2.2 µF, CVINB=10 µF. Typical values and limits appearing in normal type apply for TJ=25°C. Limits appearing in boldface type apply over the entire junction temperature range for operation, TJ= -40 to +125°C. (Note 6) Symbol VOUT ISC VDO ΔVOUT Parameter Output Voltage Accuracy Output Current Limit Dropout Voltage Line Regulation Load Regulation eN PSRR tSTART UP VTransient COUT Output Noise Voltage Power Supply Ripple Rejection Ratio Start-Up Time from Shutdown Start-Up Transient Overshoot External output capacitance for stability Conditions IOUT = 1mA, VOUT = 2.85V VOUT = 0V IOUT = IMAX (Note 8) VOUT + 0.5V ≤ VIN ≤ 4.5V IOUT = IMAX 1mA ≤ IOUT ≤ IMAX 10Hz ≤ f ≤ 100kHz COUT = 1µF (Note 7) f=10kHz, COUT = 1µF IOUT = 20mA (Note 7) COUT = 1µF, IOUT = IMAX (Note 7) COUT = 1µF, IOUT = IMAX (Note 7) LDO# 2,3 2,3 2,3 2,3 2,3 2,3 2,3 2,3 2,3 2,3 1.0 0.5 600 200 1 5 15 70 35 30 20 400 Typ Limit Min -2 -3 Max +2 +3 Units % % mA mV mV mV µVRMS dB µs mV µF D-Type and LO-Type LDO Electrical Characteristics Unless otherwise noted, VVBATT=VVINB =VVIN1=VVIN2=3.6V, GND=GNDB=0V, CVBATT=CVIN1=CVIN2=2.2 µF, CVINB=10 µF. Typical values and limits appearing in normal type apply for TJ=25°C. Limits appearing in boldface type apply over the entire junction temperature range for operation, TJ= -40 to +125°C. (Note 6) Symbol VOUT Parameter Output Voltage Accuracy Conditions IOUT = 1mA, VOUT = 2.85V IOUT = 1mA, VOUT = 1.20V IOUT = 1mA, VOUT = 2.60V ISC VDO ΔVOUT Output Current Limit Dropout Voltage Line Regulation Load Regulation eN PSRR tSTART UP VTransient COUT Output Noise Voltage Power Supply Ripple Rejection Ratio Start-Up Time from Shutdown Start-Up Transient Overshoot External output capacitance for stability VOUT = 0V IOUT = IMAX (Note 8) VOUT + 0.5V ≤ VIN ≤ 4.5V IOUT = IMAX 1mA ≤ IOUT ≤ IMAX 10Hz ≤ f ≤ 100kHz COUT = 1µF (Note 7) f=10kHz, COUT = 1µF IOUT = 20mA (Note 7) COUT = 1µF, IOUT = IMAX (Note 7) COUT = 1µF, IOUT = IMAX (Note 7) LDO# 1,5 4 4 1,4,5 1,4,5 1,4,5 1,4,5 1,4,5 1,4,5 1,4,5 1,4,5 1,4,5 1.0 0.5 600 190 2 5 100 55 35 30 20 400 Typ Limit Min -2 -3 -2 -3 -3 -4 Max +2 +3 +2 +3 +3 +4 Units % % % % % % mA mV mV mV µVRMS dB µs mV µF 17 www.national.com LP8720 Serial Interface Unless otherwise noted, VVBATT=VVINB =VVIN1=VVIN2=3.6V, GND=GNDB=0V, CVBATT=CVIN1=CVIN2=2.2 µF, CVINB=10 µF. Typical values and limits appearing in normal type apply for TJ=25°C. Limits appearing in boldface type apply over the entire junction temperature range for operation, TJ= -40 to +125°C. (Note 6, Note 7) Symbol fCLK tBF tHOLD tCLK-LP tCLK-HP tSU tDATA-HOLD tDATA-SU tSU tTRANS Parameter Clock Frequency Bus-Free Time between START and STOP Hold Time Repeated START Condition CLK Low Period CLK High Period Set-Up Time Repeated START Condition Data Hold Time Data Set-Up Time Set-Up Time for STOP Condition Maximum Pulse Width of Spikes that Must Be Suppressed by the Input Filter of Both DATA & CLK Signals 1.3 0.6 1.3 0.6 0.6 50 100 0.6 Conditions Typ Limit Min Max 400 Units kHz µs µs µs µs µs ns ns µs 50 ns Notes to Electrical Characteristics Tables Note 1: Absolute Maximum Ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions under which operation of the device is guaranteed. Operating Ratings do not imply guaranteed performance limits. For guaranteed performance limits and associated test conditions, see the Electrical Characteristics tables. Note 2: All voltages are with respect to the potential at the GND pin. Note 3: The Absolute Maximum power dissipation depends on the ambient temperature and can be calculated using the formula P = (TJ – TA)/θJA, (eq. 1) where TJ is the junction temperature, TA is the ambient temperature, and θJA is the junction-to-ambient thermal resistance. The 1.75W rating appearing under Absolute Maximum Ratings results from substituting the Absolute Maximum junction temperature, 150ºC for TJ, 70ºC for TA, and 45°C/W for θJA. More power can be dissipated safely at ambient temperatures below 70°C. Less power can be dissipated safely at ambient temperatures above 70°C. The Absolute Maximum power dissipation can be increased by 22mW for each degree below 70°C, and it must be de-rated by 22 mW for each degree above 70ºC. Note 4: The human-body model is 100 pF discharged through 1.5 kΩ. The machine model is a 200 pF capacitor discharged directly into each pin, MIL-STD-883 3015.7. Note 5: Like the Absolute Maximum power dissipation, the maximum power dissipation for operation depends on the ambient temperature. The 1.2W rating for Micro SMD 20 appearing under Operating Ratings results from substituting the maximum junction temperature for operation, 125°C, for TJ, 70°C for TA, and 45° C/W for θJA into (eg. 1) above. More power can be dissipated at ambient temperatures below 70°C. Less power can be dissipated at ambient temperatures above 70°C. The maximum power dissipation for operation can be increased by 22mW for each degree below 70°C, and it must be de-rated by 22 mW for each degree above 70°C. Note 6: All limits are guaranteed. All electrical characteristics having room-temperature limits are tested during production with TJ = 25°C. All hot and cold limits are guaranteed by correlating the electrical characteristics to process and temperature variations and applying statistical process control. Note 7: Guaranteed by design. Note 8: Dropout voltage is the input-to-output voltage difference at which the output voltage is 100mV below its nominal value. This specification does not apply in cases it implies operation with an input voltage below the 2.5V minimum appearing under Operating Ratings. For example, this specification does not apply for devices having 1.5V outputs because the specification would imply operation with an input voltage at or about 1.5V. Note 9: Junction-to-ambient thermal resistance is highly application and board-layout dependent. In applications where high maximum power dissipation exists, special care must be paid to thermal dissipation issues in board design. Note 10: Guaranteed for output voltages no less than 1.0V www.national.com 18 LP8720 I2C-Compatible Serial Bus Interface INTERFACE BUS OVERVIEW The I2C compatible synchronous serial interface provides access to the programmable functions and registers on the device. This protocol uses a two-wire interface for bi-directional communications between the IC’s connected to the bus. The two interface lines are the Serial Data Line (SDA), and the Serial Clock Line (SCL). These lines should be connected to a positive supply, via a pull-up resistor of 1.5 kΩ, and remain HIGH even when the bus is idle. Every device on the bus is assigned a unique address and acts as either a Master or a Slave depending on whether it generates or receives the serial clock (SCL). DATA TRANSACTIONS One data bit is transferred during each clock pulse. Data is sampled during the high state of the serial clock (SCL). Consequently, throughout the clock’s high period, the data should remain stable. Any changes on the SDA line during the high state of the SCL and in the middle of a transaction, aborts the current transaction. New data should be sent during the low SCL state. This protocol permits a single data line to transfer both command/control information and data using the synchronous serial clock. Condition to terminate the transaction. Every byte written to the SDA bus must be 8 bits long and is transferred with the most significant bit first. After each byte, an Acknowledge signal must follow. The following sections provide further details of this process. START AND STOP The Master device on the bus always generates the Start and Stop Conditions (control codes). After a Start Condition is generated, the bus is considered busy and it retains this status until a certain time after a Stop Condition is generated. A high-to-low transition of the data line (SDA) while the clock (SCL) is high indicates a Start Condition. A low-to-high transition of the SDA line while the SCL is high indicates a Stop Condition. 30067510 FIGURE 2. Start and Stop Conditions In addition to the first Start Condition, a repeated Start Condition can be generated in the middle of a transaction. This allows another device to be accessed, or a register read cycle. ACKNOWLEDGE CYCLE The Acknowledge Cycle consists of two signals: the acknowledge clock pulse the master sends with each byte transferred, and the acknowledge signal sent by the receiving device. The master generates the acknowledge clock pulse on the ninth clock pulse of the byte transfer. The transmitter releases the SDA line (permits it to go high) to allow the receiver to send the acknowledge signal. The receiver must pull down the SDA line during the acknowledge clock pulse and ensure that SDA remains low during the high period of the clock pulse, thus signaling the correct reception of the last data byte and its readiness to receive the next byte. 30067527 FIGURE 1. Bit Transfer Each data transaction is composed of a Start Condition, a number of byte transfers (set by the software) and a Stop 30067528 FIGURE 3. Bus Acknowledge Cycle 19 www.national.com LP8720 ”ACKNOWLEDGE AFTER EVERY BYTE” RULE The master generates an acknowledge clock pulse after each byte transfer. The receiver sends an acknowledge signal after every byte received. There is one exception to the “acknowledge after every byte” rule. When the master is the receiver, it must indicate to the transmitter an end of data by not-acknowledging (“negative acknowledge”) the last byte clocked out of the slave. This “negative acknowledge” still includes the acknowledge clock pulse (generated by the master), but the SDA line is not pulled down. ADDRESSING TRANSFER FORMATS Each device on the bus has a unique slave address. The LP8720 operates as a slave device. Slave address is selectable by IDSEL-pin. When IDSEL= VBATT then slave address is 7h’7F When IDSEL= floating (Hi-Z) then slave address is 7h’7C When IDSEL= GND then slave address is 7h’7D Before any data is transmitted, the master transmits the address of the slave being addressed. The slave device should send an acknowledge signal on the SDA line, once it recognizes its address. The slave address is the first seven bits after a Start Condition. The direction of the data transfer (R/W) depends on the bit sent after the slave address — the eighth bit. When the slave address is sent, each device in the system compares this slave address with its own. If there is a match, the device considers itself addressed and sends an acknowledge signal. Depending upon the state of the R/W bit (1:read, 0:write), the device acts as a transmitter or a receiver. CONTROL REGISTER WRITE CYCLE • Master device generates start condition. • Master device sends slave address (7 bits) and the data direction bit (r/w = '0'). • Slave device sends acknowledge signal if the slave address is correct. • Master sends control register address (8 bits). • Slave sends acknowledge signal. • Master sends data byte to be written to the addressed register. • Slave sends acknowledge signal. • If master will send further data bytes the control register address will be incremented by one after acknowledge signal. • Write cycle ends when the master creates stop condition. CONTROL REGISTER READ CYCLE • Master device generates a start condition. • Master device sends slave address (7 bits) and the data direction bit (r/w = '0'). • Slave device sends acknowledge signal if the slave address is correct. • Master sends control register address (8 bits). • Slave sends acknowledge signal. • Master device generates repeated start condition. • Master sends the slave address (7 bits) and the data direction bit (r/w = “1”). • Slave sends acknowledge signal if the slave address is correct. • Slave sends data byte from addressed register. • If the master device sends acknowledge signal, the control register address will be incremented by one. Slave device sends data byte from addressed register. • Read cycle ends when the master does not generate acknowledge signal after data byte and generates stop condition. Address Mode Data Read [Ack] [Ack] [Ack] [Register Data] … additional reads from subsequent register address possible [Ack] [Ack] [Ack] … additional writes to subsequent register address possible Data Write < > Data from master [ ] Data from slave www.national.com 20 LP8720 REGISTER READ AND WRITE DETAIL 30067529 FIGURE 4. Register Write Format 30067530 FIGURE 5. Register Read Format 21 www.national.com LP8720 Physical Dimensions inches (millimeters) unless otherwise noted Micro SMD 20 Package NS Package Number MKT-TLA2011A X1 = 1.970 mm ±0.030 mm X2 = 2.466 mm ±0.030 mm X3 = 0.600 mm ±0.075 mm www.national.com 22 LP8720 Notes 23 www.national.com LP8720 One Step-Down DC/DC and Five Linear Regulators with I2C Compatible Interface Notes For more National Semiconductor product information and proven design tools, visit the following Web sites at: www.national.com Products Amplifiers Audio Clock and Timing Data Converters Interface LVDS Power Management Switching Regulators LDOs LED Lighting Voltage References PowerWise® Solutions Temperature Sensors PLL/VCO www.national.com/amplifiers www.national.com/audio www.national.com/timing www.national.com/adc www.national.com/interface www.national.com/lvds www.national.com/power www.national.com/switchers www.national.com/ldo www.national.com/led www.national.com/vref www.national.com/powerwise WEBENCH® Tools App Notes Reference Designs Samples Eval Boards Packaging Green Compliance Distributors Quality and Reliability Feedback/Support Design Made Easy Design Support www.national.com/webench www.national.com/appnotes www.national.com/refdesigns www.national.com/samples www.national.com/evalboards www.national.com/packaging www.national.com/quality/green www.national.com/contacts www.national.com/quality www.national.com/feedback www.national.com/easy www.national.com/solutions www.national.com/milaero www.national.com/solarmagic www.national.com/training Applications & Markets Mil/Aero PowerWise® Design University Serial Digital Interface (SDI) www.national.com/sdi www.national.com/wireless www.national.com/tempsensors SolarMagic™ THE CONTENTS OF THIS DOCUMENT ARE PROVIDED IN CONNECTION WITH NATIONAL SEMICONDUCTOR CORPORATION (“NATIONAL”) PRODUCTS. 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