MM54C164 MM74C164 8-Bit Parallel-Out Serial Shift Register
February 1988
MM54C164 MM74C164 8-Bit Parallel-Out Serial Shift Register
General Description
The MM54C164 MM74C164 shift registers are a monolithic complementary MOS (CMOS) integrated circuit constructed with N- and P-channel enhancement transistors These 8-bit shift registers have gated serial inputs and clear Each register bit is a D-type master slave flip-flop A high-level input enables the other input which will then determine the state of the flip-flop Data is serially shifted in and out of the 8-bit register during the positive going transition of clock pulse Clear is independent of the clock and accomplished by a low level at the clear input All inputs are protected against electrostatic effects
Features
Y Y Y Y Y
Supply voltage range Tenth power TTL compatible High noise immunity Low power Medium speed operation
3V to 15V drive 2 LPTTL loads 0 45 VCC (typ ) 50 nW (typ ) 0 8 MHz (typ ) with 10V supply
Applications
Y Y Y Y
Data terminals Instrumentation Medical electronics Alarm systems
Y Y Y
Industrial electronics Remote metering Computers
Truth Table
Serial Inputs A and B Inputs tn A 1 0 1 0 B 1 1 0 0 Output tn a 1 QA 1 0 0 0
Connection Diagram
Dual-In-Line Package
TL F 5896 – 2
Top View Order Number MM54C164 or MM74C164
Block Diagram
TL F 5896 – 1
C1995 National Semiconductor Corporation
TL F 5896
RRD-B30M105 Printed in U S A
Absolute Maximum Ratings (Note 1)
If Military Aerospace specified devices are required please contact the National Semiconductor Sales Office Distributors for availability and specifications Voltage at Any Pin Operating Temperature Range MM54C164 MM74C164
b 0 3V to VCC a 0 3V b 55 C to a 125 C b 40 C to a 85 C
Storage Temperature Range Absolute Maximum VCC Power Dissipation (PD) Dual-In-Line Small Outline Operating VCC Range Lead Temperature (soldering 10 sec )
b 65 C to a 150 C
18V 700 mW 500 mW 3V to 15V 260 C
DC Electrical Characteristics Min
Symbol CMOS TO CMOS VIN(1) VIN(0) VOUT(1) VOUT(0) IIN(1) IIN(0) ICC Logical ‘‘1’’ Input Voltage Logical ‘‘0’’ Input Voltage Logical ‘‘1’’ Output Voltage Logical ‘‘0’’ Output Voltage Logical ‘‘1’’ Input Current Logical ‘‘0’’ Input Current Supply Current Parameter
Max limits apply across temperature range unless otherwise noted Conditions Min Typ Max Units
VCC e 5V VCC e 10V VCC e 5V VCC e 10V VCC e 5V IO e b10 mA VCC e 10V IO e b10 mA VCC e 5V IO e a 10 mA VCC e 10V IO e a 10 mA VCC e 15V VIN e 15V VCC e 15V VIN e 0V VCC e 15V
35 80 15 20 45 90 05 10 0 005
b1 0 b 0 005
V V V V V V V V mA mA 300 mA
10
0 05
CMOS TO LPTTL INTERFACE VIN(1) VIN(0) VOUT(1) VOUT(0) Logical ‘‘1’’ Input Voltage Logical ‘‘0’’ Input Voltage Logical ‘‘1’’ Output Voltage Logical ‘‘0’’ Output Voltage 54C VCC e 4 5V 74C VCC e 4 75V 54C VCC e 4 5V 74C VCC e 4 75V 54C VCC e 4 5V IO e b360 mA 74C VCC e 4 75V IO e b360 mA 54C VCC e 4 5V IO e 360 mA 74C VCC e 4 75V IO e 360 mA 24 24 04 04 VCC b 1 5 VCC b 1 5 08 08 V V V V V V V V
OUTPUT DRIVE (See 54C 74C Family Characteristics Data Sheet) (Short Circuit Current) ISOURCE ISOURCE ISINK ISINK Output Source Current Output Source Current Output Sink Current Output Sink Current VCC e 5V VIN(0) e 0V TA e 25 C VOUT e 0V VCC e 10V VIN(0) e 0V TA e 25 C VOUT e 0V VCC e 5V VIN(1) e 5V TA e 25 C VOUT e VCC VCC e 10V VIN(1) e 10V TA e 25 C VOUT e VCC
b 1 75 b8 0
mA mA mA mA
1 75 80
Note 1 ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed Except for ‘‘Operating Temperature Range’’ they are not meant to imply that the devices should be operated at these limits The table of ‘‘Electrical Characteristics’’ provides conditions for actual device operation
2
AC Electrical Characteristics
Symbol tpd1 tpd0 tS tH fMAX tW tr tf CIN CPD Parameter
TA e 25 C CL e 50 pF unless otherwise noted Conditions VCC e 5V VCC e 10V VCC e 5V VCC e 10V VCC e 5V VCC e 10V VCC e 5V VCC e 10V VCC e 5V VCC e 10V VCC e 5V VCC e 10V VCC e 5V VCC e 10V Any Input (Note 2) (Note 3) 15 5 5 140 200 80 0 0 20 55 Min Typ 230 90 280 110 110 30 0 0 3 8 150 55 250 90 Max 310 120 380 150 Units ns ns ns ns ns ns ns ns MHz MHz ns ns ms ms pF pF
Propagation Delay Time to a Logical ‘‘0’’ or a Logical ‘‘1’’ from Clock to Q Propagation Delay Time to a Logical ‘‘0’’ from Clear to Q Time Prior to Clock Pulse that Data Must be Present Time After Clock Pulse that Data Must be Held Maximum Clock Frequency Minimum Clear Pulse Width Maximum Clock Rise and Fall Time Input Capacitance Power Dissipation Capacitance
AC Parameters are guaranteed by DC correlated testing Note 2 Capacitance is guaranteed by periodic testing Note 3 CPD determines the no load AC power consumption of any CMOS device For complete explanation see 54C 74C Family Characteristics application note AN-90
Logic Waveforms
TL F 5896 – 3
3
Switching Time Waveforms
CMOS to CMOS TTL to CMOS
TL F 5896 – 4
TL F 5896 – 5
tr e tf e 20 ns
AC Test Circuit
TL F 5896 – 6
Typical Applications
74C Compatibility Guaranteed Noise Margin as a Function of VCC
TL F 5896 – 7
TL F 5896 – 8
4
Physical Dimensions inches (millimeters)
Ceramic Dual-In-Line Package (J) Order Number MM54C164J or MM74C164J NS Package Number J14A
5
MM54C164 MM74C164 8-Bit Parallel-Out Serial Shift Register
Physical Dimensions inches (millimeters)
Molded Dual-In-Line Package (N) Order Number MM54C164N or MM74C164N NS Package Number N14A
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